1 /* $NetBSD: r8a77980-cpg-mssr.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ */ 4 /* 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 9 #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 10 11 #include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13 /* r8a77980 CPG Core Clocks */ 14 #define R8A77980_CLK_Z2 0 15 #define R8A77980_CLK_ZR 1 16 #define R8A77980_CLK_ZTR 2 17 #define R8A77980_CLK_ZTRD2 3 18 #define R8A77980_CLK_ZT 4 19 #define R8A77980_CLK_ZX 5 20 #define R8A77980_CLK_S0D1 6 21 #define R8A77980_CLK_S0D2 7 22 #define R8A77980_CLK_S0D3 8 23 #define R8A77980_CLK_S0D4 9 24 #define R8A77980_CLK_S0D6 10 25 #define R8A77980_CLK_S0D12 11 26 #define R8A77980_CLK_S0D24 12 27 #define R8A77980_CLK_S1D1 13 28 #define R8A77980_CLK_S1D2 14 29 #define R8A77980_CLK_S1D4 15 30 #define R8A77980_CLK_S2D1 16 31 #define R8A77980_CLK_S2D2 17 32 #define R8A77980_CLK_S2D4 18 33 #define R8A77980_CLK_S3D1 19 34 #define R8A77980_CLK_S3D2 20 35 #define R8A77980_CLK_S3D4 21 36 #define R8A77980_CLK_LB 22 37 #define R8A77980_CLK_CL 23 38 #define R8A77980_CLK_ZB3 24 39 #define R8A77980_CLK_ZB3D2 25 40 #define R8A77980_CLK_ZB3D4 26 41 #define R8A77980_CLK_SD0H 27 42 #define R8A77980_CLK_SD0 28 43 #define R8A77980_CLK_RPC 29 44 #define R8A77980_CLK_RPCD2 30 45 #define R8A77980_CLK_MSO 31 46 #define R8A77980_CLK_CANFD 32 47 #define R8A77980_CLK_CSI0 33 48 #define R8A77980_CLK_CP 34 49 #define R8A77980_CLK_CPEX 35 50 #define R8A77980_CLK_R 36 51 #define R8A77980_CLK_OSC 37 52 53 #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ 54
Indexes created Mon Oct 06 21:09:46 GMT 2025