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    Searched defs:READ_REG (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/arch/mips/sibyte/dev/
sbbuswatch.c 43 #define READ_REG(rp) mips3_ld((register_t)(rp))
51 (void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
75 bus_err_status = READ_REG(
81 l2_errors = READ_REG(
86 mem_io_errors = READ_REG(
sbwdog.c 81 #define READ_REG(rp) (mips3_ld((register_t)(rp)))
sbtimer.c 61 #define READ_REG(rp) mips3_ld((register_t)(rp))
160 if (G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))) == 0) {
sbjcn.c 238 #define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp)))
1051 while (((reg = READ_REG(ch->ch_input_reg)) != 0) && --timo)
1473 inbuf = READ_REG(ch->ch_input_reg);
1515 while ((ctrl_val = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_CONTROL))) == 0)
1561 inbuf = READ_REG(MIPS_PHYS_TO_KSEG1(sbjcn_cons_addr + JTAG_CONS_INPUT));
sbscn.c 247 #define READ_REG(rp) (mips3_ld((register_t)(rp)))
255 ((~READ_REG(MIPS_PHYS_TO_KSEG1((ch)->ch_sc->sc_addr + 0x280))) & (ch)->ch_i_mask)
1139 while (ISSET(READ_REG(ch->ch_base + 0x20), 0x01)
1146 READ_REG(ch->ch_base + 0x60);
1266 while (ch->ch_tbc && READ_REG(ch->ch_base + 0x20) & 0x04) {
1489 isr = READ_REG(ch->ch_isr_base) & ch->ch_imr;
1502 sr = READ_REG(ch->ch_base + 0x20);
1509 (void)READ_REG(ch->ch_base + 0x60);
1516 (void)READ_REG(ch->ch_base + 0x60);
1526 put[0] = READ_REG(ch->ch_base + 0x60)
    [all...]
  /src/sys/arch/evbmips/sbmips/
cpu.c 58 #define READ_REG(rp) mips3_ld((register_t)(rp))
81 part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
107 plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sb1250_icu.c 93 #define READ_REG(rp) mips3_ld((register_t)(rp))
197 mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
268 u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
312 sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
rtc.c 420 #define READ_REG(rp) mips3_ld((register_t)(MIPS_PHYS_TO_KSEG1(rp)))
443 status = READ_REG(reg);
524 err = READ_REG(reg);
  /src/sys/arch/sbmips/sbmips/
cpu.c 57 #define READ_REG(rp) mips3_ld((register_t)(rp))
80 part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
106 plldiv = G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG)));
sb1250_icu.c 93 #define READ_REG(rp) mips3_ld((register_t)(rp))
197 mbox_mask = READ_REG(cpu->sb1cpu_imr_base + R_IMR_MAILBOX_CPU);
268 u_int sys_part = G_SYS_PART(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_REVISION)));
312 sstatus &= READ_REG(imr_base + R_IMR_INTERRUPT_SOURCE_STATUS);
rtc.c 420 #define READ_REG(rp) mips3_ld((register_t)(MIPS_PHYS_TO_KSEG1(rp)))
443 status = READ_REG(reg);
524 err = READ_REG(reg);
  /src/sys/arch/arm/imx/
imxspi.c 72 #define READ_REG(sc, x) \
143 contrl = READ_REG(sc, CONREG);
192 contrl = READ_REG(sc, CONREG);
243 if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF))
260 if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN)))
261 WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH));
273 if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR))))
277 data = READ_REG(sc, RXDATA);
310 chipselect = READ_REG(sc, CONREG);
357 if ((intr = READ_REG(sc, INTREG)) == 0)
    [all...]
  /src/sys/arch/hppa/gsc/
harmonyvar.h 113 #define READ_REG(sc, reg) \
  /src/sys/dev/pci/
ubsec.c 138 #define READ_REG(sc,r) \
528 ctrl = READ_REG(sc, BS_CTRL);
645 stat = READ_REG(sc, BS_STAT);
773 volatile u_int32_t a = READ_REG(sc, BS_ERR);
843 if ((stat = READ_REG(sc, BS_STAT))
909 if ((stat = READ_REG(sc, BS_STAT))
1871 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1899 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR4_FULL)
2179 ctrl = READ_REG(sc, BS_CTRL);
2205 ctrl = READ_REG(sc, BS_CTRL)
    [all...]
if_txpreg.h 629 #define READ_REG(sc,reg) \

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