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    Searched defs:REGISTERS (Results 1 - 2 of 2) sorted by relevancy

  /src/external/gpl3/gdb.old/dist/sim/mips/
sim-main.h 68 /* FPU registers must be one of the following types. All other values
110 /* For some MIPS targets, the HI/LO registers have certain timing
189 destinations, schedule two writes. For floating point registers,
326 vector of registers. The internal simulator engine then uses
329 unsigned_word registers[LAST_EMBED_REGNUM + 1]; member in struct:mips_sim_cpu
332 #define REGISTERS (MIPS_SIM_CPU (CPU)->registers)
334 #define GPR (&REGISTERS[0])
335 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
337 #define LO (REGISTERS[33]
    [all...]
  /src/external/gpl3/gdb/dist/sim/mips/
sim-main.h 68 /* FPU registers must be one of the following types. All other values
110 /* For some MIPS targets, the HI/LO registers have certain timing
189 destinations, schedule two writes. For floating point registers,
326 vector of registers. The internal simulator engine then uses
329 unsigned_word registers[LAST_EMBED_REGNUM + 1]; member in struct:mips_sim_cpu
332 #define REGISTERS (MIPS_SIM_CPU (CPU)->registers)
334 #define GPR (&REGISTERS[0])
335 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
337 #define LO (REGISTERS[33]
    [all...]

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