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    Searched defs:REG_WRITE (Results 1 - 16 of 16) sorted by relevancy

  /src/sys/dev/goldfish/
gfpic.c 56 #define REG_WRITE(sc, r, v) \
69 REG_WRITE(sc, GFPIC_DISABLE_ALL, 0);
82 REG_WRITE(sc, GFPIC_ENABLE, (1U << pirq));
95 REG_WRITE(sc, GFPIC_DISABLE, (1U << pirq));
gftty.c 79 #define REG_WRITE(sc, r, v) REG_WRITE0((sc)->sc_config, (r), (v))
313 REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);
346 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
357 REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);
390 REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);
471 REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);
487 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
527 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
653 REG_WRITE(sc, GFTTY_CMD, CMD_WRITE_BUFFER);
  /src/sys/arch/virt68k/dev/
virtctrl.c 66 #define REG_WRITE(sc, r, v) \
79 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_PANIC);
81 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_HALT);
83 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_RESET);
  /src/sys/arch/mips/adm5120/
adm5120_intr.c 159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
181 REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK);
219 REG_WRITE(ICU_MODE_REG,
222 REG_WRITE(ICU_MODE_REG,
226 REG_WRITE(ICU_ENABLE_REG, irqmask);
257 REG_WRITE(ICU_DISABLE_REG, irqmask);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/
dmub_reg.h 55 #define REG_WRITE(reg, val) \
56 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
  /src/sys/arch/mips/adm5120/dev/
uart.c 55 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
145 REG_WRITE(UART_CR_REG,UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN);
340 REG_WRITE(UART_ECR_REG, UART_ECR_RSR);
if_admsw.c 165 #define REG_WRITE(o, v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
224 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
225 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
226 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
227 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
242 REG_WRITE(VLAN_G1_REG, i);
244 REG_WRITE(VLAN_G2_REG, i);
253 REG_WRITE(PORT_CONF0_REG,
255 REG_WRITE(CPUP_CONF_REG,
266 REG_WRITE(PHY_CNTL2_REG
    [all...]
ahci.c 245 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
291 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* disable interrupts */
292 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_SW_RESET); /* reset */
297 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_HOST_EN);
298 REG_WRITE(ADMHCD_REG_HOSTHEAD, 0x00000000);
299 REG_WRITE(ADMHCD_REG_FMINTERVAL, 0x20002edf);
300 REG_WRITE(ADMHCD_REG_LSTHRESH, 0x628);
301 REG_WRITE(ADMHCD_REG_RHDESCR, ADMHCD_NPS | ADMHCD_LPSC);
302 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
304 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* XXX: enable interrupts *
    [all...]
  /src/external/gpl3/binutils/dist/opcodes/
arc-ext.h 75 REG_WRITE,
  /src/external/gpl3/binutils.old/dist/opcodes/
arc-ext.h 75 REG_WRITE,
  /src/external/gpl3/gdb.old/dist/opcodes/
arc-ext.h 75 REG_WRITE,
  /src/external/gpl3/gdb/dist/opcodes/
arc-ext.h 75 REG_WRITE,
  /src/sys/arch/hb68k/pg68k/
pgtimer.c 66 #define REG_WRITE(sc, r, v) \
105 REG_WRITE(sc, TIMER_VAL, (uint8_t)(ticks >> 8));
106 REG_WRITE(sc, TIMER_VAL, (uint8_t)ticks);
107 REG_WRITE(sc, TIMER_CSR, CSR_ENAB);
186 REG_WRITE(sc, TIMER_CSR, 0);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
reg_helper.h 44 #define REG_WRITE(reg_name, value) \
  /src/sys/external/isc/atheros_hal/dist/ar5312/
ar5312reg.h 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val);
  /src/sys/dev/pcmcia/
if_ray.c 383 #define REG_WRITE(sc, off, val) \
426 #define RAY_ECF_START_CMD(sc) REG_WRITE(sc, RAY_ECFIR, RAY_ECSIR_IRQ)
543 REG_WRITE(sc, RAY_HCSIR, 0);
758 REG_WRITE(sc, RAY_HCSIR, 0);
2040 REG_WRITE(sc, RAY_HCSIR, 0);

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