Lines Matching defs:REG_WRITE
245 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
291 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* disable interrupts */
292 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_SW_RESET); /* reset */
297 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_HOST_EN);
298 REG_WRITE(ADMHCD_REG_HOSTHEAD, 0x00000000);
299 REG_WRITE(ADMHCD_REG_FMINTERVAL, 0x20002edf);
300 REG_WRITE(ADMHCD_REG_LSTHRESH, 0x628);
301 REG_WRITE(ADMHCD_REG_RHDESCR, ADMHCD_NPS | ADMHCD_LPSC);
302 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
304 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* XXX: enable interrupts */
603 #define WPS(x) REG_WRITE(ADMHCD_REG_PORTSTATUS0+(index-1)*4, (x))
694 #define WPS(x) REG_WRITE(ADMHCD_REG_PORTSTATUS0+(index-1)*4, (x))
929 REG_WRITE(ADMHCD_REG_HOSTHEAD, (uint32_t)ep);
930 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP | ADMHCD_DMA_EN);
963 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
1248 REG_WRITE(ADMHCD_REG_HOSTHEAD, (uint32_t)ep);
1249 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP | ADMHCD_DMA_EN);
1277 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);