| /src/sys/arch/aarch64/aarch64/ |
| trap.c | 683 int Rn, Rd, Rm, error;
685 Rn = __SHIFTOUT(insn, 0x000f0000);
689 vaddr = tf->tf_reg[Rn] & 0xffffffff;
|
| /src/external/gpl3/gdb/dist/sim/arm/ |
| thumbemu.c | 267 case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
269 ARMword Rn = tBITS (0, 3);
277 * ainstr |= (Rn << 16);
289 ARMword Rn = tBITS (0, 3);
296 address = state->Reg[Rn] + state->Reg[Rm] * 2;
302 address = state->Reg[Rn] + state->Reg[Rm];
320 ARMword Rn = tBITS (0, 3);
334 if (Rn == 15)
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8
[all...] |
| armemu.c | 274 ARMword Rn;
339 Rn = BITS (16, 19);
342 if (Rd == 15 || Rn == 15 || Rm == 15)
345 val1 = state->Reg[Rn];
350 case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
374 case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
410 case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
446 case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
470 case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
494 case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. *
[all...] |
| iwmmxt.c | 672 ARMdword Rn;
682 Rn = state->Reg [BITS (12, 15)];
684 Rn &= 0xfffffffc;
691 Rn &= 0xff;
692 wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
693 | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/arm/ |
| thumbemu.c | 267 case 0x29: // TST<c>.W <Rn>,<Rm>{,<shift>}
269 ARMword Rn = tBITS (0, 3);
277 * ainstr |= (Rn << 16);
289 ARMword Rn = tBITS (0, 3);
296 address = state->Reg[Rn] + state->Reg[Rm] * 2;
302 address = state->Reg[Rn] + state->Reg[Rm];
320 ARMword Rn = tBITS (0, 3);
334 if (Rn == 15)
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8
[all...] |
| armemu.c | 274 ARMword Rn;
339 Rn = BITS (16, 19);
342 if (Rd == 15 || Rn == 15 || Rm == 15)
345 val1 = state->Reg[Rn];
350 case 0xF1: /* QADD16<c> <Rd>,<Rn>,<Rm>. */
374 case 0xF3: /* QASX<c> <Rd>,<Rn>,<Rm>. */
410 case 0xF5: /* QSAX<c> <Rd>,<Rn>,<Rm>. */
446 case 0xF7: /* QSUB16<c> <Rd>,<Rn>,<Rm>. */
470 case 0xF9: /* QADD8<c> <Rd>,<Rn>,<Rm>. */
494 case 0xFF: /* QSUB8<c> <Rd>,<Rn>,<Rm>. *
[all...] |
| iwmmxt.c | 672 ARMdword Rn;
682 Rn = state->Reg [BITS (12, 15)];
684 Rn &= 0xfffffffc;
691 Rn &= 0xff;
692 wR [wRd] = (Rn << 56) | (Rn << 48) | (Rn << 40) | (Rn << 32)
693 | (Rn << 24) | (Rn << 16) | (Rn << 8) | Rn
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 927 // [Rn, Rm]
929 // {2-0} = Rn
932 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
934 return (Rm << 3) | Rn;
997 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1063 // {6-3} Rn
1068 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1073 return (Rn << 3) | Qm;
1122 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1254 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg())
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
473 assert(isARMLowRegister(Rn));
481 .addReg(Rn, RegState::Define)
482 .addReg(Rn)
|
| ARMBaseInstrInfo.cpp | 2520 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
3560 Register Rn = MI.getOperand(2).getReg();
3565 return (Rt == Rn) ? 3 : 2;
3586 Register Rn = MI.getOperand(3).getReg();
3591 return (Rt == Rn) ? 4 : 3;
3596 Register Rn = MI.getOperand(3).getReg();
3597 return (Rt == Rn) ? 4 : 3;
3633 Register Rn = MI.getOperand(2).getReg();
3634 return (Rt == Rn) ? 3 : 2;
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| tic30.h | 190 #define Rn 0x0001
209 #define GAddr1 Rn | Direct | Indirect | Imm16
211 #define TAddr1 op3T1 | Rn | Indirect
212 #define TAddr2 op3T2 | Rn | Indirect
213 #define Reg Rn | ARn
247 { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
251 { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
252 { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
347 { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
408 { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 890 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
895 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
898 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
981 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1009 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1030 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1076 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1127 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1137 unsigned Rn = fieldFromInstruction(insn, 5, 5);
1195 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 1579 // Writeback not allowed if Rn is in the target list.
1673 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1848 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1908 if (writeback && (Rn == 15 || Rn == Rt))
1953 unsigned Rn = fieldFromInstruction(Val, 13, 4)
[all...] |
| /src/external/gpl3/gdb/dist/sim/sh/ |
| interp.c | 119 #define Rn saved_state.asregs.regs[n]
334 The compiler generates "add #0,rn" insns to mark registers as invalid,
1157 dmul_s (uint32_t rm, uint32_t rn)
1159 int64_t res = (int64_t)(int32_t)rm * (int64_t)(int32_t)rn;
1165 dmul_u (uint32_t rm, uint32_t rn)
1167 uint64_t res = (uint64_t)(uint32_t)rm * (uint64_t)(uint32_t)rn;
1910 sh_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
1916 switch (rn)
1924 saved_state.asregs.regs[rn] = val;
1959 SET_FI (rn - SIM_SH_FR0_REGNUM, val)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/sh/ |
| interp.c | 119 #define Rn saved_state.asregs.regs[n]
334 The compiler generates "add #0,rn" insns to mark registers as invalid,
1157 dmul_s (uint32_t rm, uint32_t rn)
1159 int64_t res = (int64_t)(int32_t)rm * (int64_t)(int32_t)rn;
1165 dmul_u (uint32_t rm, uint32_t rn)
1167 uint64_t res = (uint64_t)(uint32_t)rm * (uint64_t)(uint32_t)rn;
1910 sh_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length)
1916 switch (rn)
1924 saved_state.asregs.regs[rn] = val;
1959 SET_FI (rn - SIM_SH_FR0_REGNUM, val)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 4209 unsigned Rn = Inst.getOperand(3).getReg();
4210 if (RI->isSubRegisterEq(Rn, Rt))
4213 if (RI->isSubRegisterEq(Rn, Rt2))
4255 unsigned Rn = Inst.getOperand(3).getReg();
4256 if (RI->isSubRegisterEq(Rn, Rt))
4259 if (RI->isSubRegisterEq(Rn, Rt2))
4287 unsigned Rn = Inst.getOperand(2).getReg();
4288 if (RI->isSubRegisterEq(Rn, Rt))
4306 unsigned Rn = Inst.getOperand(2).getReg();
4307 if (RI->isSubRegisterEq(Rn, Rt)
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| arm-dis.c | 5645 unsigned long rm, rn;
5647 rn = arm_decode_field (given, 16, 19);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
6274 unsigned long rn = arm_decode_field (given, 16, 19);
6276 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6282 if (rn == 0xf)
6300 unsigned long rn = arm_decode_field (given, 16, 19);
6302 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)
5644 unsigned long rm, rn; local
6273 unsigned long rn = arm_decode_field (given, 16, 19); local
6299 unsigned long rn = arm_decode_field (given, 16, 19); local
6329 unsigned long rn = arm_decode_field (given, 16, 19); local
8036 int rn = (given >> 16) & 0xf; local
8568 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
9075 int rn = ((given >> 16) & 0xf); local
9125 int rn = ((given >> 16) & 0xf); local
9213 int rn = ((given >> 16) & 0xf); local
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| arm-dis.c | 5645 unsigned long rm, rn;
5647 rn = arm_decode_field (given, 16, 19);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
6274 unsigned long rn = arm_decode_field (given, 16, 19);
6276 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6282 if (rn == 0xf)
6300 unsigned long rn = arm_decode_field (given, 16, 19);
6302 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)
5644 unsigned long rm, rn; local
6273 unsigned long rn = arm_decode_field (given, 16, 19); local
6299 unsigned long rn = arm_decode_field (given, 16, 19); local
6329 unsigned long rn = arm_decode_field (given, 16, 19); local
8036 int rn = (given >> 16) & 0xf; local
8568 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
9075 int rn = ((given >> 16) & 0xf); local
9125 int rn = ((given >> 16) & 0xf); local
9213 int rn = ((given >> 16) & 0xf); local
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| arm-dis.c | 5645 unsigned long rm, rn;
5647 rn = arm_decode_field (given, 16, 19);
5649 if (rm == 0xf && rn == 0xf)
5652 else if (rn == rm && rn != 0xf)
6274 unsigned long rn = arm_decode_field (given, 16, 19);
6276 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6282 if (rn == 0xf)
6300 unsigned long rn = arm_decode_field (given, 16, 19);
6302 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)
5644 unsigned long rm, rn; local
6273 unsigned long rn = arm_decode_field (given, 16, 19); local
6299 unsigned long rn = arm_decode_field (given, 16, 19); local
6329 unsigned long rn = arm_decode_field (given, 16, 19); local
8036 int rn = (given >> 16) & 0xf; local
8568 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
9075 int rn = ((given >> 16) & 0xf); local
9125 int rn = ((given >> 16) & 0xf); local
9213 int rn = ((given >> 16) & 0xf); local
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| arm-dis.c | 5741 unsigned long rm, rn;
5743 rn = arm_decode_field (given, 16, 19);
5745 if (rm == 0xf && rn == 0xf)
5748 else if (rn == rm && rn != 0xf)
6370 unsigned long rn = arm_decode_field (given, 16, 19);
6372 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
6378 if (rn == 0xf)
6396 unsigned long rn = arm_decode_field (given, 16, 19);
6398 if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1)
5740 unsigned long rm, rn; local
6369 unsigned long rn = arm_decode_field (given, 16, 19); local
6395 unsigned long rn = arm_decode_field (given, 16, 19); local
6425 unsigned long rn = arm_decode_field (given, 16, 19); local
8132 int rn = (given >> 16) & 0xf; local
8761 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
9268 int rn = ((given >> 16) & 0xf); local
9318 int rn = ((given >> 16) & 0xf); local
9406 int rn = ((given >> 16) & 0xf); local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 5735 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
5740 // If we have a three-operand form, make sure to set Rn to be the operand
7571 unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
7573 if (Rn == Rt || Rn == Rt2) {
7760 // Rt must be different from Rn.
7762 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
7764 if (Rt == Rn)
7773 // Rt must be different from Rn
[all...] |
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-arm.c | 2409 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
5813 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5814 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5815 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5822 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5823 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/
[all...] |
