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  /src/external/gpl3/gdb/dist/sim/testsuite/bfin/
c_comp3op_pr_plus_pr_sh1.s 13 imm32 sp, 0x98761432;
20 SP = P1 + ( SP << 1 );
27 CHECKREG sp, 0xCDED8231;
35 imm32 sp, 0x98765422;
42 SP = P2 + ( SP << 1 );
49 CHECKREG sp, 0x345676C8;
57 imm32 sp, 0x98765433;
64 SP = P3 + ( SP << 1 )
    [all...]
c_comp3op_pr_plus_pr_sh2.s 13 imm32 sp, 0x98761432;
20 SP = P1 + ( SP << 2 );
27 CHECKREG sp, 0x122FE673;
35 imm32 sp, 0x98765422;
42 SP = P2 + ( SP << 2 );
49 CHECKREG sp, 0x12345364;
57 imm32 sp, 0x98765433;
64 SP = P3 + ( SP << 2 )
    [all...]
c_ldimmhalf_lz_pr.s 17 SP = 0x000f (Z);
24 CHECKREG sp, 0x0000000f;
32 SP = 0x00f0 (Z);
40 CHECKREG sp, 0x000000f0;
48 SP = 0x0f00 (Z);
55 CHECKREG sp, 0x00000f00;
63 SP = 0xf000 (Z);
70 CHECKREG sp, 0x0000f000;
c_ldimmhalf_lzhi_pr.s 25 SP = 0x000f (Z);
26 SP.H = 0x000e;
33 CHECKREG sp, 0x000e000f;
47 SP = 0x00f0 (Z);
48 SP.H = 0x00e0;
56 CHECKREG sp, 0x00e000f0;
70 SP = 0x0f00 (Z);
71 SP.H = 0x0e00;
78 CHECKREG sp, 0x0e000f00;
92 SP = 0xf000 (Z)
    [all...]
c_ptr2op_pr_sft_2_1.s 13 imm32 sp, 0xe07c180d;
20 SP = P1 << 2;
27 CHECKREG sp, 0x09212030;
35 imm32 sp, 0xb00c1a0d;
42 SP = P2;
49 CHECKREG sp, 0x26041005;
57 imm32 sp, 0x200c100d;
64 SP = P3 >> 1;
71 CHECKREG sp, 0x0400C200;
79 imm32 sp, 0x700c110d
    [all...]
stk5.s 6 SP += -12;
7 FP = SP;
15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
27 [ -- SP ] = R5;
29 [ -- SP ] = R5;
32 SP = SP + P5;
c_compi2opp_pr_eq_i7_n.s 14 SP = -6;
22 CHECKREG sp, -6;
31 SP = -14;
39 CHECKREG sp, -14;
48 SP = -22;
56 CHECKREG sp, -22;
65 SP = -30;
73 CHECKREG sp, -30;
82 SP = -38;
90 CHECKREG sp, -38
    [all...]
c_compi2opp_pr_eq_i7_p.s 14 SP = 6;
21 CHECKREG sp, 6;
29 SP = 14;
36 CHECKREG sp, 14;
44 SP = 22;
51 CHECKREG sp, 22;
59 SP = 30;
66 CHECKREG sp, 30;
75 SP = 38;
83 CHECKREG sp, 38
    [all...]
c_ptr2op_pr_shadd_1_2.s 18 imm32 sp, 0xe07c180d;
25 SP = ( SP + P1 ) << 2;
32 CHECKREG sp, 0x9432A094;
40 imm32 sp, 0xb00c1a0d;
47 SP = ( SP + P2 ) << 1;
54 CHECKREG sp, 0xC059346A;
62 imm32 sp, 0x200c1b0d;
69 SP = ( SP + P3 ) << 1
    [all...]
c_regmv_imlb_pr.s 21 SP = I1;
29 CHECKREG sp, 0x22222222;
38 SP = I0;
46 CHECKREG sp, 0x11111111;
55 SP = I3;
63 CHECKREG sp, 0x44444444;
72 SP = I2;
80 CHECKREG sp, 0x33333333;
94 SP = M1;
102 CHECKREG sp, 0x66666666
    [all...]
usp.S 21 SP = R6;
26 # SP should now be USP
27 R1 = SP;
31 # Now set SP to another value
32 SP = R5;
38 # SP should be the same as original, but USP should change
39 R1 = SP;
  /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/
c_comp3op_pr_plus_pr_sh1.s 13 imm32 sp, 0x98761432;
20 SP = P1 + ( SP << 1 );
27 CHECKREG sp, 0xCDED8231;
35 imm32 sp, 0x98765422;
42 SP = P2 + ( SP << 1 );
49 CHECKREG sp, 0x345676C8;
57 imm32 sp, 0x98765433;
64 SP = P3 + ( SP << 1 )
    [all...]
c_comp3op_pr_plus_pr_sh2.s 13 imm32 sp, 0x98761432;
20 SP = P1 + ( SP << 2 );
27 CHECKREG sp, 0x122FE673;
35 imm32 sp, 0x98765422;
42 SP = P2 + ( SP << 2 );
49 CHECKREG sp, 0x12345364;
57 imm32 sp, 0x98765433;
64 SP = P3 + ( SP << 2 )
    [all...]
c_ldimmhalf_lz_pr.s 17 SP = 0x000f (Z);
24 CHECKREG sp, 0x0000000f;
32 SP = 0x00f0 (Z);
40 CHECKREG sp, 0x000000f0;
48 SP = 0x0f00 (Z);
55 CHECKREG sp, 0x00000f00;
63 SP = 0xf000 (Z);
70 CHECKREG sp, 0x0000f000;
c_ldimmhalf_lzhi_pr.s 25 SP = 0x000f (Z);
26 SP.H = 0x000e;
33 CHECKREG sp, 0x000e000f;
47 SP = 0x00f0 (Z);
48 SP.H = 0x00e0;
56 CHECKREG sp, 0x00e000f0;
70 SP = 0x0f00 (Z);
71 SP.H = 0x0e00;
78 CHECKREG sp, 0x0e000f00;
92 SP = 0xf000 (Z)
    [all...]
c_ptr2op_pr_sft_2_1.s 13 imm32 sp, 0xe07c180d;
20 SP = P1 << 2;
27 CHECKREG sp, 0x09212030;
35 imm32 sp, 0xb00c1a0d;
42 SP = P2;
49 CHECKREG sp, 0x26041005;
57 imm32 sp, 0x200c100d;
64 SP = P3 >> 1;
71 CHECKREG sp, 0x0400C200;
79 imm32 sp, 0x700c110d
    [all...]
stk5.s 6 SP += -12;
7 FP = SP;
15 [ -- SP ] = ( R7:7, P5:4 );
20 ( R7:7, P5:4 ) = [ SP ++ ];
27 [ -- SP ] = R5;
29 [ -- SP ] = R5;
32 SP = SP + P5;
c_compi2opp_pr_eq_i7_n.s 14 SP = -6;
22 CHECKREG sp, -6;
31 SP = -14;
39 CHECKREG sp, -14;
48 SP = -22;
56 CHECKREG sp, -22;
65 SP = -30;
73 CHECKREG sp, -30;
82 SP = -38;
90 CHECKREG sp, -38
    [all...]
c_compi2opp_pr_eq_i7_p.s 14 SP = 6;
21 CHECKREG sp, 6;
29 SP = 14;
36 CHECKREG sp, 14;
44 SP = 22;
51 CHECKREG sp, 22;
59 SP = 30;
66 CHECKREG sp, 30;
75 SP = 38;
83 CHECKREG sp, 38
    [all...]
c_ptr2op_pr_shadd_1_2.s 18 imm32 sp, 0xe07c180d;
25 SP = ( SP + P1 ) << 2;
32 CHECKREG sp, 0x9432A094;
40 imm32 sp, 0xb00c1a0d;
47 SP = ( SP + P2 ) << 1;
54 CHECKREG sp, 0xC059346A;
62 imm32 sp, 0x200c1b0d;
69 SP = ( SP + P3 ) << 1
    [all...]
c_regmv_imlb_pr.s 21 SP = I1;
29 CHECKREG sp, 0x22222222;
38 SP = I0;
46 CHECKREG sp, 0x11111111;
55 SP = I3;
63 CHECKREG sp, 0x44444444;
72 SP = I2;
80 CHECKREG sp, 0x33333333;
94 SP = M1;
102 CHECKREG sp, 0x66666666
    [all...]
usp.S 21 SP = R6;
26 # SP should now be USP
27 R1 = SP;
31 # Now set SP to another value
32 SP = R5;
38 # SP should be the same as original, but USP should change
39 R1 = SP;
  /src/external/apache2/llvm/dist/llvm/tools/opt/
BreakpointPrinter.cpp 46 if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.sp"))
49 auto *SP = cast_or_null<DISubprogram>(NMD->getOperand(i));
50 if (!SP)
52 getContextName(SP->getScope(), Name);
53 Name = Name + SP->getName().str();
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
PseudoProbePrinter.cpp 58 const DISubprogram *SP = InlinedAt->getScope()->getSubprogram();
60 auto Name = SP->getLinkageName();
62 Name = SP->getName();
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFrameLowering.cpp 56 // Offset - offset from sp after stack allocation on function prologue
58 // The sp is the stack pointer subtracted/added from the stack size
67 // sw REGX, 4(SP)
72 // lw REGX, 16+StackSize(SP)
112 // from $sp so that it can be determined if an emergency spill slot for stack
140 unsigned SP = STI.getABI().IsN64() ? Mips::SP_64 : Mips::SP;
147 STI.getInstrInfo()->adjustStackPtr(SP, Amount, MBB, I);

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