1 /* $NetBSD: esp_isa.c,v 1.38 2026/01/02 23:33:58 nia Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994 Peter Galbavy 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 50 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 51 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 52 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 53 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 56 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 57 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * Based on aic6360 by Jarle Greipsland 63 * 64 * Acknowledgements: Many of the algorithms used in this driver are 65 * inspired by the work of Julian Elischer (julian (at) tfs.com) and 66 * Charles Hannum (mycroft (at) duality.gnu.ai.mit.edu). Thanks a million! 67 */ 68 69 /* 70 * Initial m68k mac support from Allen Briggs <briggs (at) macbsd.com> 71 * (basically consisting of the match, a bit of the attach, and the 72 * "DMA" glue functions). 73 */ 74 75 /* 76 * Copyright (c) 1997 Eric S. Hvozda (hvozda (at) netcom.com) 77 * All rights reserved. 78 * 79 * Redistribution and use in source and binary forms, with or without 80 * modification, are permitted provided that the following conditions 81 * are met: 82 * 1. Redistributions of source code must retain the above copyright 83 * notice, this list of conditions and the following disclaimer. 84 * 2. Redistributions in binary form must reproduce the above copyright 85 * notice, this list of conditions and the following disclaimer in the 86 * documentation and/or other materials provided with the distribution. 87 * 3. All advertising materials mentioning features or use of this software 88 * must display the following acknowledgement: 89 * This product includes software developed by Eric S. Hvozda. 90 * 4. The name of Eric S. Hvozda may not be used to endorse or promote products 91 * derived from this software without specific prior written permission. 92 * 93 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 94 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 95 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 96 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 97 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 98 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 99 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 100 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 101 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 102 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 103 */ 104 105 #include <sys/cdefs.h> 106 __KERNEL_RCSID(0, "$NetBSD: esp_isa.c,v 1.38 2026/01/02 23:33:58 nia Exp $"); 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/device.h> 111 #include <sys/buf.h> 112 113 #include <sys/bus.h> 114 #include <sys/intr.h> 115 116 #include <dev/scsipi/scsipi_all.h> 117 #include <dev/scsipi/scsi_all.h> 118 #include <dev/scsipi/scsiconf.h> 119 120 #include <dev/isa/isavar.h> 121 #include <dev/isa/isadmavar.h> 122 123 #include <dev/ic/ncr53c9xreg.h> 124 #include <dev/ic/ncr53c9xvar.h> 125 126 #include <dev/isa/esp_isavar.h> 127 128 int esp_isa_match(device_t, cfdata_t, void *); 129 void esp_isa_attach(device_t, device_t, void *); 130 131 CFATTACH_DECL_NEW(esp_isa, sizeof(struct esp_isa_softc), 132 esp_isa_match, esp_isa_attach, NULL, NULL); 133 134 int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */ 135 136 /* 137 * Functions and the switch for the MI code. 138 */ 139 uint8_t esp_isa_read_reg(struct ncr53c9x_softc *, int); 140 void esp_isa_write_reg(struct ncr53c9x_softc *, int, uint8_t); 141 int esp_isa_dma_isintr(struct ncr53c9x_softc *); 142 void esp_isa_dma_reset(struct ncr53c9x_softc *); 143 int esp_isa_dma_intr(struct ncr53c9x_softc *); 144 int esp_isa_dma_setup(struct ncr53c9x_softc *, uint8_t **, 145 size_t *, int, size_t *); 146 void esp_isa_dma_go(struct ncr53c9x_softc *); 147 void esp_isa_dma_stop(struct ncr53c9x_softc *); 148 int esp_isa_dma_isactive(struct ncr53c9x_softc *); 149 150 struct ncr53c9x_glue esp_isa_glue = { 151 esp_isa_read_reg, 152 esp_isa_write_reg, 153 esp_isa_dma_isintr, 154 esp_isa_dma_reset, 155 esp_isa_dma_intr, 156 esp_isa_dma_setup, 157 esp_isa_dma_go, 158 esp_isa_dma_stop, 159 esp_isa_dma_isactive, 160 NULL, /* gl_clear_latched_intr */ 161 }; 162 163 /* 164 * Look for the board 165 */ 166 int 167 esp_isa_find(bus_space_tag_t iot, bus_space_handle_t ioh, 168 struct esp_isa_probe_data *epd) 169 { 170 u_int vers; 171 u_int p1; 172 u_int p2; 173 u_int jmp; 174 175 ESP_TRACE(("[esp_isa_find] ")); 176 177 /* reset card before we probe? */ 178 179 epd->sc_cfg4 = NCRCFG4_ACTNEG; 180 epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC; 181 182 /* 183 * Switch to the PIO regs and look for the bit pattern 184 * we expect... 185 */ 186 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 187 188 #define SIG_MASK 0x87 189 #define REV_MASK 0x70 190 #define M1 0x02 191 #define M2 0x05 192 #define ISNCR 0x80 193 #define ISESP406 0x40 194 195 vers = bus_space_read_1(iot, ioh, NCR_SIGNTR); 196 p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 197 p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK; 198 199 ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2)); 200 201 if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1))) 202 return 0; 203 204 /* Ok, what is it? */ 205 epd->sc_isncr = (vers & ISNCR); 206 epd->sc_rev = ((vers & REV_MASK) == ISESP406) ? 207 NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408; 208 209 /* What do the jumpers tell us? */ 210 jmp = bus_space_read_1(iot, ioh, NCR_JMP); 211 212 epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000; 213 epd->sc_parity = jmp & NCRJMP_J2; 214 epd->sc_sync = jmp & NCRJMP_J4; 215 epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6; 216 switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) { 217 case NCRJMP_J0 | NCRJMP_J1: 218 epd->sc_irq = 11; 219 break; 220 case NCRJMP_J0: 221 epd->sc_irq = 10; 222 break; 223 case NCRJMP_J1: 224 epd->sc_irq = 15; 225 break; 226 default: 227 epd->sc_irq = 12; 228 break; 229 } 230 231 bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5); 232 233 /* Try to set NCRESPCFG3_FCLK, some FAS408's don't support 234 * NCRESPCFG3_FCLK even though it is documented. A bad 235 * batch of chips perhaps? 236 */ 237 bus_space_write_1(iot, ioh, NCR_ESPCFG3, 238 bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK); 239 epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3) 240 & NCRESPCFG3_FCLK; 241 242 return 1; 243 } 244 245 void 246 esp_isa_init(struct esp_isa_softc *esc, struct esp_isa_probe_data *epd) 247 { 248 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 249 250 ESP_TRACE(("[esp_isa_init] ")); 251 252 /* 253 * Set up the glue for MI code early; we use some of it here. 254 */ 255 sc->sc_glue = &esp_isa_glue; 256 257 sc->sc_rev = epd->sc_rev; 258 sc->sc_id = epd->sc_id; 259 260 /* If we could set NCRESPCFG3_FCLK earlier, we can really move */ 261 sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3); 262 if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) { 263 sc->sc_freq = 40; 264 sc->sc_cfg3 |= NCRESPCFG3_FCLK; 265 } else 266 sc->sc_freq = 24; 267 268 /* Setup the register defaults */ 269 sc->sc_cfg1 = sc->sc_id; 270 if (epd->sc_parity) 271 sc->sc_cfg1 |= NCRCFG1_PARENB; 272 sc->sc_cfg2 = NCRCFG2_SCSI2; 273 sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI; 274 sc->sc_cfg4 = epd->sc_cfg4; 275 sc->sc_cfg5 = epd->sc_cfg5; 276 277 /* 278 * This is the value used to start sync negotiations 279 * Note that the NCR register "SYNCTP" is programmed 280 * in "clocks per byte", and has a minimum value of 4. 281 * The SCSI period used in negotiation is one-fourth 282 * of the time (in nanoseconds) needed to transfer one byte. 283 * Since the chip's clock is given in MHz, we have the following 284 * formula: 4 * period = (1000 / freq) * 4 285 */ 286 if (epd->sc_sync) { 287 #ifdef DIAGNOSTIC 288 aprint_normal_dev(sc->sc_dev, 289 "sync requested, but not supported; will do async\n"); 290 #endif 291 epd->sc_sync = 0; 292 } 293 294 sc->sc_minsync = 0; 295 296 /* Really no limit, but since we want to fit into the TCR... */ 297 sc->sc_maxxfer = 64 * 1024; 298 } 299 300 /* 301 * Check the slots looking for a board we recognise 302 * If we find one, note its address (slot) and call 303 * the actual probe routine to check it out. 304 */ 305 int 306 esp_isa_match(device_t parent, cfdata_t cf, void *aux) 307 { 308 struct isa_attach_args *ia = aux; 309 bus_space_tag_t iot = ia->ia_iot; 310 bus_space_handle_t ioh; 311 struct esp_isa_probe_data epd; 312 int rv; 313 314 if (ia->ia_nio < 1) 315 return 0; 316 if (ia->ia_nirq < 1) 317 return 0; 318 if (ia->ia_ndrq < 1) 319 return 0; 320 321 if (ISA_DIRECT_CONFIG(ia)) 322 return 0; 323 324 ESP_TRACE(("[esp_isa_match] ")); 325 326 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 327 return 0; 328 329 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) 330 return 0; 331 332 rv = esp_isa_find(iot, ioh, &epd); 333 334 bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE); 335 336 if (rv) { 337 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 338 ia->ia_irq[0].ir_irq != epd.sc_irq) { 339 #ifdef DIAGNOSTIC 340 printf("%s: configured IRQ (%0d) does not " 341 "match board IRQ (%0d), device not configured\n", 342 __func__, ia->ia_irq[0].ir_irq, epd.sc_irq); 343 #endif 344 return 0; 345 } 346 ia->ia_irq[0].ir_irq = epd.sc_irq; 347 ia->ia_iomem[0].ir_size = 0; 348 ia->ia_io[0].ir_size = ESP_ISA_IOSIZE; 349 } 350 return rv; 351 } 352 353 /* 354 * Attach this instance, and then all the sub-devices 355 */ 356 void 357 esp_isa_attach(device_t parent, device_t self, void *aux) 358 { 359 struct esp_isa_softc *esc = device_private(self); 360 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 361 struct isa_attach_args *ia = aux; 362 bus_space_tag_t iot = ia->ia_iot; 363 bus_space_handle_t ioh; 364 struct esp_isa_probe_data epd; 365 isa_chipset_tag_t ic = ia->ia_ic; 366 int error; 367 368 sc->sc_dev = self; 369 aprint_normal("\n"); 370 ESP_TRACE(("[esp_isa_attach] ")); 371 372 if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) { 373 aprint_error_dev(self, "can't map i/o space\n"); 374 return; 375 } 376 377 if (!esp_isa_find(iot, ioh, &epd)) { 378 aprint_error_dev(self, "esp_isa_find failed\n"); 379 return; 380 } 381 382 if (ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) { 383 if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) { 384 aprint_error_dev(self, 385 "unable to cascade DRQ, error = %d\n", error); 386 return; 387 } 388 } 389 390 esc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE, 391 IPL_BIO, ncr53c9x_intr, esc); 392 if (esc->sc_ih == NULL) { 393 aprint_error_dev(self, "couldn't establish interrupt\n"); 394 return; 395 } 396 397 esc->sc_ioh = ioh; 398 esc->sc_iot = iot; 399 esp_isa_init(esc, &epd); 400 401 aprint_normal_dev(self, "%ssync,%sparity\n", 402 epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no "); 403 aprint_normal("%s", device_xname(self)); 404 405 /* 406 * Now try to attach all the sub-devices 407 */ 408 sc->sc_adapter.adapt_minphys = minphys; 409 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 410 ncr53c9x_attach(sc); 411 } 412 413 /* 414 * Glue functions. 415 */ 416 uint8_t 417 esp_isa_read_reg(struct ncr53c9x_softc *sc, int reg) 418 { 419 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 420 uint8_t v; 421 422 v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg); 423 424 ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ", 425 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 426 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 427 428 return v; 429 } 430 431 void 432 esp_isa_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 433 { 434 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 435 uint8_t v = val; 436 437 if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) { 438 v = NCRCMD_TRANS; 439 } 440 441 ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ", 442 (bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) & 443 NCRCFG4_CRS1) ? '1' : '0', reg, v)); 444 445 bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v); 446 } 447 448 int 449 esp_isa_dma_isintr(struct ncr53c9x_softc *sc) 450 { 451 452 ESP_TRACE(("[esp_isa_dma_isintr] ")); 453 454 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 455 } 456 457 void 458 esp_isa_dma_reset(struct ncr53c9x_softc *sc) 459 { 460 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 461 462 ESP_TRACE(("[esp_isa_dma_reset] ")); 463 464 esc->sc_active = 0; 465 esc->sc_tc = 0; 466 } 467 468 int 469 esp_isa_dma_intr(struct ncr53c9x_softc *sc) 470 { 471 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 472 uint8_t*p; 473 u_int espphase, espstat, espintr; 474 int cnt; 475 476 ESP_TRACE(("[esp_isa_dma_intr] ")); 477 478 if (esc->sc_active == 0) { 479 printf("%s: dma_intr--inactive DMA\n", 480 device_xname(sc->sc_dev)); 481 return -1; 482 } 483 484 if ((sc->sc_espintr & NCRINTR_BS) == 0) { 485 esc->sc_active = 0; 486 return 0; 487 } 488 489 cnt = *esc->sc_pdmalen; 490 if (*esc->sc_pdmalen == 0) { 491 printf("%s: data interrupt, but no count left\n", 492 device_xname(sc->sc_dev)); 493 } 494 495 p = *esc->sc_dmaaddr; 496 espphase = sc->sc_phase; 497 espstat = (u_int)sc->sc_espstat; 498 espintr = (u_int)sc->sc_espintr; 499 do { 500 if (esc->sc_datain) { 501 *p++ = NCR_READ_REG(sc, NCR_FIFO); 502 cnt--; 503 if (espphase == DATA_IN_PHASE) { 504 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 505 } else { 506 esc->sc_active = 0; 507 } 508 } else { 509 if ((espphase == DATA_OUT_PHASE) || 510 (espphase == MESSAGE_OUT_PHASE)) { 511 NCR_WRITE_REG(sc, NCR_FIFO, *p++); 512 cnt--; 513 NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS); 514 } else { 515 esc->sc_active = 0; 516 } 517 } 518 519 if (esc->sc_active) { 520 while ((NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) == 0) 521 ; 522 espstat = NCR_READ_REG(sc, NCR_STAT); 523 espintr = NCR_READ_REG(sc, NCR_INTR); 524 espphase = (espintr & NCRINTR_DIS) ? 525 /* Disconnected */ BUSFREE_PHASE : 526 espstat & PHASE_MASK; 527 } 528 } while (esc->sc_active && espintr); 529 sc->sc_phase = espphase; 530 sc->sc_espstat = (uint8_t)espstat; 531 sc->sc_espintr = (uint8_t)espintr; 532 *esc->sc_dmaaddr = p; 533 *esc->sc_pdmalen = cnt; 534 535 if (*esc->sc_pdmalen == 0) { 536 esc->sc_tc = NCRSTAT_TC; 537 } 538 sc->sc_espstat |= esc->sc_tc; 539 return 0; 540 } 541 542 int 543 esp_isa_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 544 int datain, size_t *dmasize) 545 { 546 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 547 548 ESP_TRACE(("[esp_isa_dma_setup] ")); 549 550 esc->sc_dmaaddr = addr; 551 esc->sc_pdmalen = len; 552 esc->sc_datain = datain; 553 esc->sc_dmasize = *dmasize; 554 esc->sc_tc = 0; 555 556 return 0; 557 } 558 559 void 560 esp_isa_dma_go(struct ncr53c9x_softc *sc) 561 { 562 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 563 564 ESP_TRACE(("[esp_isa_dma_go] ")); 565 566 esc->sc_active = 1; 567 } 568 569 void 570 esp_isa_dma_stop(struct ncr53c9x_softc *sc) 571 { 572 ESP_TRACE(("[esp_isa_dma_stop] ")); 573 } 574 575 int 576 esp_isa_dma_isactive(struct ncr53c9x_softc *sc) 577 { 578 struct esp_isa_softc *esc = (struct esp_isa_softc *)sc; 579 580 ESP_TRACE(("[esp_isa_dma_isactive] ")); 581 582 return esc->sc_active; 583 } 584
Indexes created Sun Oct 25 00:26:45 UTC 2026