| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| model.c | 1114 #define TIMING_DATA(td) td
1116 #define TIMING_DATA(td) 0
1121 { "lm32", & lm32_mach, MODEL_LM32, TIMING_DATA (& lm32_timing[0]), lm32_model_init },
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| model.c | 1114 #define TIMING_DATA(td) td
1116 #define TIMING_DATA(td) 0
1121 { "lm32", & lm32_mach, MODEL_LM32, TIMING_DATA (& lm32_timing[0]), lm32_model_init },
|
| /src/external/gpl3/gdb.old/dist/sim/iq2000/ |
| model.c | 2508 #define TIMING_DATA(td) td
2510 #define TIMING_DATA(td) 0
2515 { "iq2000", & iq2000_mach, MODEL_IQ2000, TIMING_DATA (& iq2000_timing[0]), iq2000_model_init },
|
| /src/external/gpl3/gdb.old/dist/sim/m32r/ |
| model2.c | 3191 #define TIMING_DATA(td) td
3193 #define TIMING_DATA(td) 0
3198 { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
|
| modelx.c | 3009 #define TIMING_DATA(td) td
3011 #define TIMING_DATA(td) 0
3016 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
|
| model.c | 4296 #define TIMING_DATA(td) td
4298 #define TIMING_DATA(td) 0
4303 { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4304 { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
|
| /src/external/gpl3/gdb/dist/sim/iq2000/ |
| model.c | 2508 #define TIMING_DATA(td) td
2510 #define TIMING_DATA(td) 0
2515 { "iq2000", & iq2000_mach, MODEL_IQ2000, TIMING_DATA (& iq2000_timing[0]), iq2000_model_init },
|
| /src/external/gpl3/gdb/dist/sim/m32r/ |
| model2.c | 3191 #define TIMING_DATA(td) td
3193 #define TIMING_DATA(td) 0
3198 { "m32r2", & m32r2_mach, MODEL_M32R2, TIMING_DATA (& m32r2_timing[0]), m32r2_model_init },
|
| modelx.c | 3009 #define TIMING_DATA(td) td
3011 #define TIMING_DATA(td) 0
3016 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
|
| model.c | 4296 #define TIMING_DATA(td) td
4298 #define TIMING_DATA(td) 0
4303 { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4304 { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
|
| /src/external/gpl3/gdb.old/dist/sim/cris/ |
| modelv10.c | 4112 #define TIMING_DATA(td) td
4114 #define TIMING_DATA(td) 0
4119 { "crisv10", & crisv10_mach, MODEL_CRISV10, TIMING_DATA (& crisv10_timing[0]), crisv10_model_init },
|
| modelv32.c | 5903 #define TIMING_DATA(td) td
5905 #define TIMING_DATA(td) 0
5910 { "crisv32", & crisv32_mach, MODEL_CRISV32, TIMING_DATA (& crisv32_timing[0]), crisv32_model_init },
|
| /src/external/gpl3/gdb/dist/sim/cris/ |
| modelv10.c | 4112 #define TIMING_DATA(td) td
4114 #define TIMING_DATA(td) 0
4119 { "crisv10", & crisv10_mach, MODEL_CRISV10, TIMING_DATA (& crisv10_timing[0]), crisv10_model_init },
|
| modelv32.c | 5903 #define TIMING_DATA(td) td
5905 #define TIMING_DATA(td) 0
5910 { "crisv32", & crisv32_mach, MODEL_CRISV32, TIMING_DATA (& crisv32_timing[0]), crisv32_model_init },
|
| /src/external/gpl3/gdb.old/dist/sim/or1k/ |
| model.c | 4871 #define TIMING_DATA(td) td
4873 #define TIMING_DATA(td) 0
4878 { "or1200", & or32_mach, MODEL_OR1200, TIMING_DATA (& or1200_timing[0]), or1200_model_init },
4884 { "or1200nd", & or32nd_mach, MODEL_OR1200ND, TIMING_DATA (& or1200nd_timing[0]), or1200nd_model_init },
|
| /src/external/gpl3/gdb/dist/sim/or1k/ |
| model.c | 4871 #define TIMING_DATA(td) td
4873 #define TIMING_DATA(td) 0
4878 { "or1200", & or32_mach, MODEL_OR1200, TIMING_DATA (& or1200_timing[0]), or1200_model_init },
4884 { "or1200nd", & or32nd_mach, MODEL_OR1200ND, TIMING_DATA (& or1200nd_timing[0]), or1200nd_model_init },
|
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| model.c | [all...] |
| /src/external/gpl3/gdb/dist/sim/frv/ |
| model.c | [all...] |
