1 /* $OpenBSD: octxctlreg.h,v 1.2 2018/01/16 15:50:28 visa Exp $ */ 2 3 /* 4 * Copyright (c) 2017 Visa Hankala 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _OCTXCTLREG_H_ 20 #define _OCTXCTLREG_H_ 21 22 #define XCTL_CTL 0x00 23 #define XCTL_CTL_CLEAR_BIST 0x8000000000000000ull 24 #define XCTL_CTL_START_BIST 0x4000000000000000ull 25 #define XCTL_CTL_REFCLK_SEL 0x3000000000000000ull 26 #define XCTL_CTL_REFCLK_SEL_SHIFT 60 27 #define XCTL_CTL_SSC_EN 0x0800000000000000ull 28 #define XCTL_CTL_SSC_RANG 0x0700000000000000ull 29 #define XCTL_CTL_SSC_REFCLK_SEL 0x00ff800000000000ull 30 #define XCTL_CTL_MPLL_MULT 0x00007f0000000000ull 31 #define XCTL_CTL_MPLL_MULT_SHIFT 40 32 #define XCTL_CTL_REFCLK_SSP_EN 0x0000008000000000ull 33 #define XCTL_CTL_REFCLK_DIV2 0x0000004000000000ull 34 #define XCTL_CTL_REFCLK_FSEL 0x0000003f00000000ull 35 #define XCTL_CTL_REFCLK_FSEL_SHIFT 32 36 #define XCTL_CTL_CLK_EN 0x0000000040000000ull 37 #define XCTL_CTL_CLK_BYP_SEL 0x0000000020000000ull 38 #define XCTL_CTL_CLKDIV_RST 0x0000000010000000ull 39 #define XCTL_CTL_CLKDIV_SEL 0x0000000007000000ull 40 #define XCTL_CTL_CLKDIV_SEL_SHIFT 24 41 #define XCTL_CTL_USB3_PORT_PERM_ATTACH 0x0000000000200000ull 42 #define XCTL_CTL_USB2_PORT_PERM_ATTACH 0x0000000000100000ull 43 #define XCTL_CTL_USB3_PORT_DIS 0x0000000000040000ull 44 #define XCTL_CTL_USB2_PORT_DIS 0x0000000000010000ull 45 #define XCTL_CTL_SSPOWER_EN 0x0000000000004000ull 46 #define XCTL_CTL_HSPOWER_EN 0x0000000000001000ull 47 #define XCTL_CTL_CSCLK_EN 0x0000000000000010ull 48 #define XCTL_CTL_DRD_MODE 0x0000000000000008ull 49 #define XCTL_CTL_UPHY_RST 0x0000000000000004ull 50 #define XCTL_CTL_UAHC_RST 0x0000000000000002ull 51 #define XCTL_CTL_UCTL_RST 0x0000000000000001ull 52 53 #define XCTL_HOST_CFG 0xe0 54 #define XCTL_HOST_CFG_PPC_EN 0x0000000002000000ull 55 #define XCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN 0x0000000001000000ull 56 57 #define XCTL_SHIM_CFG 0xe8 58 #define XCTL_SHIM_CFG_DMA_BYTE_SWAP 0x0000000000000300ull 59 #define XCTL_SHIM_CFG_DMA_BYTE_SWAP_SHIFT 8 60 #define XCTL_SHIM_CFG_CSR_BYTE_SWAP 0x0000000000000003ull 61 #define XCTL_SHIM_CFG_CSR_BYTE_SWAP_SHIFT 0 62 #define XCTL_SHIM_ENDIAN_LITTLE 0 /* A-B-C-D-E-F-G-H -> A-B-C-D-E-F-G-H */ 63 #define XCTL_SHIM_ENDIAN_BIG 1 /* A-B-C-D-E-F-G-H -> H-G-F-E-D-C-B-A */ 64 #define XCTL_SHIM_ENDIAN_RSVD2 2 /* A-B-C-D-E-F-G-H -> D-C-B-A-H-G-F-E */ 65 #define XCTL_SHIM_ENDIAN_RSVD3 3 /* A-B-C-D-E-F-G-H -> E-F-G-H-A-B-C-D */ 66 67 /* 68 * DWC3 core control registers. 69 * These are relative to the xHCI register space. 70 */ 71 72 #define DWC3_GCTL 0xc110 73 #define DWC3_GCTL_PRTCAP_MASK 0x00003000u 74 #define DWC3_GCTL_PRTCAP_HOST 0x00001000u 75 #define DWC3_GCTL_SOFITPSYNC 0x00000400u 76 #define DWC3_GCTL_SCALEDOWN_MASK 0x00000030u 77 #define DWC3_GCTL_DISSCRAMBLE 0x00000004u 78 #define DWC3_GCTL_DSBLCLKGTNG 0x00000001u 79 80 #define DWC3_GSNPSID 0xc120 81 82 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) 83 #define DWC3_GUSB2PHYCFG_SUSPHY 0x00000040u 84 85 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) 86 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX 0x08000000u 87 #define DWC3_GUSB3PIPECTL_SUSPHY 0x00020000u 88 89 /* DWC3 revision numbers. */ 90 #define DWC3_REV_210A 0x210a 91 #define DWC3_REV_250A 0x250a 92 93 #endif /* !_OCTXCTLREG_H_ */ 94
Indexes created Sat Sep 27 22:09:54 GMT 2025