1 /* $NetBSD: sun5i_a13_gpio.c,v 1.3 2018/04/03 16:01:25 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: sun5i_a13_gpio.c,v 1.3 2018/04/03 16:01:25 bouyer Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/types.h> 38 39 #include <arm/sunxi/sunxi_gpio.h> 40 41 static const struct sunxi_gpio_pins a13_pins[] = { 42 { "PB0", 1, 0, { "gpio_in", "gpio_out", "i2c0" } }, 43 { "PB1", 1, 1, { "gpio_in", "gpio_out", "i2c0" } }, 44 { "PB2", 1, 2, { "gpio_in", "gpio_out", "pwm", NULL, NULL, NULL, "irq" }, 6, 16 }, 45 { "PB3", 1, 3, { "gpio_in", "gpio_out", "ir0", NULL, NULL, NULL, "irq" }, 6, 17 }, 46 { "PB4", 1, 4, { "gpio_in", "gpio_out", "ir0", NULL, NULL, NULL, "irq" }, 6, 18 }, 47 { "PB10", 1, 10, { "gpio_in", "gpio_out", "spi2", NULL, NULL, NULL, "irq" }, 6, 24 }, 48 { "PB15", 1, 15, { "gpio_in", "gpio_out", "i2c1" } }, 49 { "PB16", 1, 16, { "gpio_in", "gpio_out", "i2c1" } }, 50 { "PB17", 1, 17, { "gpio_in", "gpio_out", "i2c2" } }, 51 { "PB18", 1, 18, { "gpio_in", "gpio_out", "i2c2" } }, 52 53 { "PC0", 2, 0, { "gpio_in", "gpio_out", "nand0", "spi0" } }, 54 { "PC1", 2, 1, { "gpio_in", "gpio_out", "nand0", "spi0" } }, 55 { "PC2", 2, 2, { "gpio_in", "gpio_out", "nand0", "spi0" } }, 56 { "PC3", 2, 3, { "gpio_in", "gpio_out", "nand0", "spi0" } }, 57 { "PC4", 2, 4, { "gpio_in", "gpio_out", "nand0" } }, 58 { "PC5", 2, 5, { "gpio_in", "gpio_out", "nand0" } }, 59 { "PC6", 2, 6, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 60 { "PC7", 2, 7, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 61 { "PC8", 2, 8, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 62 { "PC9", 2, 9, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 63 { "PC10", 2, 10, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 64 { "PC11", 2, 11, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 65 { "PC12", 2, 12, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 66 { "PC13", 2, 13, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 67 { "PC14", 2, 14, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 68 { "PC15", 2, 15, { "gpio_in", "gpio_out", "nand0", "mmc2" } }, 69 { "PC19", 2, 19, { "gpio_in", "gpio_out", "nand0" } }, 70 71 { "PD2", 3, 2, { "gpio_in", "gpio_out", "lcd0", "uart2" } }, 72 { "PD3", 3, 3, { "gpio_in", "gpio_out", "lcd0", "uart2" } }, 73 { "PD4", 3, 4, { "gpio_in", "gpio_out", "lcd0", "uart2" } }, 74 { "PD5", 3, 5, { "gpio_in", "gpio_out", "lcd0", "uart2" } }, 75 { "PD6", 3, 6, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 76 { "PD7", 3, 7, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 77 { "PD10", 3, 10, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 78 { "PD11", 3, 11, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 79 { "PD12", 3, 12, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 80 { "PD13", 3, 13, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 81 { "PD14", 3, 14, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 82 { "PD15", 3, 15, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 83 { "PD18", 3, 18, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 84 { "PD19", 3, 19, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 85 { "PD20", 3, 20, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 86 { "PD21", 3, 21, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 87 { "PD22", 3, 22, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 88 { "PD23", 3, 23, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 89 { "PD24", 3, 24, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 90 { "PD25", 3, 25, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 91 { "PD26", 3, 26, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 92 { "PD27", 3, 27, { "gpio_in", "gpio_out", "lcd0", "emac" } }, 93 94 { "PE0", 4, 0, { "gpio_in", NULL, "ts0", "csi0", "spi2", NULL, "irq" }, 6, 14 }, 95 { "PE1", 4, 1, { "gpio_in", NULL, "ts0", "csi0", "spi2", NULL, "irq" }, 6, 15 }, 96 { "PE2", 4, 2, { "gpio_in", NULL, "ts0", "csi0", "spi2" } }, 97 { "PE3", 4, 3, { "gpio_in", "gpio_out", "ts0", "csi0", "spi2" } }, 98 { "PE4", 4, 4, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 99 { "PE5", 4, 5, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 100 { "PE6", 4, 6, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 101 { "PE7", 4, 7, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 102 { "PE8", 4, 8, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 103 { "PE9", 4, 9, { "gpio_in", "gpio_out", "ts0", "csi0", "mmc2" } }, 104 { "PE10", 4, 10, { "gpio_in", "gpio_out", "ts0", "csi0", "uart1" } }, 105 { "PE11", 4, 11, { "gpio_in", "gpio_out", "ts0", "csi0", "uart1" } }, 106 107 { "PF0", 5, 0, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 108 { "PF1", 5, 1, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 109 { "PF2", 5, 2, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 110 { "PF3", 5, 3, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 111 { "PF4", 5, 4, { "gpio_in", "gpio_out", "mmc0", "uart0" } }, 112 { "PF5", 5, 5, { "gpio_in", "gpio_out", "mmc0", "jtag" } }, 113 114 { "PG0", 6, 0, { "gpio_in", NULL, "gps", NULL, NULL, NULL, "irq" }, 6, 0 }, 115 { "PG1", 6, 1, { "gpio_in", NULL, "gps", NULL, NULL, NULL, "irq" }, 6, 1 }, 116 { "PG2", 6, 2, { "gpio_in", NULL, "gps", NULL, NULL, NULL, "irq" }, 6, 2 }, 117 { "PG3", 6, 3, { "gpio_in", "gpio_out", NULL, NULL, "uart1", NULL, "irq" }, 6, 3 }, 118 { "PG4", 6, 4, { "gpio_in", "gpio_out", NULL, NULL, "uart1", NULL, "irq" }, 6, 4 }, 119 { "PG9", 6, 9, { "gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "irq" }, 6, 9 }, 120 { "PG10", 6, 10, { "gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "irq" }, 6, 10 }, 121 { "PG11", 6, 11, { "gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "irq" }, 6, 11 }, 122 { "PG12", 6, 12, { "gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "irq" }, 6, 12 }, 123 }; 124 125 const struct sunxi_gpio_padconf sun5i_a13_padconf = { 126 .npins = __arraycount(a13_pins), 127 .pins = a13_pins, 128 }; 129
Indexes created Tue Sep 30 20:09:53 GMT 2025