1 /* $NetBSD: if_ae.c,v 1.45 2024/07/05 04:31:49 rin Exp $ */ 2 /*- 3 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 4 * Copyright (c) 2006 Garrett D'Amore. 5 * All rights reserved. 6 * 7 * This code was written by Garrett D'Amore for the Champaign-Urbana 8 * Community Wireless Network Project. 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer in the documentation and/or other materials provided 18 * with the distribution. 19 * 3. All advertising materials mentioning features or use of this 20 * software must display the following acknowledgements: 21 * This product includes software developed by the Urbana-Champaign 22 * Independent Media Center. 23 * This product includes software developed by Garrett D'Amore. 24 * 4. Urbana-Champaign Independent Media Center's name and Garrett 25 * D'Amore's name may not be used to endorse or promote products 26 * derived from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 29 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 33 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 39 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 40 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 */ 42 /*- 43 * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc. 44 * All rights reserved. 45 * 46 * This code is derived from software contributed to The NetBSD Foundation 47 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 48 * NASA Ames Research Center; and by Charles M. Hannum. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 60 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 69 * POSSIBILITY OF SUCH DAMAGE. 70 */ 71 72 /* 73 * Device driver for the onboard ethernet MAC found on the AR5312 74 * chip's AHB bus. 75 * 76 * This device is very simliar to the tulip in most regards, and 77 * the code is directly derived from NetBSD's tulip.c. However, it 78 * is different enough that it did not seem to be a good idea to 79 * add further complexity to the tulip driver, so we have our own. 80 * 81 * Also tulip has a lot of complexity in it for various parts/options 82 * that we don't need, and on these little boxes with only ~8MB RAM, we 83 * don't want any extra bloat. 84 */ 85 86 /* 87 * TODO: 88 * 89 * 1) Find out about BUS_MODE_ALIGN16B. This chip can apparently align 90 * inbound packets on a half-word boundary, which would make life easier 91 * for TCP/IP. (Aligning IP headers on a word.) 92 * 93 * 2) There is stuff in original tulip to shut down the device when reacting 94 * to a change in link status. Is that needed. 95 * 96 * 3) Test with variety of 10/100 HDX/FDX scenarios. 97 * 98 */ 99 100 #include <sys/cdefs.h> 101 __KERNEL_RCSID(0, "$NetBSD: if_ae.c,v 1.45 2024/07/05 04:31:49 rin Exp $"); 102 103 104 #include <sys/param.h> 105 #include <sys/bus.h> 106 #include <sys/callout.h> 107 #include <sys/device.h> 108 #include <sys/endian.h> 109 #include <sys/errno.h> 110 #include <sys/intr.h> 111 #include <sys/ioctl.h> 112 #include <sys/kernel.h> 113 #include <sys/mbuf.h> 114 #include <sys/socket.h> 115 116 #include <uvm/uvm_extern.h> 117 118 #include <net/if.h> 119 #include <net/if_dl.h> 120 #include <net/if_media.h> 121 #include <net/if_ether.h> 122 123 #include <net/bpf.h> 124 125 #include <dev/mii/mii.h> 126 #include <dev/mii/miivar.h> 127 #include <dev/mii/mii_bitbang.h> 128 129 #include <mips/atheros/include/arbusvar.h> 130 #include <mips/atheros/dev/aereg.h> 131 #include <mips/atheros/dev/aevar.h> 132 133 static const struct { 134 uint32_t txth_opmode; /* OPMODE bits */ 135 const char *txth_name; /* name of mode */ 136 } ae_txthresh[] = { 137 { OPMODE_TR_32, "32 words" }, 138 { OPMODE_TR_64, "64 words" }, 139 { OPMODE_TR_128, "128 words" }, 140 { OPMODE_TR_256, "256 words" }, 141 { OPMODE_SF, "store and forward mode" }, 142 { 0, NULL }, 143 }; 144 145 static int ae_match(device_t, struct cfdata *, void *); 146 static void ae_attach(device_t, device_t, void *); 147 static int ae_detach(device_t, int); 148 static int ae_activate(device_t, enum devact); 149 150 static int ae_ifflags_cb(struct ethercom *); 151 static void ae_reset(struct ae_softc *); 152 static void ae_idle(struct ae_softc *, uint32_t); 153 154 static void ae_start(struct ifnet *); 155 static void ae_watchdog(struct ifnet *); 156 static int ae_ioctl(struct ifnet *, u_long, void *); 157 static int ae_init(struct ifnet *); 158 static void ae_stop(struct ifnet *, int); 159 160 static void ae_shutdown(void *); 161 162 static void ae_rxdrain(struct ae_softc *); 163 static int ae_add_rxbuf(struct ae_softc *, int); 164 165 static int ae_enable(struct ae_softc *); 166 static void ae_disable(struct ae_softc *); 167 static void ae_power(int, void *); 168 169 static void ae_filter_setup(struct ae_softc *); 170 171 static int ae_intr(void *); 172 static void ae_rxintr(struct ae_softc *); 173 static void ae_txintr(struct ae_softc *); 174 175 static void ae_mii_tick(void *); 176 static void ae_mii_statchg(struct ifnet *); 177 178 static int ae_mii_readreg(device_t, int, int, uint16_t *); 179 static int ae_mii_writereg(device_t, int, int, uint16_t); 180 181 #ifdef AE_DEBUG 182 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 183 printf x 184 #else 185 #define DPRINTF(sc, x) /* nothing */ 186 #endif 187 188 #ifdef AE_STATS 189 static void ae_print_stats(struct ae_softc *); 190 #endif 191 192 CFATTACH_DECL_NEW(ae, sizeof(struct ae_softc), 193 ae_match, ae_attach, ae_detach, ae_activate); 194 195 /* 196 * ae_match: 197 * 198 * Check for a device match. 199 */ 200 int 201 ae_match(device_t parent, struct cfdata *cf, void *aux) 202 { 203 struct arbus_attach_args *aa = aux; 204 205 if (strcmp(aa->aa_name, cf->cf_name) == 0) 206 return 1; 207 208 return 0; 209 210 } 211 212 /* 213 * ae_attach: 214 * 215 * Attach an ae interface to the system. 216 */ 217 void 218 ae_attach(device_t parent, device_t self, void *aux) 219 { 220 const uint8_t *enaddr; 221 prop_data_t ea; 222 struct ae_softc *sc = device_private(self); 223 struct arbus_attach_args *aa = aux; 224 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 225 struct mii_data * const mii = &sc->sc_mii; 226 int i, error; 227 228 sc->sc_dev = self; 229 230 callout_init(&sc->sc_tick_callout, 0); 231 232 printf(": Atheros AR531X 10/100 Ethernet\n"); 233 234 /* 235 * Try to get MAC address. 236 */ 237 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-address"); 238 if (ea == NULL) { 239 printf("%s: unable to get mac-addr property\n", 240 device_xname(sc->sc_dev)); 241 return; 242 } 243 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 244 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 245 enaddr = prop_data_data_nocopy(ea); 246 247 /* Announce ourselves. */ 248 printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev), 249 ether_sprintf(enaddr)); 250 251 sc->sc_cirq = aa->aa_cirq; 252 sc->sc_mirq = aa->aa_mirq; 253 sc->sc_st = aa->aa_bst; 254 sc->sc_dmat = aa->aa_dmat; 255 256 SIMPLEQ_INIT(&sc->sc_txfreeq); 257 SIMPLEQ_INIT(&sc->sc_txdirtyq); 258 259 /* 260 * Map registers. 261 */ 262 sc->sc_size = aa->aa_size; 263 if ((error = bus_space_map(sc->sc_st, aa->aa_addr, sc->sc_size, 0, 264 &sc->sc_sh)) != 0) { 265 printf("%s: unable to map registers, error = %d\n", 266 device_xname(sc->sc_dev), error); 267 goto fail_0; 268 } 269 270 /* 271 * Allocate the control data structures, and create and load the 272 * DMA map for it. 273 */ 274 if ((error = bus_dmamem_alloc(sc->sc_dmat, 275 sizeof(struct ae_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 276 1, &sc->sc_cdnseg, 0)) != 0) { 277 printf("%s: unable to allocate control data, error = %d\n", 278 device_xname(sc->sc_dev), error); 279 goto fail_1; 280 } 281 282 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 283 sizeof(struct ae_control_data), (void **)&sc->sc_control_data, 284 BUS_DMA_COHERENT)) != 0) { 285 printf("%s: unable to map control data, error = %d\n", 286 device_xname(sc->sc_dev), error); 287 goto fail_2; 288 } 289 290 if ((error = bus_dmamap_create(sc->sc_dmat, 291 sizeof(struct ae_control_data), 1, 292 sizeof(struct ae_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 293 printf("%s: unable to create control data DMA map, " 294 "error = %d\n", device_xname(sc->sc_dev), error); 295 goto fail_3; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct ae_control_data), NULL, 300 0)) != 0) { 301 printf("%s: unable to load control data DMA map, error = %d\n", 302 device_xname(sc->sc_dev), error); 303 goto fail_4; 304 } 305 306 /* 307 * Create the transmit buffer DMA maps. 308 */ 309 for (i = 0; i < AE_TXQUEUELEN; i++) { 310 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 311 AE_NTXSEGS, MCLBYTES, 0, 0, 312 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 313 printf("%s: unable to create tx DMA map %d, " 314 "error = %d\n", device_xname(sc->sc_dev), i, error); 315 goto fail_5; 316 } 317 } 318 319 /* 320 * Create the receive buffer DMA maps. 321 */ 322 for (i = 0; i < AE_NRXDESC; i++) { 323 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 324 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 325 printf("%s: unable to create rx DMA map %d, " 326 "error = %d\n", device_xname(sc->sc_dev), i, error); 327 goto fail_6; 328 } 329 sc->sc_rxsoft[i].rxs_mbuf = NULL; 330 } 331 332 /* 333 * Reset the chip to a known state. 334 */ 335 ae_reset(sc); 336 337 /* 338 * From this point forward, the attachment cannot fail. A failure 339 * before this point releases all resources that may have been 340 * allocated. 341 */ 342 sc->sc_flags |= AE_ATTACHED; 343 344 /* 345 * Initialize our media structures. This may probe the MII, if 346 * present. 347 */ 348 mii->mii_ifp = ifp; 349 mii->mii_readreg = ae_mii_readreg; 350 mii->mii_writereg = ae_mii_writereg; 351 mii->mii_statchg = ae_mii_statchg; 352 sc->sc_ethercom.ec_mii = mii; 353 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 354 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 355 MII_OFFSET_ANY, 0); 356 357 if (LIST_FIRST(&mii->mii_phys) == NULL) { 358 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 359 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 360 } else 361 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 362 363 sc->sc_tick = ae_mii_tick; 364 365 strcpy(ifp->if_xname, device_xname(sc->sc_dev)); 366 ifp->if_softc = sc; 367 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 368 sc->sc_if_flags = ifp->if_flags; 369 ifp->if_ioctl = ae_ioctl; 370 ifp->if_start = ae_start; 371 ifp->if_watchdog = ae_watchdog; 372 ifp->if_init = ae_init; 373 ifp->if_stop = ae_stop; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 /* 377 * We can support 802.1Q VLAN-sized frames. 378 */ 379 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 380 381 /* 382 * Attach the interface. 383 */ 384 if_attach(ifp); 385 if_deferred_start_init(ifp, NULL); 386 ether_ifattach(ifp, enaddr); 387 ether_set_ifflags_cb(&sc->sc_ethercom, ae_ifflags_cb); 388 389 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 390 RND_TYPE_NET, RND_FLAG_DEFAULT); 391 392 /* 393 * Make sure the interface is shutdown during reboot. 394 */ 395 sc->sc_sdhook = shutdownhook_establish(ae_shutdown, sc); 396 if (sc->sc_sdhook == NULL) 397 printf("%s: WARNING: unable to establish shutdown hook\n", 398 device_xname(sc->sc_dev)); 399 400 /* 401 * Add a suspend hook to make sure we come back up after a 402 * resume. 403 */ 404 sc->sc_powerhook = powerhook_establish(device_xname(sc->sc_dev), 405 ae_power, sc); 406 if (sc->sc_powerhook == NULL) 407 printf("%s: WARNING: unable to establish power hook\n", 408 device_xname(sc->sc_dev)); 409 return; 410 411 /* 412 * Free any resources we've allocated during the failed attach 413 * attempt. Do this in reverse order and fall through. 414 */ 415 fail_6: 416 for (i = 0; i < AE_NRXDESC; i++) { 417 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 418 bus_dmamap_destroy(sc->sc_dmat, 419 sc->sc_rxsoft[i].rxs_dmamap); 420 } 421 fail_5: 422 for (i = 0; i < AE_TXQUEUELEN; i++) { 423 if (sc->sc_txsoft[i].txs_dmamap != NULL) 424 bus_dmamap_destroy(sc->sc_dmat, 425 sc->sc_txsoft[i].txs_dmamap); 426 } 427 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 428 fail_4: 429 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 430 fail_3: 431 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 432 sizeof(struct ae_control_data)); 433 fail_2: 434 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 435 fail_1: 436 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 437 fail_0: 438 return; 439 } 440 441 /* 442 * ae_activate: 443 * 444 * Handle device activation/deactivation requests. 445 */ 446 int 447 ae_activate(device_t self, enum devact act) 448 { 449 struct ae_softc *sc = device_private(self); 450 451 switch (act) { 452 case DVACT_DEACTIVATE: 453 if_deactivate(&sc->sc_ethercom.ec_if); 454 return 0; 455 default: 456 return EOPNOTSUPP; 457 } 458 } 459 460 /* 461 * ae_detach: 462 * 463 * Detach a device interface. 464 */ 465 int 466 ae_detach(device_t self, int flags) 467 { 468 struct ae_softc *sc = device_private(self); 469 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 470 struct ae_rxsoft *rxs; 471 struct ae_txsoft *txs; 472 int i; 473 474 /* 475 * Succeed now if there isn't any work to do. 476 */ 477 if ((sc->sc_flags & AE_ATTACHED) == 0) 478 return (0); 479 480 /* Unhook our tick handler. */ 481 if (sc->sc_tick) 482 callout_stop(&sc->sc_tick_callout); 483 484 /* Detach all PHYs */ 485 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 486 487 rnd_detach_source(&sc->sc_rnd_source); 488 ether_ifdetach(ifp); 489 if_detach(ifp); 490 491 /* Delete all remaining media. */ 492 ifmedia_fini(&sc->sc_mii.mii_media); 493 494 for (i = 0; i < AE_NRXDESC; i++) { 495 rxs = &sc->sc_rxsoft[i]; 496 if (rxs->rxs_mbuf != NULL) { 497 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 498 m_freem(rxs->rxs_mbuf); 499 rxs->rxs_mbuf = NULL; 500 } 501 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 502 } 503 for (i = 0; i < AE_TXQUEUELEN; i++) { 504 txs = &sc->sc_txsoft[i]; 505 if (txs->txs_mbuf != NULL) { 506 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 507 m_freem(txs->txs_mbuf); 508 txs->txs_mbuf = NULL; 509 } 510 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 511 } 512 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 514 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 515 sizeof(struct ae_control_data)); 516 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 517 518 shutdownhook_disestablish(sc->sc_sdhook); 519 powerhook_disestablish(sc->sc_powerhook); 520 521 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size); 522 523 524 return (0); 525 } 526 527 /* 528 * ae_shutdown: 529 * 530 * Make sure the interface is stopped at reboot time. 531 */ 532 static void 533 ae_shutdown(void *arg) 534 { 535 struct ae_softc *sc = arg; 536 537 ae_stop(&sc->sc_ethercom.ec_if, 1); 538 } 539 540 /* 541 * ae_start: [ifnet interface function] 542 * 543 * Start packet transmission on the interface. 544 */ 545 static void 546 ae_start(struct ifnet *ifp) 547 { 548 struct ae_softc *sc = ifp->if_softc; 549 struct mbuf *m0, *m; 550 struct ae_txsoft *txs; 551 bus_dmamap_t dmamap; 552 int error, firsttx, nexttx, lasttx = 1, ofree, seg; 553 554 DPRINTF(sc, ("%s: ae_start: sc_flags 0x%08x, if_flags 0x%08x\n", 555 device_xname(sc->sc_dev), sc->sc_flags, ifp->if_flags)); 556 557 558 if ((ifp->if_flags & IFF_RUNNING) == 0) 559 return; 560 561 /* 562 * Remember the previous number of free descriptors and 563 * the first descriptor we'll use. 564 */ 565 ofree = sc->sc_txfree; 566 firsttx = sc->sc_txnext; 567 568 DPRINTF(sc, ("%s: ae_start: txfree %d, txnext %d\n", 569 device_xname(sc->sc_dev), ofree, firsttx)); 570 571 /* 572 * Loop through the send queue, setting up transmit descriptors 573 * until we drain the queue, or use up all available transmit 574 * descriptors. 575 */ 576 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 577 sc->sc_txfree != 0) { 578 /* 579 * Grab a packet off the queue. 580 */ 581 IFQ_POLL(&ifp->if_snd, m0); 582 if (m0 == NULL) 583 break; 584 m = NULL; 585 586 dmamap = txs->txs_dmamap; 587 588 /* 589 * Load the DMA map. If this fails, the packet either 590 * didn't fit in the allotted number of segments, or we were 591 * short on resources. In this case, we'll copy and try 592 * again. 593 */ 594 if (((mtod(m0, uintptr_t) & 3) != 0) || 595 bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 596 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) { 597 MGETHDR(m, M_DONTWAIT, MT_DATA); 598 if (m == NULL) { 599 printf("%s: unable to allocate Tx mbuf\n", 600 device_xname(sc->sc_dev)); 601 break; 602 } 603 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 604 if (m0->m_pkthdr.len > MHLEN) { 605 MCLGET(m, M_DONTWAIT); 606 if ((m->m_flags & M_EXT) == 0) { 607 printf("%s: unable to allocate Tx " 608 "cluster\n", device_xname(sc->sc_dev)); 609 m_freem(m); 610 break; 611 } 612 } 613 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 614 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 615 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 616 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 617 if (error) { 618 printf("%s: unable to load Tx buffer, " 619 "error = %d\n", device_xname(sc->sc_dev), 620 error); 621 break; 622 } 623 } 624 625 /* 626 * Ensure we have enough descriptors free to describe 627 * the packet. 628 */ 629 if (dmamap->dm_nsegs > sc->sc_txfree) { 630 /* 631 * Not enough free descriptors to transmit this 632 * packet. We haven't committed to anything yet, 633 * so just unload the DMA map, put the packet 634 * back on the queue, and punt. Notify the upper 635 * layer that there are no more slots left. 636 * 637 * XXX We could allocate an mbuf and copy, but 638 * XXX it is worth it? 639 */ 640 bus_dmamap_unload(sc->sc_dmat, dmamap); 641 m_freem(m); 642 break; 643 } 644 645 IFQ_DEQUEUE(&ifp->if_snd, m0); 646 if (m != NULL) { 647 m_freem(m0); 648 m0 = m; 649 } 650 651 /* 652 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 653 */ 654 655 /* Sync the DMA map. */ 656 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 657 BUS_DMASYNC_PREWRITE); 658 659 /* 660 * Initialize the transmit descriptors. 661 */ 662 for (nexttx = sc->sc_txnext, seg = 0; 663 seg < dmamap->dm_nsegs; 664 seg++, nexttx = AE_NEXTTX(nexttx)) { 665 /* 666 * If this is the first descriptor we're 667 * enqueueing, don't set the OWN bit just 668 * yet. That could cause a race condition. 669 * We'll do it below. 670 */ 671 sc->sc_txdescs[nexttx].ad_status = 672 (nexttx == firsttx) ? 0 : ADSTAT_OWN; 673 sc->sc_txdescs[nexttx].ad_bufaddr1 = 674 dmamap->dm_segs[seg].ds_addr; 675 sc->sc_txdescs[nexttx].ad_ctl = 676 (dmamap->dm_segs[seg].ds_len << 677 ADCTL_SIZE1_SHIFT) | 678 (nexttx == (AE_NTXDESC - 1) ? 679 ADCTL_ER : 0); 680 lasttx = nexttx; 681 } 682 683 KASSERT(lasttx != -1); 684 685 /* Set `first segment' and `last segment' appropriately. */ 686 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; 687 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; 688 689 #ifdef AE_DEBUG 690 if (ifp->if_flags & IFF_DEBUG) { 691 printf(" txsoft %p transmit chain:\n", txs); 692 for (seg = sc->sc_txnext;; seg = AE_NEXTTX(seg)) { 693 printf(" descriptor %d:\n", seg); 694 printf(" ad_status: 0x%08x\n", 695 sc->sc_txdescs[seg].ad_status); 696 printf(" ad_ctl: 0x%08x\n", 697 sc->sc_txdescs[seg].ad_ctl); 698 printf(" ad_bufaddr1: 0x%08x\n", 699 sc->sc_txdescs[seg].ad_bufaddr1); 700 printf(" ad_bufaddr2: 0x%08x\n", 701 sc->sc_txdescs[seg].ad_bufaddr2); 702 if (seg == lasttx) 703 break; 704 } 705 } 706 #endif 707 708 /* Sync the descriptors we're using. */ 709 AE_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 712 /* 713 * Store a pointer to the packet so we can free it later, 714 * and remember what txdirty will be once the packet is 715 * done. 716 */ 717 txs->txs_mbuf = m0; 718 txs->txs_firstdesc = sc->sc_txnext; 719 txs->txs_lastdesc = lasttx; 720 txs->txs_ndescs = dmamap->dm_nsegs; 721 722 /* Advance the tx pointer. */ 723 sc->sc_txfree -= dmamap->dm_nsegs; 724 sc->sc_txnext = nexttx; 725 726 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 727 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 728 729 /* 730 * Pass the packet to any BPF listeners. 731 */ 732 bpf_mtap(ifp, m0, BPF_D_OUT); 733 } 734 735 if (sc->sc_txfree != ofree) { 736 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 737 device_xname(sc->sc_dev), lasttx, firsttx)); 738 /* 739 * Cause a transmit interrupt to happen on the 740 * last packet we enqueued. 741 */ 742 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; 743 AE_CDTXSYNC(sc, lasttx, 1, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 746 /* 747 * The entire packet chain is set up. Give the 748 * first descriptor to the chip now. 749 */ 750 sc->sc_txdescs[firsttx].ad_status |= ADSTAT_OWN; 751 AE_CDTXSYNC(sc, firsttx, 1, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 754 /* Wake up the transmitter. */ 755 /* XXX USE AUTOPOLLING? */ 756 AE_WRITE(sc, CSR_TXPOLL, TXPOLL_TPD); 757 AE_BARRIER(sc); 758 759 /* Set a watchdog timer in case the chip flakes out. */ 760 ifp->if_timer = 5; 761 } 762 } 763 764 /* 765 * ae_watchdog: [ifnet interface function] 766 * 767 * Watchdog timer handler. 768 */ 769 static void 770 ae_watchdog(struct ifnet *ifp) 771 { 772 struct ae_softc *sc = ifp->if_softc; 773 int doing_transmit; 774 775 doing_transmit = (! SIMPLEQ_EMPTY(&sc->sc_txdirtyq)); 776 777 if (doing_transmit) { 778 printf("%s: transmit timeout\n", device_xname(sc->sc_dev)); 779 if_statinc(ifp, if_oerrors); 780 } 781 else 782 printf("%s: spurious watchdog timeout\n", device_xname(sc->sc_dev)); 783 784 (void) ae_init(ifp); 785 786 /* Try to get more packets going. */ 787 ae_start(ifp); 788 } 789 790 /* If the interface is up and running, only modify the receive 791 * filter when changing to/from promiscuous mode. Otherwise return 792 * ENETRESET so that ether_ioctl will reset the chip. 793 */ 794 static int 795 ae_ifflags_cb(struct ethercom *ec) 796 { 797 struct ifnet *ifp = &ec->ec_if; 798 struct ae_softc *sc = ifp->if_softc; 799 u_short change = ifp->if_flags ^ sc->sc_if_flags; 800 801 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 802 return ENETRESET; 803 else if ((change & IFF_PROMISC) != 0) 804 ae_filter_setup(sc); 805 return 0; 806 } 807 808 /* 809 * ae_ioctl: [ifnet interface function] 810 * 811 * Handle control requests from the operator. 812 */ 813 static int 814 ae_ioctl(struct ifnet *ifp, u_long cmd, void *data) 815 { 816 struct ae_softc *sc = ifp->if_softc; 817 int s, error; 818 819 s = splnet(); 820 821 error = ether_ioctl(ifp, cmd, data); 822 if (error == ENETRESET) { 823 if (ifp->if_flags & IFF_RUNNING) { 824 /* 825 * Multicast list has changed. Set the 826 * hardware filter accordingly. 827 */ 828 ae_filter_setup(sc); 829 } 830 error = 0; 831 } 832 833 /* Try to get more packets going. */ 834 if (AE_IS_ENABLED(sc)) 835 ae_start(ifp); 836 837 sc->sc_if_flags = ifp->if_flags; 838 splx(s); 839 return (error); 840 } 841 842 /* 843 * ae_intr: 844 * 845 * Interrupt service routine. 846 */ 847 int 848 ae_intr(void *arg) 849 { 850 struct ae_softc *sc = arg; 851 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 852 uint32_t status, rxstatus, txstatus; 853 int handled = 0, txthresh; 854 855 DPRINTF(sc, ("%s: ae_intr\n", device_xname(sc->sc_dev))); 856 857 #ifdef DEBUG 858 if (AE_IS_ENABLED(sc) == 0) 859 panic("%s: ae_intr: not enabled", device_xname(sc->sc_dev)); 860 #endif 861 862 /* 863 * If the interface isn't running, the interrupt couldn't 864 * possibly have come from us. 865 */ 866 if ((ifp->if_flags & IFF_RUNNING) == 0 || 867 !device_is_active(sc->sc_dev)) { 868 printf("spurious?!?\n"); 869 return (0); 870 } 871 872 for (;;) { 873 status = AE_READ(sc, CSR_STATUS); 874 if (status) { 875 AE_WRITE(sc, CSR_STATUS, status); 876 AE_BARRIER(sc); 877 } 878 879 if ((status & sc->sc_inten) == 0) 880 break; 881 882 handled = 1; 883 884 rxstatus = status & sc->sc_rxint_mask; 885 txstatus = status & sc->sc_txint_mask; 886 887 if (rxstatus) { 888 /* Grab new any new packets. */ 889 ae_rxintr(sc); 890 891 if (rxstatus & STATUS_RU) { 892 printf("%s: receive ring overrun\n", 893 device_xname(sc->sc_dev)); 894 /* Get the receive process going again. */ 895 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 896 AE_BARRIER(sc); 897 break; 898 } 899 } 900 901 if (txstatus) { 902 /* Sweep up transmit descriptors. */ 903 ae_txintr(sc); 904 905 if (txstatus & STATUS_TJT) 906 printf("%s: transmit jabber timeout\n", 907 device_xname(sc->sc_dev)); 908 909 if (txstatus & STATUS_UNF) { 910 /* 911 * Increase our transmit threshold if 912 * another is available. 913 */ 914 txthresh = sc->sc_txthresh + 1; 915 if (ae_txthresh[txthresh].txth_name != NULL) { 916 uint32_t opmode; 917 /* Idle the transmit process. */ 918 opmode = AE_READ(sc, CSR_OPMODE); 919 ae_idle(sc, OPMODE_ST); 920 921 sc->sc_txthresh = txthresh; 922 opmode &= ~(OPMODE_TR | OPMODE_SF); 923 opmode |= 924 ae_txthresh[txthresh].txth_opmode; 925 printf("%s: transmit underrun; new " 926 "threshold: %s\n", 927 device_xname(sc->sc_dev), 928 ae_txthresh[txthresh].txth_name); 929 930 /* 931 * Set the new threshold and restart 932 * the transmit process. 933 */ 934 AE_WRITE(sc, CSR_OPMODE, opmode); 935 AE_BARRIER(sc); 936 } 937 /* 938 * XXX Log every Nth underrun from 939 * XXX now on? 940 */ 941 } 942 } 943 944 if (status & (STATUS_TPS | STATUS_RPS)) { 945 if (status & STATUS_TPS) 946 printf("%s: transmit process stopped\n", 947 device_xname(sc->sc_dev)); 948 if (status & STATUS_RPS) 949 printf("%s: receive process stopped\n", 950 device_xname(sc->sc_dev)); 951 (void) ae_init(ifp); 952 break; 953 } 954 955 if (status & STATUS_SE) { 956 const char *str; 957 958 if (status & STATUS_TX_ABORT) 959 str = "tx abort"; 960 else if (status & STATUS_RX_ABORT) 961 str = "rx abort"; 962 else 963 str = "unknown error"; 964 965 printf("%s: fatal system error: %s\n", 966 device_xname(sc->sc_dev), str); 967 (void) ae_init(ifp); 968 break; 969 } 970 971 /* 972 * Not handled: 973 * 974 * Transmit buffer unavailable -- normal 975 * condition, nothing to do, really. 976 * 977 * General purpose timer experied -- we don't 978 * use the general purpose timer. 979 * 980 * Early receive interrupt -- not available on 981 * all chips, we just use RI. We also only 982 * use single-segment receive DMA, so this 983 * is mostly useless. 984 */ 985 } 986 987 /* Try to get more packets going. */ 988 if_schedule_deferred_start(ifp); 989 990 if (handled) 991 rnd_add_uint32(&sc->sc_rnd_source, status); 992 return (handled); 993 } 994 995 /* 996 * ae_rxintr: 997 * 998 * Helper; handle receive interrupts. 999 */ 1000 static void 1001 ae_rxintr(struct ae_softc *sc) 1002 { 1003 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1004 struct ae_rxsoft *rxs; 1005 struct mbuf *m; 1006 uint32_t rxstat; 1007 int i, len; 1008 1009 for (i = sc->sc_rxptr;; i = AE_NEXTRX(i)) { 1010 rxs = &sc->sc_rxsoft[i]; 1011 1012 AE_CDRXSYNC(sc, i, 1013 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1014 1015 rxstat = sc->sc_rxdescs[i].ad_status; 1016 1017 if (rxstat & ADSTAT_OWN) { 1018 /* 1019 * We have processed all of the receive buffers. 1020 */ 1021 break; 1022 } 1023 1024 /* 1025 * If any collisions were seen on the wire, count one. 1026 */ 1027 if (rxstat & ADSTAT_Rx_CS) 1028 if_statinc(ifp, if_collisions); 1029 1030 /* 1031 * If an error occurred, update stats, clear the status 1032 * word, and leave the packet buffer in place. It will 1033 * simply be reused the next time the ring comes around. 1034 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 1035 * error. 1036 */ 1037 if (rxstat & ADSTAT_ES && 1038 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) == 0 || 1039 (rxstat & (ADSTAT_Rx_DE | ADSTAT_Rx_RF | 1040 ADSTAT_Rx_DB | ADSTAT_Rx_CE)) != 0)) { 1041 #define PRINTERR(bit, str) \ 1042 if (rxstat & (bit)) \ 1043 printf("%s: receive error: %s\n", \ 1044 device_xname(sc->sc_dev), str) 1045 if_statinc(ifp, if_ierrors); 1046 PRINTERR(ADSTAT_Rx_DE, "descriptor error"); 1047 PRINTERR(ADSTAT_Rx_RF, "runt frame"); 1048 PRINTERR(ADSTAT_Rx_TL, "frame too long"); 1049 PRINTERR(ADSTAT_Rx_RE, "MII error"); 1050 PRINTERR(ADSTAT_Rx_DB, "dribbling bit"); 1051 PRINTERR(ADSTAT_Rx_CE, "CRC error"); 1052 #undef PRINTERR 1053 AE_INIT_RXDESC(sc, i); 1054 continue; 1055 } 1056 1057 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1058 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1059 1060 /* 1061 * No errors; receive the packet. Note the chip 1062 * includes the CRC with every packet. 1063 */ 1064 len = ADSTAT_Rx_LENGTH(rxstat) - ETHER_CRC_LEN; 1065 1066 /* 1067 * XXX: the Atheros part can align on half words. what 1068 * is the performance implication of this? Probably 1069 * minimal, and we should use it... 1070 */ 1071 #ifdef __NO_STRICT_ALIGNMENT 1072 /* 1073 * Allocate a new mbuf cluster. If that fails, we are 1074 * out of memory, and must drop the packet and recycle 1075 * the buffer that's already attached to this descriptor. 1076 */ 1077 m = rxs->rxs_mbuf; 1078 if (ae_add_rxbuf(sc, i) != 0) { 1079 if_statinc(ifp, if_ierrors); 1080 AE_INIT_RXDESC(sc, i); 1081 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1082 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1083 continue; 1084 } 1085 #else 1086 /* 1087 * The chip's receive buffers must be 4-byte aligned. 1088 * But this means that the data after the Ethernet header 1089 * is misaligned. We must allocate a new buffer and 1090 * copy the data, shifted forward 2 bytes. 1091 */ 1092 MGETHDR(m, M_DONTWAIT, MT_DATA); 1093 if (m == NULL) { 1094 dropit: 1095 if_statinc(ifp, if_ierrors); 1096 AE_INIT_RXDESC(sc, i); 1097 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1098 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1099 continue; 1100 } 1101 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1102 if (len > (MHLEN - 2)) { 1103 MCLGET(m, M_DONTWAIT); 1104 if ((m->m_flags & M_EXT) == 0) { 1105 m_freem(m); 1106 goto dropit; 1107 } 1108 } 1109 m->m_data += 2; 1110 1111 /* 1112 * Note that we use clusters for incoming frames, so the 1113 * buffer is virtually contiguous. 1114 */ 1115 memcpy(mtod(m, void *), mtod(rxs->rxs_mbuf, void *), len); 1116 1117 /* Allow the receive descriptor to continue using its mbuf. */ 1118 AE_INIT_RXDESC(sc, i); 1119 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1120 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1121 #endif /* __NO_STRICT_ALIGNMENT */ 1122 1123 m_set_rcvif(m, ifp); 1124 m->m_pkthdr.len = m->m_len = len; 1125 1126 /* Pass it on. */ 1127 if_percpuq_enqueue(ifp->if_percpuq, m); 1128 } 1129 1130 /* Update the receive pointer. */ 1131 sc->sc_rxptr = i; 1132 } 1133 1134 /* 1135 * ae_txintr: 1136 * 1137 * Helper; handle transmit interrupts. 1138 */ 1139 static void 1140 ae_txintr(struct ae_softc *sc) 1141 { 1142 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1143 struct ae_txsoft *txs; 1144 uint32_t txstat; 1145 1146 DPRINTF(sc, ("%s: ae_txintr: sc_flags 0x%08x\n", 1147 device_xname(sc->sc_dev), sc->sc_flags)); 1148 1149 /* 1150 * Go through our Tx list and free mbufs for those 1151 * frames that have been transmitted. 1152 */ 1153 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1154 AE_CDTXSYNC(sc, txs->txs_lastdesc, 1155 txs->txs_ndescs, 1156 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1157 1158 #ifdef AE_DEBUG 1159 if (ifp->if_flags & IFF_DEBUG) { 1160 int i; 1161 printf(" txsoft %p transmit chain:\n", txs); 1162 for (i = txs->txs_firstdesc;; i = AE_NEXTTX(i)) { 1163 printf(" descriptor %d:\n", i); 1164 printf(" ad_status: 0x%08x\n", 1165 sc->sc_txdescs[i].ad_status); 1166 printf(" ad_ctl: 0x%08x\n", 1167 sc->sc_txdescs[i].ad_ctl); 1168 printf(" ad_bufaddr1: 0x%08x\n", 1169 sc->sc_txdescs[i].ad_bufaddr1); 1170 printf(" ad_bufaddr2: 0x%08x\n", 1171 sc->sc_txdescs[i].ad_bufaddr2); 1172 if (i == txs->txs_lastdesc) 1173 break; 1174 } 1175 } 1176 #endif 1177 1178 txstat = sc->sc_txdescs[txs->txs_lastdesc].ad_status; 1179 if (txstat & ADSTAT_OWN) 1180 break; 1181 1182 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1183 1184 sc->sc_txfree += txs->txs_ndescs; 1185 1186 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 1187 0, txs->txs_dmamap->dm_mapsize, 1188 BUS_DMASYNC_POSTWRITE); 1189 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1190 m_freem(txs->txs_mbuf); 1191 txs->txs_mbuf = NULL; 1192 1193 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1194 1195 /* 1196 * Check for errors and collisions. 1197 */ 1198 #ifdef AE_STATS 1199 if (txstat & ADSTAT_Tx_UF) 1200 sc->sc_stats.ts_tx_uf++; 1201 if (txstat & ADSTAT_Tx_TO) 1202 sc->sc_stats.ts_tx_to++; 1203 if (txstat & ADSTAT_Tx_EC) 1204 sc->sc_stats.ts_tx_ec++; 1205 if (txstat & ADSTAT_Tx_LC) 1206 sc->sc_stats.ts_tx_lc++; 1207 #endif 1208 1209 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1210 if (txstat & (ADSTAT_Tx_UF | ADSTAT_Tx_TO)) 1211 if_statinc_ref(ifp, nsr, if_oerrors); 1212 1213 if (txstat & ADSTAT_Tx_EC) 1214 if_statadd_ref(ifp, nsr, if_collisions, 16); 1215 else if (ADSTAT_Tx_COLLISIONS(txstat)) 1216 if_statadd_ref(ifp, nsr, if_collisions, 1217 ADSTAT_Tx_COLLISIONS(txstat)); 1218 if (txstat & ADSTAT_Tx_LC) 1219 if_statinc_ref(ifp, nsr, if_collisions); 1220 1221 if_statinc_ref(ifp, nsr, if_opackets); 1222 IF_STAT_PUTREF(ifp); 1223 } 1224 1225 /* 1226 * If there are no more pending transmissions, cancel the watchdog 1227 * timer. 1228 */ 1229 if (txs == NULL) 1230 ifp->if_timer = 0; 1231 } 1232 1233 #ifdef AE_STATS 1234 void 1235 ae_print_stats(struct ae_softc *sc) 1236 { 1237 1238 printf("%s: tx_uf %lu, tx_to %lu, tx_ec %lu, tx_lc %lu\n", 1239 device_xname(sc->sc_dev), 1240 sc->sc_stats.ts_tx_uf, sc->sc_stats.ts_tx_to, 1241 sc->sc_stats.ts_tx_ec, sc->sc_stats.ts_tx_lc); 1242 } 1243 #endif 1244 1245 /* 1246 * ae_reset: 1247 * 1248 * Perform a soft reset on the chip. 1249 */ 1250 void 1251 ae_reset(struct ae_softc *sc) 1252 { 1253 int i; 1254 1255 AE_WRITE(sc, CSR_BUSMODE, BUSMODE_SWR); 1256 AE_BARRIER(sc); 1257 1258 /* 1259 * The chip doesn't take itself out of reset automatically. 1260 * We need to do so after 2us. 1261 */ 1262 delay(10); 1263 AE_WRITE(sc, CSR_BUSMODE, 0); 1264 AE_BARRIER(sc); 1265 1266 for (i = 0; i < 1000; i++) { 1267 /* 1268 * Wait a bit for the reset to complete before peeking 1269 * at the chip again. 1270 */ 1271 delay(10); 1272 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR) == 0) 1273 break; 1274 } 1275 1276 if (AE_ISSET(sc, CSR_BUSMODE, BUSMODE_SWR)) 1277 printf("%s: reset failed to complete\n", device_xname(sc->sc_dev)); 1278 1279 delay(1000); 1280 } 1281 1282 /* 1283 * ae_init: [ ifnet interface function ] 1284 * 1285 * Initialize the interface. Must be called at splnet(). 1286 */ 1287 static int 1288 ae_init(struct ifnet *ifp) 1289 { 1290 struct ae_softc *sc = ifp->if_softc; 1291 struct ae_txsoft *txs; 1292 struct ae_rxsoft *rxs; 1293 const uint8_t *enaddr; 1294 int i, error = 0; 1295 1296 if ((error = ae_enable(sc)) != 0) 1297 goto out; 1298 1299 /* 1300 * Cancel any pending I/O. 1301 */ 1302 ae_stop(ifp, 0); 1303 1304 /* 1305 * Reset the chip to a known state. 1306 */ 1307 ae_reset(sc); 1308 1309 /* 1310 * Initialize the BUSMODE register. 1311 */ 1312 AE_WRITE(sc, CSR_BUSMODE, 1313 /* XXX: not sure if this is a good thing or not... */ 1314 //BUSMODE_ALIGN_16B | 1315 BUSMODE_BAR | BUSMODE_BLE | BUSMODE_PBL_4LW); 1316 AE_BARRIER(sc); 1317 1318 /* 1319 * Initialize the transmit descriptor ring. 1320 */ 1321 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1322 for (i = 0; i < AE_NTXDESC; i++) { 1323 sc->sc_txdescs[i].ad_ctl = 0; 1324 sc->sc_txdescs[i].ad_bufaddr2 = 1325 AE_CDTXADDR(sc, AE_NEXTTX(i)); 1326 } 1327 sc->sc_txdescs[AE_NTXDESC - 1].ad_ctl |= ADCTL_ER; 1328 AE_CDTXSYNC(sc, 0, AE_NTXDESC, 1329 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1330 sc->sc_txfree = AE_NTXDESC; 1331 sc->sc_txnext = 0; 1332 1333 /* 1334 * Initialize the transmit job descriptors. 1335 */ 1336 SIMPLEQ_INIT(&sc->sc_txfreeq); 1337 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1338 for (i = 0; i < AE_TXQUEUELEN; i++) { 1339 txs = &sc->sc_txsoft[i]; 1340 txs->txs_mbuf = NULL; 1341 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1342 } 1343 1344 /* 1345 * Initialize the receive descriptor and receive job 1346 * descriptor rings. 1347 */ 1348 for (i = 0; i < AE_NRXDESC; i++) { 1349 rxs = &sc->sc_rxsoft[i]; 1350 if (rxs->rxs_mbuf == NULL) { 1351 if ((error = ae_add_rxbuf(sc, i)) != 0) { 1352 printf("%s: unable to allocate or map rx " 1353 "buffer %d, error = %d\n", 1354 device_xname(sc->sc_dev), i, error); 1355 /* 1356 * XXX Should attempt to run with fewer receive 1357 * XXX buffers instead of just failing. 1358 */ 1359 ae_rxdrain(sc); 1360 goto out; 1361 } 1362 } else 1363 AE_INIT_RXDESC(sc, i); 1364 } 1365 sc->sc_rxptr = 0; 1366 1367 /* 1368 * Initialize the interrupt mask and enable interrupts. 1369 */ 1370 /* normal interrupts */ 1371 sc->sc_inten = STATUS_TI | STATUS_TU | STATUS_RI | STATUS_NIS; 1372 1373 /* abnormal interrupts */ 1374 sc->sc_inten |= STATUS_TPS | STATUS_TJT | STATUS_UNF | 1375 STATUS_RU | STATUS_RPS | STATUS_SE | STATUS_AIS; 1376 1377 sc->sc_rxint_mask = STATUS_RI | STATUS_RU; 1378 sc->sc_txint_mask = STATUS_TI | STATUS_UNF | STATUS_TJT; 1379 1380 sc->sc_rxint_mask &= sc->sc_inten; 1381 sc->sc_txint_mask &= sc->sc_inten; 1382 1383 AE_WRITE(sc, CSR_INTEN, sc->sc_inten); 1384 AE_WRITE(sc, CSR_STATUS, 0xffffffff); 1385 1386 /* 1387 * Give the transmit and receive rings to the chip. 1388 */ 1389 AE_WRITE(sc, CSR_TXLIST, AE_CDTXADDR(sc, sc->sc_txnext)); 1390 AE_WRITE(sc, CSR_RXLIST, AE_CDRXADDR(sc, sc->sc_rxptr)); 1391 AE_BARRIER(sc); 1392 1393 /* 1394 * Set the station address. 1395 */ 1396 enaddr = CLLADDR(ifp->if_sadl); 1397 AE_WRITE(sc, CSR_MACHI, enaddr[5] << 16 | enaddr[4]); 1398 AE_WRITE(sc, CSR_MACLO, enaddr[3] << 24 | enaddr[2] << 16 | 1399 enaddr[1] << 8 | enaddr[0]); 1400 AE_BARRIER(sc); 1401 1402 /* 1403 * Set the receive filter. This will start the transmit and 1404 * receive processes. 1405 */ 1406 ae_filter_setup(sc); 1407 1408 /* 1409 * Set the current media. 1410 */ 1411 if ((error = ether_mediachange(ifp)) != 0) 1412 goto out; 1413 1414 /* 1415 * Start the mac. 1416 */ 1417 AE_SET(sc, CSR_MACCTL, MACCTL_RE | MACCTL_TE); 1418 AE_BARRIER(sc); 1419 1420 /* 1421 * Write out the opmode. 1422 */ 1423 AE_WRITE(sc, CSR_OPMODE, OPMODE_SR | OPMODE_ST | 1424 ae_txthresh[sc->sc_txthresh].txth_opmode); 1425 /* 1426 * Start the receive process. 1427 */ 1428 AE_WRITE(sc, CSR_RXPOLL, RXPOLL_RPD); 1429 AE_BARRIER(sc); 1430 1431 if (sc->sc_tick != NULL) { 1432 /* Start the one second clock. */ 1433 callout_reset(&sc->sc_tick_callout, hz >> 3, sc->sc_tick, sc); 1434 } 1435 1436 /* 1437 * Note that the interface is now running. 1438 */ 1439 ifp->if_flags |= IFF_RUNNING; 1440 sc->sc_if_flags = ifp->if_flags; 1441 1442 out: 1443 if (error) { 1444 ifp->if_flags &= ~IFF_RUNNING; 1445 ifp->if_timer = 0; 1446 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1447 } 1448 return (error); 1449 } 1450 1451 /* 1452 * ae_enable: 1453 * 1454 * Enable the chip. 1455 */ 1456 static int 1457 ae_enable(struct ae_softc *sc) 1458 { 1459 1460 if (AE_IS_ENABLED(sc) == 0) { 1461 sc->sc_ih = arbus_intr_establish(sc->sc_cirq, sc->sc_mirq, 1462 ae_intr, sc); 1463 if (sc->sc_ih == NULL) { 1464 printf("%s: unable to establish interrupt\n", 1465 device_xname(sc->sc_dev)); 1466 return (EIO); 1467 } 1468 sc->sc_flags |= AE_ENABLED; 1469 } 1470 return (0); 1471 } 1472 1473 /* 1474 * ae_disable: 1475 * 1476 * Disable the chip. 1477 */ 1478 static void 1479 ae_disable(struct ae_softc *sc) 1480 { 1481 1482 if (AE_IS_ENABLED(sc)) { 1483 arbus_intr_disestablish(sc->sc_ih); 1484 sc->sc_flags &= ~AE_ENABLED; 1485 } 1486 } 1487 1488 /* 1489 * ae_power: 1490 * 1491 * Power management (suspend/resume) hook. 1492 */ 1493 static void 1494 ae_power(int why, void *arg) 1495 { 1496 struct ae_softc *sc = arg; 1497 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1498 int s; 1499 1500 printf("power called: %d, %x\n", why, (uint32_t)arg); 1501 s = splnet(); 1502 switch (why) { 1503 case PWR_STANDBY: 1504 /* do nothing! */ 1505 break; 1506 case PWR_SUSPEND: 1507 ae_stop(ifp, 0); 1508 ae_disable(sc); 1509 break; 1510 case PWR_RESUME: 1511 if (ifp->if_flags & IFF_UP) { 1512 ae_enable(sc); 1513 ae_init(ifp); 1514 } 1515 break; 1516 case PWR_SOFTSUSPEND: 1517 case PWR_SOFTSTANDBY: 1518 case PWR_SOFTRESUME: 1519 break; 1520 } 1521 splx(s); 1522 } 1523 1524 /* 1525 * ae_rxdrain: 1526 * 1527 * Drain the receive queue. 1528 */ 1529 static void 1530 ae_rxdrain(struct ae_softc *sc) 1531 { 1532 struct ae_rxsoft *rxs; 1533 int i; 1534 1535 for (i = 0; i < AE_NRXDESC; i++) { 1536 rxs = &sc->sc_rxsoft[i]; 1537 if (rxs->rxs_mbuf != NULL) { 1538 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1539 m_freem(rxs->rxs_mbuf); 1540 rxs->rxs_mbuf = NULL; 1541 } 1542 } 1543 } 1544 1545 /* 1546 * ae_stop: [ ifnet interface function ] 1547 * 1548 * Stop transmission on the interface. 1549 */ 1550 static void 1551 ae_stop(struct ifnet *ifp, int disable) 1552 { 1553 struct ae_softc *sc = ifp->if_softc; 1554 struct ae_txsoft *txs; 1555 1556 if (sc->sc_tick != NULL) { 1557 /* Stop the one second clock. */ 1558 callout_stop(&sc->sc_tick_callout); 1559 } 1560 1561 /* Down the MII. */ 1562 mii_down(&sc->sc_mii); 1563 1564 /* Disable interrupts. */ 1565 AE_WRITE(sc, CSR_INTEN, 0); 1566 1567 /* Stop the transmit and receive processes. */ 1568 AE_WRITE(sc, CSR_OPMODE, 0); 1569 AE_WRITE(sc, CSR_RXLIST, 0); 1570 AE_WRITE(sc, CSR_TXLIST, 0); 1571 AE_CLR(sc, CSR_MACCTL, MACCTL_TE | MACCTL_RE); 1572 AE_BARRIER(sc); 1573 1574 /* 1575 * Release any queued transmit buffers. 1576 */ 1577 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1578 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1579 if (txs->txs_mbuf != NULL) { 1580 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 1581 m_freem(txs->txs_mbuf); 1582 txs->txs_mbuf = NULL; 1583 } 1584 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1585 } 1586 1587 /* 1588 * Mark the interface down and cancel the watchdog timer. 1589 */ 1590 ifp->if_flags &= ~IFF_RUNNING; 1591 sc->sc_if_flags = ifp->if_flags; 1592 ifp->if_timer = 0; 1593 1594 if (disable) { 1595 ae_rxdrain(sc); 1596 ae_disable(sc); 1597 } 1598 1599 /* 1600 * Reset the chip (needed on some flavors to actually disable it). 1601 */ 1602 ae_reset(sc); 1603 } 1604 1605 /* 1606 * ae_add_rxbuf: 1607 * 1608 * Add a receive buffer to the indicated descriptor. 1609 */ 1610 static int 1611 ae_add_rxbuf(struct ae_softc *sc, int idx) 1612 { 1613 struct ae_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1614 struct mbuf *m; 1615 int error; 1616 1617 MGETHDR(m, M_DONTWAIT, MT_DATA); 1618 if (m == NULL) 1619 return (ENOBUFS); 1620 1621 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1622 MCLGET(m, M_DONTWAIT); 1623 if ((m->m_flags & M_EXT) == 0) { 1624 m_freem(m); 1625 return (ENOBUFS); 1626 } 1627 1628 if (rxs->rxs_mbuf != NULL) 1629 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1630 1631 rxs->rxs_mbuf = m; 1632 1633 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 1634 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1635 BUS_DMA_READ | BUS_DMA_NOWAIT); 1636 if (error) { 1637 printf("%s: can't load rx DMA map %d, error = %d\n", 1638 device_xname(sc->sc_dev), idx, error); 1639 panic("ae_add_rxbuf"); /* XXX */ 1640 } 1641 1642 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 1643 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1644 1645 AE_INIT_RXDESC(sc, idx); 1646 1647 return (0); 1648 } 1649 1650 /* 1651 * ae_filter_setup: 1652 * 1653 * Set the chip's receive filter. 1654 */ 1655 static void 1656 ae_filter_setup(struct ae_softc *sc) 1657 { 1658 struct ethercom *ec = &sc->sc_ethercom; 1659 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1660 struct ether_multi *enm; 1661 struct ether_multistep step; 1662 uint32_t hash, mchash[2]; 1663 uint32_t macctl = 0; 1664 1665 /* 1666 * If the chip is running, we need to reset the interface, 1667 * and will revisit here (with IFF_RUNNING) clear. The 1668 * chip seems to really not like to have its multicast 1669 * filter programmed without a reset. 1670 */ 1671 if (ifp->if_flags & IFF_RUNNING) { 1672 (void) ae_init(ifp); 1673 return; 1674 } 1675 1676 DPRINTF(sc, ("%s: ae_filter_setup: sc_flags 0x%08x\n", 1677 device_xname(sc->sc_dev), sc->sc_flags)); 1678 1679 macctl = AE_READ(sc, CSR_MACCTL); 1680 macctl &= ~(MACCTL_PR | MACCTL_PM); 1681 macctl |= MACCTL_HASH; 1682 macctl |= MACCTL_HBD; 1683 macctl |= MACCTL_PR; 1684 1685 if (ifp->if_flags & IFF_PROMISC) { 1686 macctl |= MACCTL_PR; 1687 goto allmulti; 1688 } 1689 1690 mchash[0] = mchash[1] = 0; 1691 1692 ETHER_LOCK(ec); 1693 ETHER_FIRST_MULTI(step, ec, enm); 1694 while (enm != NULL) { 1695 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1696 /* 1697 * We must listen to a range of multicast addresses. 1698 * For now, just accept all multicasts, rather than 1699 * trying to set only those filter bits needed to match 1700 * the range. (At this time, the only use of address 1701 * ranges is for IP multicast routing, for which the 1702 * range is big enough to require all bits set.) 1703 */ 1704 ETHER_UNLOCK(ec); 1705 goto allmulti; 1706 } 1707 1708 /* Verify whether we use big or little endian hashes */ 1709 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3f; 1710 mchash[hash >> 5] |= 1 << (hash & 0x1f); 1711 ETHER_NEXT_MULTI(step, enm); 1712 } 1713 ETHER_UNLOCK(ec); 1714 ifp->if_flags &= ~IFF_ALLMULTI; 1715 goto setit; 1716 1717 allmulti: 1718 ifp->if_flags |= IFF_ALLMULTI; 1719 mchash[0] = mchash[1] = 0xffffffff; 1720 macctl |= MACCTL_PM; 1721 1722 setit: 1723 AE_WRITE(sc, CSR_HTHI, mchash[0]); 1724 AE_WRITE(sc, CSR_HTHI, mchash[1]); 1725 1726 AE_WRITE(sc, CSR_MACCTL, macctl); 1727 AE_BARRIER(sc); 1728 1729 DPRINTF(sc, ("%s: ae_filter_setup: returning %x\n", 1730 device_xname(sc->sc_dev), macctl)); 1731 } 1732 1733 /* 1734 * ae_idle: 1735 * 1736 * Cause the transmit and/or receive processes to go idle. 1737 */ 1738 void 1739 ae_idle(struct ae_softc *sc, uint32_t bits) 1740 { 1741 static const char * const txstate_names[] = { 1742 "STOPPED", 1743 "RUNNING - FETCH", 1744 "RUNNING - WAIT", 1745 "RUNNING - READING", 1746 "-- RESERVED --", 1747 "RUNNING - SETUP", 1748 "SUSPENDED", 1749 "RUNNING - CLOSE", 1750 }; 1751 static const char * const rxstate_names[] = { 1752 "STOPPED", 1753 "RUNNING - FETCH", 1754 "RUNNING - CHECK", 1755 "RUNNING - WAIT", 1756 "SUSPENDED", 1757 "RUNNING - CLOSE", 1758 "RUNNING - FLUSH", 1759 "RUNNING - QUEUE", 1760 }; 1761 1762 uint32_t csr, ackmask = 0; 1763 int i; 1764 1765 if (bits & OPMODE_ST) 1766 ackmask |= STATUS_TPS; 1767 1768 if (bits & OPMODE_SR) 1769 ackmask |= STATUS_RPS; 1770 1771 AE_CLR(sc, CSR_OPMODE, bits); 1772 1773 for (i = 0; i < 1000; i++) { 1774 if (AE_ISSET(sc, CSR_STATUS, ackmask) == ackmask) 1775 break; 1776 delay(10); 1777 } 1778 1779 csr = AE_READ(sc, CSR_STATUS); 1780 if ((csr & ackmask) != ackmask) { 1781 if ((bits & OPMODE_ST) != 0 && (csr & STATUS_TPS) == 0 && 1782 (csr & STATUS_TS) != STATUS_TS_STOPPED) { 1783 printf("%s: transmit process failed to idle: " 1784 "state %s\n", device_xname(sc->sc_dev), 1785 txstate_names[(csr & STATUS_TS) >> 20]); 1786 } 1787 if ((bits & OPMODE_SR) != 0 && (csr & STATUS_RPS) == 0 && 1788 (csr & STATUS_RS) != STATUS_RS_STOPPED) { 1789 printf("%s: receive process failed to idle: " 1790 "state %s\n", device_xname(sc->sc_dev), 1791 rxstate_names[(csr & STATUS_RS) >> 17]); 1792 } 1793 } 1794 } 1795 1796 /***************************************************************************** 1797 * Support functions for MII-attached media. 1798 *****************************************************************************/ 1799 1800 /* 1801 * ae_mii_tick: 1802 * 1803 * One second timer, used to tick the MII. 1804 */ 1805 static void 1806 ae_mii_tick(void *arg) 1807 { 1808 struct ae_softc *sc = arg; 1809 int s; 1810 1811 if (!device_is_active(sc->sc_dev)) 1812 return; 1813 1814 s = splnet(); 1815 mii_tick(&sc->sc_mii); 1816 splx(s); 1817 1818 callout_reset(&sc->sc_tick_callout, hz, sc->sc_tick, sc); 1819 } 1820 1821 /* 1822 * ae_mii_statchg: [mii interface function] 1823 * 1824 * Callback from PHY when media changes. 1825 */ 1826 static void 1827 ae_mii_statchg(struct ifnet *ifp) 1828 { 1829 struct ae_softc *sc = ifp->if_softc; 1830 uint32_t macctl, flowc; 1831 1832 //opmode = AE_READ(sc, CSR_OPMODE); 1833 macctl = AE_READ(sc, CSR_MACCTL); 1834 1835 /* XXX: do we need to do this? */ 1836 /* Idle the transmit and receive processes. */ 1837 //ae_idle(sc, OPMODE_ST | OPMODE_SR); 1838 1839 if (sc->sc_mii.mii_media_active & IFM_FDX) { 1840 flowc = FLOWC_FCE; 1841 macctl &= ~MACCTL_DRO; 1842 macctl |= MACCTL_FDX; 1843 } else { 1844 flowc = 0; /* cannot do flow control in HDX */ 1845 macctl |= MACCTL_DRO; 1846 macctl &= ~MACCTL_FDX; 1847 } 1848 1849 AE_WRITE(sc, CSR_FLOWC, flowc); 1850 AE_WRITE(sc, CSR_MACCTL, macctl); 1851 1852 /* restore operational mode */ 1853 //AE_WRITE(sc, CSR_OPMODE, opmode); 1854 AE_BARRIER(sc); 1855 } 1856 1857 /* 1858 * ae_mii_readreg: 1859 * 1860 * Read a PHY register. 1861 */ 1862 static int 1863 ae_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1864 { 1865 struct ae_softc *sc = device_private(self); 1866 uint32_t addr; 1867 int i; 1868 1869 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT); 1870 AE_WRITE(sc, CSR_MIIADDR, addr); 1871 AE_BARRIER(sc); 1872 for (i = 0; i < 100000000; i++) { 1873 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1874 break; 1875 } 1876 1877 if (i >= 100000000) 1878 return ETIMEDOUT; 1879 1880 *val = AE_READ(sc, CSR_MIIDATA) & 0xffff; 1881 return 0; 1882 } 1883 1884 /* 1885 * ae_mii_writereg: 1886 * 1887 * Write a PHY register. 1888 */ 1889 static int 1890 ae_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1891 { 1892 struct ae_softc *sc = device_private(self); 1893 uint32_t addr; 1894 int i; 1895 1896 /* write the data register */ 1897 AE_WRITE(sc, CSR_MIIDATA, val); 1898 1899 /* write the address to latch it in */ 1900 addr = (phy << MIIADDR_PHY_SHIFT) | (reg << MIIADDR_REG_SHIFT) | 1901 MIIADDR_WRITE; 1902 AE_WRITE(sc, CSR_MIIADDR, addr); 1903 AE_BARRIER(sc); 1904 1905 for (i = 0; i < 100000000; i++) { 1906 if ((AE_READ(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) 1907 break; 1908 } 1909 1910 if (i >= 100000000) 1911 return ETIMEDOUT; 1912 1913 return 0; 1914 } 1915
Indexes created Tue Sep 23 23:09:58 GMT 2025