1 /* $NetBSD: if_agereg.h,v 1.3 2009/07/28 21:03:46 cegger Exp $ */ 2 /* $OpenBSD: if_agereg.h,v 1.1 2009/01/16 05:00:34 kevlo Exp $ */ 3 4 /*- 5 * Copyright (c) 2008, Pyun YongHyeon <yongari (at) FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: src/sys/dev/age/if_agereg.h,v 1.1 2008/05/19 01:39:59 yongari Exp $ 31 */ 32 33 #ifndef _IF_AGEREG_H 34 #define _IF_AGEREG_H 35 36 #define AGE_PCIR_BAR 0x10 37 38 #define AGE_VPD_REG_CONF_START 0x0100 39 #define AGE_VPD_REG_CONF_END 0x01FF 40 #define AGE_VPD_REG_CONF_SIG 0x5A 41 42 #define AGE_SPI_CTRL 0x200 43 #define SPI_STAT_NOT_READY 0x00000001 44 #define SPI_STAT_WR_ENB 0x00000002 45 #define SPI_STAT_WRP_ENB 0x00000080 46 #define SPI_INST_MASK 0x000000FF 47 #define SPI_START 0x00000100 48 #define SPI_INST_START 0x00000800 49 #define SPI_VPD_ENB 0x00002000 50 #define SPI_LOADER_START 0x00008000 51 #define SPI_CS_HI_MASK 0x00030000 52 #define SPI_CS_HOLD_MASK 0x000C0000 53 #define SPI_CLK_LO_MASK 0x00300000 54 #define SPI_CLK_HI_MASK 0x00C00000 55 #define SPI_CS_SETUP_MASK 0x03000000 56 #define SPI_EPROM_PG_MASK 0x0C000000 57 #define SPI_INST_SHIFT 8 58 #define SPI_CS_HI_SHIFT 16 59 #define SPI_CS_HOLD_SHIFT 18 60 #define SPI_CLK_LO_SHIFT 20 61 #define SPI_CLK_HI_SHIFT 22 62 #define SPI_CS_SETUP_SHIFT 24 63 #define SPI_EPROM_PG_SHIFT 26 64 #define SPI_WAIT_READY 0x10000000 65 66 #define AGE_SPI_ADDR 0x204 /* 16bits */ 67 68 #define AGE_SPI_DATA 0x208 69 70 #define AGE_SPI_CONFIG 0x20C 71 72 #define AGE_SPI_OP_PROGRAM 0x210 /* 8bits */ 73 74 #define AGE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 75 76 #define AGE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 77 78 #define AGE_SPI_OP_RDID 0x213 /* 8bits */ 79 80 #define AGE_SPI_OP_WREN 0x214 /* 8bits */ 81 82 #define AGE_SPI_OP_RDSR 0x215 /* 8bits */ 83 84 #define AGE_SPI_OP_WRSR 0x216 /* 8bits */ 85 86 #define AGE_SPI_OP_READ 0x217 /* 8bits */ 87 88 #define AGE_TWSI_CTRL 0x218 89 #define TWSI_CTRL_SW_LD_START 0x00000800 90 #define TWSI_CTRL_HW_LD_START 0x00001000 91 #define TWSI_CTRL_LD_EXIST 0x00400000 92 93 #define AGE_DEV_MISC_CTRL 0x21C 94 95 #define AGE_MASTER_CFG 0x1400 96 #define MASTER_RESET 0x00000001 97 #define MASTER_MTIMER_ENB 0x00000002 98 #define MASTER_ITIMER_ENB 0x00000004 99 #define MASTER_MANUAL_INT_ENB 0x00000008 100 #define MASTER_CHIP_REV_MASK 0x00FF0000 101 #define MASTER_CHIP_ID_MASK 0xFF000000 102 #define MASTER_CHIP_REV_SHIFT 16 103 #define MASTER_CHIP_ID_SHIFT 24 104 105 /* Number of ticks per usec for L1. */ 106 #define AGE_TICK_USECS 2 107 #define AGE_USECS(x) ((x) / AGE_TICK_USECS) 108 109 #define AGE_MANUAL_TIMER 0x1404 110 111 #define AGE_IM_TIMER 0x1408 /* 16bits */ 112 #define AGE_IM_TIMER_MIN 0 113 #define AGE_IM_TIMER_MAX 130000 /* 130ms */ 114 #define AGE_IM_TIMER_DEFAULT 100 115 116 #define AGE_GPHY_CTRL 0x140C /* 16bits */ 117 #define GPHY_CTRL_RST 0x0000 118 #define GPHY_CTRL_CLR 0x0001 119 120 #define AGE_INTR_CLR_TIMER 0x140E /* 16bits */ 121 122 #define AGE_IDLE_STATUS 0x1410 123 #define IDLE_STATUS_RXMAC 0x00000001 124 #define IDLE_STATUS_TXMAC 0x00000002 125 #define IDLE_STATUS_RXQ 0x00000004 126 #define IDLE_STATUS_TXQ 0x00000008 127 #define IDLE_STATUS_DMARD 0x00000010 128 #define IDLE_STATUS_DMAWR 0x00000020 129 #define IDLE_STATUS_SMB 0x00000040 130 #define IDLE_STATUS_CMB 0x00000080 131 132 #define AGE_MDIO 0x1414 133 #define MDIO_DATA_MASK 0x0000FFFF 134 #define MDIO_REG_ADDR_MASK 0x001F0000 135 #define MDIO_OP_READ 0x00200000 136 #define MDIO_OP_WRITE 0x00000000 137 #define MDIO_SUP_PREAMBLE 0x00400000 138 #define MDIO_OP_EXECUTE 0x00800000 139 #define MDIO_CLK_25_4 0x00000000 140 #define MDIO_CLK_25_6 0x02000000 141 #define MDIO_CLK_25_8 0x03000000 142 #define MDIO_CLK_25_10 0x04000000 143 #define MDIO_CLK_25_14 0x05000000 144 #define MDIO_CLK_25_20 0x06000000 145 #define MDIO_CLK_25_28 0x07000000 146 #define MDIO_OP_BUSY 0x08000000 147 #define MDIO_DATA_SHIFT 0 148 #define MDIO_REG_ADDR_SHIFT 16 149 150 #define MDIO_REG_ADDR(x) \ 151 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 152 /* Default PHY address. */ 153 #define AGE_PHY_ADDR 0 154 155 #define AGE_PHY_STATUS 0x1418 156 157 #define AGE_BIST0 0x141C 158 #define BIST0_ENB 0x00000001 159 #define BIST0_SRAM_FAIL 0x00000002 160 #define BIST0_FUSE_FLAG 0x00000004 161 162 #define AGE_BIST1 0x1420 163 #define BIST1_ENB 0x00000001 164 #define BIST1_SRAM_FAIL 0x00000002 165 #define BIST1_FUSE_FLAG 0x00000004 166 167 #define AGE_MAC_CFG 0x1480 168 #define MAC_CFG_TX_ENB 0x00000001 169 #define MAC_CFG_RX_ENB 0x00000002 170 #define MAC_CFG_TX_FC 0x00000004 171 #define MAC_CFG_RX_FC 0x00000008 172 #define MAC_CFG_LOOP 0x00000010 173 #define MAC_CFG_FULL_DUPLEX 0x00000020 174 #define MAC_CFG_TX_CRC_ENB 0x00000040 175 #define MAC_CFG_TX_AUTO_PAD 0x00000080 176 #define MAC_CFG_TX_LENCHK 0x00000100 177 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 178 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 179 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 180 #define MAC_CFG_PROMISC 0x00008000 181 #define MAC_CFG_TX_PAUSE 0x00010000 182 #define MAC_CFG_SCNT 0x00020000 183 #define MAC_CFG_SYNC_RST_TX 0x00040000 184 #define MAC_CFG_SPEED_MASK 0x00300000 185 #define MAC_CFG_SPEED_10_100 0x00100000 186 #define MAC_CFG_SPEED_1000 0x00200000 187 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 188 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 189 #define MAC_CFG_RXCSUM_ENB 0x01000000 190 #define MAC_CFG_ALLMULTI 0x02000000 191 #define MAC_CFG_BCAST 0x04000000 192 #define MAC_CFG_DBG 0x08000000 193 #define MAC_CFG_PREAMBLE_SHIFT 10 194 #define MAC_CFG_PREAMBLE_DEFAULT 7 195 196 #define AGE_IPG_IFG_CFG 0x1484 197 #define IPG_IFG_IPGT_MASK 0x0000007F 198 #define IPG_IFG_MIFG_MASK 0x0000FF00 199 #define IPG_IFG_IPG1_MASK 0x007F0000 200 #define IPG_IFG_IPG2_MASK 0x7F000000 201 #define IPG_IFG_IPGT_SHIFT 0 202 #define IPG_IFG_IPGT_DEFAULT 0x60 203 #define IPG_IFG_MIFG_SHIFT 8 204 #define IPG_IFG_MIFG_DEFAULT 0x50 205 #define IPG_IFG_IPG1_SHIFT 16 206 #define IPG_IFG_IPG1_DEFAULT 0x40 207 #define IPG_IFG_IPG2_SHIFT 24 208 #define IPG_IFG_IPG2_DEFAULT 0x60 209 210 /* station address */ 211 #define AGE_PAR0 0x1488 212 #define AGE_PAR1 0x148C 213 214 /* 64bit multicast hash register. */ 215 #define AGE_MAR0 0x1490 216 #define AGE_MAR1 0x1494 217 218 /* half-duplex parameter configuration. */ 219 #define AGE_HDPX_CFG 0x1498 220 #define HDPX_CFG_LCOL_MASK 0x000003FF 221 #define HDPX_CFG_RETRY_MASK 0x0000F000 222 #define HDPX_CFG_EXC_DEF_EN 0x00010000 223 #define HDPX_CFG_NO_BACK_C 0x00020000 224 #define HDPX_CFG_NO_BACK_P 0x00040000 225 #define HDPX_CFG_ABEBE 0x00080000 226 #define HDPX_CFG_ABEBT_MASK 0x00F00000 227 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 228 #define HDPX_CFG_LCOL_SHIFT 0 229 #define HDPX_CFG_LCOL_DEFAULT 0x37 230 #define HDPX_CFG_RETRY_SHIFT 12 231 #define HDPX_CFG_RETRY_DEFAULT 0x0F 232 #define HDPX_CFG_ABEBT_SHIFT 20 233 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 234 #define HDPX_CFG_JAMIPG_SHIFT 24 235 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 236 237 #define AGE_FRAME_SIZE 0x149C 238 239 #define AGE_WOL_CFG 0x14A0 240 #define WOL_CFG_PATTERN 0x00000001 241 #define WOL_CFG_PATTERN_ENB 0x00000002 242 #define WOL_CFG_MAGIC 0x00000004 243 #define WOL_CFG_MAGIC_ENB 0x00000008 244 #define WOL_CFG_LINK_CHG 0x00000010 245 #define WOL_CFG_LINK_CHG_ENB 0x00000020 246 #define WOL_CFG_PATTERN_DET 0x00000100 247 #define WOL_CFG_MAGIC_DET 0x00000200 248 #define WOL_CFG_LINK_CHG_DET 0x00000400 249 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 250 #define WOL_CFG_PATTERN0 0x00010000 251 #define WOL_CFG_PATTERN1 0x00020000 252 #define WOL_CFG_PATTERN2 0x00040000 253 #define WOL_CFG_PATTERN3 0x00080000 254 #define WOL_CFG_PATTERN4 0x00100000 255 #define WOL_CFG_PATTERN5 0x00200000 256 #define WOL_CFG_PATTERN6 0x00400000 257 258 /* WOL pattern length. */ 259 #define AGE_PATTERN_CFG0 0x14A4 260 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 261 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 262 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 263 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 264 265 #define AGE_PATTERN_CFG1 0x14A8 266 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 267 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 268 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 269 270 #define AGE_SRAM_RD_ADDR 0x1500 271 272 #define AGE_SRAM_RD_LEN 0x1504 273 274 #define AGE_SRAM_RRD_ADDR 0x1508 275 276 #define AGE_SRAM_RRD_LEN 0x150C 277 278 #define AGE_SRAM_TPD_ADDR 0x1510 279 280 #define AGE_SRAM_TPD_LEN 0x1514 281 282 #define AGE_SRAM_TRD_ADDR 0x1518 283 284 #define AGE_SRAM_TRD_LEN 0x151C 285 286 #define AGE_SRAM_RX_FIFO_ADDR 0x1520 287 288 #define AGE_SRAM_RX_FIFO_LEN 0x1524 289 290 #define AGE_SRAM_TX_FIFO_ADDR 0x1528 291 292 #define AGE_SRAM_TX_FIFO_LEN 0x152C 293 294 #define AGE_SRAM_TCPH_ADDR 0x1530 295 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 296 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 297 #define SRAM_TCPH_ADDR_SHIFT 0 298 #define SRAM_PATH_ADDR_SHIFT 16 299 300 #define AGE_DMA_BLOCK 0x1534 301 #define DMA_BLOCK_LOAD 0x00000001 302 303 /* 304 * All descriptors and CMB/SMB share the same high address. 305 */ 306 #define AGE_DESC_ADDR_HI 0x1540 307 308 #define AGE_DESC_RD_ADDR_LO 0x1544 309 310 #define AGE_DESC_RRD_ADDR_LO 0x1548 311 312 #define AGE_DESC_TPD_ADDR_LO 0x154C 313 314 #define AGE_DESC_CMB_ADDR_LO 0x1550 315 316 #define AGE_DESC_SMB_ADDR_LO 0x1554 317 318 #define AGE_DESC_RRD_RD_CNT 0x1558 319 #define DESC_RD_CNT_MASK 0x000007FF 320 #define DESC_RRD_CNT_MASK 0x07FF0000 321 #define DESC_RD_CNT_SHIFT 0 322 #define DESC_RRD_CNT_SHIFT 16 323 324 #define AGE_DESC_TPD_CNT 0x155C 325 #define DESC_TPD_CNT_MASK 0x00003FF 326 #define DESC_TPD_CNT_SHIFT 0 327 328 #define AGE_TXQ_CFG 0x1580 329 #define TXQ_CFG_TPD_BURST_MASK 0x0000001F 330 #define TXQ_CFG_ENB 0x00000020 331 #define TXQ_CFG_ENHANCED_MODE 0x00000040 332 #define TXQ_CFG_TPD_FETCH_THRESH_MASK 0x00003F00 333 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 334 #define TXQ_CFG_TPD_BURST_SHIFT 0 335 #define TXQ_CFG_TPD_BURST_DEFAULT 4 336 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT 8 337 #define TXQ_CFG_TPD_FETCH_DEFAULT 16 338 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 339 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 340 341 #define AGE_TX_JUMBO_TPD_TH_IPG 0x1584 342 #define TX_JUMBO_TPD_TH_MASK 0x000007FF 343 #define TX_JUMBO_TPD_IPG_MASK 0x001F0000 344 #define TX_JUMBO_TPD_TH_SHIFT 0 345 #define TX_JUMBO_TPD_IPG_SHIFT 16 346 #define TX_JUMBO_TPD_IPG_DEFAULT 1 347 348 #define AGE_RXQ_CFG 0x15A0 349 #define RXQ_CFG_RD_BURST_MASK 0x000000FF 350 #define RXQ_CFG_RRD_BURST_THRESH_MASK 0x0000FF00 351 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK 0x001F0000 352 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 353 #define RXQ_CFG_ENB 0x80000000 354 #define RXQ_CFG_RD_BURST_SHIFT 0 355 #define RXQ_CFG_RD_BURST_DEFAULT 8 356 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT 8 357 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8 358 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT 16 359 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1 360 361 #define AGE_RXQ_JUMBO_CFG 0x15A4 362 #define RXQ_JUMBO_CFG_SZ_THRESH_MASK 0x000007FF 363 #define RXQ_JUMBO_CFG_LKAH_MASK 0x00007800 364 #define RXQ_JUMBO_CFG_RRD_TIMER_MASK 0xFFFF0000 365 #define RXQ_JUMBO_CFG_SZ_THRESH_SHIFT 0 366 #define RXQ_JUMBO_CFG_LKAH_SHIFT 11 367 #define RXQ_JUMBO_CFG_LKAH_DEFAULT 0x01 368 #define RXQ_JUMBO_CFG_RRD_TIMER_SHIFT 16 369 370 #define AGE_RXQ_FIFO_PAUSE_THRESH 0x15A8 371 #define RXQ_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 372 #define RXQ_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF000 373 #define RXQ_FIFO_PAUSE_THRESH_LO_SHIFT 0 374 #define RXQ_FIFO_PAUSE_THRESH_HI_SHIFT 16 375 376 #define AGE_RXQ_RRD_PAUSE_THRESH 0x15AC 377 #define RXQ_RRD_PAUSE_THRESH_HI_MASK 0x00000FFF 378 #define RXQ_RRD_PAUSE_THRESH_LO_MASK 0x0FFF0000 379 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT 0 380 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT 16 381 382 #define AGE_DMA_CFG 0x15C0 383 #define DMA_CFG_IN_ORDER 0x00000001 384 #define DMA_CFG_ENH_ORDER 0x00000002 385 #define DMA_CFG_OUT_ORDER 0x00000004 386 #define DMA_CFG_RCB_64 0x00000000 387 #define DMA_CFG_RCB_128 0x00000008 388 #define DMA_CFG_RD_BURST_128 0x00000000 389 #define DMA_CFG_RD_BURST_256 0x00000010 390 #define DMA_CFG_RD_BURST_512 0x00000020 391 #define DMA_CFG_RD_BURST_1024 0x00000030 392 #define DMA_CFG_RD_BURST_2048 0x00000040 393 #define DMA_CFG_RD_BURST_4096 0x00000050 394 #define DMA_CFG_WR_BURST_128 0x00000000 395 #define DMA_CFG_WR_BURST_256 0x00000080 396 #define DMA_CFG_WR_BURST_512 0x00000100 397 #define DMA_CFG_WR_BURST_1024 0x00000180 398 #define DMA_CFG_WR_BURST_2048 0x00000200 399 #define DMA_CFG_WR_BURST_4096 0x00000280 400 #define DMA_CFG_RD_ENB 0x00000400 401 #define DMA_CFG_WR_ENB 0x00000800 402 #define DMA_CFG_RD_BURST_MASK 0x07 403 #define DMA_CFG_RD_BURST_SHIFT 4 404 #define DMA_CFG_WR_BURST_MASK 0x07 405 #define DMA_CFG_WR_BURST_SHIFT 7 406 407 #define AGE_CSMB_CTRL 0x15D0 408 #define CSMB_CTRL_CMB_KICK 0x00000001 409 #define CSMB_CTRL_SMB_KICK 0x00000002 410 #define CSMB_CTRL_CMB_ENB 0x00000004 411 #define CSMB_CTRL_SMB_ENB 0x00000008 412 413 /* CMB DMA Write Threshold Register */ 414 #define AGE_CMB_WR_THRESH 0x15D4 415 #define CMB_WR_THRESH_RRD_MASK 0x000007FF 416 #define CMB_WR_THRESH_TPD_MASK 0x07FF0000 417 #define CMB_WR_THRESH_RRD_SHIFT 0 418 #define CMB_WR_THRESH_RRD_DEFAULT 4 419 #define CMB_WR_THRESH_TPD_SHIFT 16 420 #define CMB_WR_THRESH_TPD_DEFAULT 4 421 422 /* RX/TX count-down timer to trigger CMB-write. */ 423 #define AGE_CMB_WR_TIMER 0x15D8 424 #define CMB_WR_TIMER_RX_MASK 0x0000FFFF 425 #define CMB_WR_TIMER_TX_MASK 0xFFFF0000 426 #define CMB_WR_TIMER_RX_SHIFT 0 427 #define CMB_WR_TIMER_TX_SHIFT 16 428 429 /* Number of packet received since last CMB write */ 430 #define AGE_CMB_RX_PKT_CNT 0x15DC 431 432 /* Number of packet transmitted since last CMB write */ 433 #define AGE_CMB_TX_PKT_CNT 0x15E0 434 435 /* SMB auto DMA timer register */ 436 #define AGE_SMB_TIMER 0x15E4 437 438 #define AGE_MBOX 0x15F0 439 #define MBOX_RD_PROD_IDX_MASK 0x000007FF 440 #define MBOX_RRD_CONS_IDX_MASK 0x003FF800 441 #define MBOX_TD_PROD_IDX_MASK 0xFFC00000 442 #define MBOX_RD_PROD_IDX_SHIFT 0 443 #define MBOX_RRD_CONS_IDX_SHIFT 11 444 #define MBOX_TD_PROD_IDX_SHIFT 22 445 446 #define AGE_INTR_STATUS 0x1600 447 #define INTR_SMB 0x00000001 448 #define INTR_MOD_TIMER 0x00000002 449 #define INTR_MANUAL_TIMER 0x00000004 450 #define INTR_RX_FIFO_OFLOW 0x00000008 451 #define INTR_RD_UNDERRUN 0x00000010 452 #define INTR_RRD_OFLOW 0x00000020 453 #define INTR_TX_FIFO_UNDERRUN 0x00000040 454 #define INTR_LINK_CHG 0x00000080 455 #define INTR_HOST_RD_UNDERRUN 0x00000100 456 #define INTR_HOST_RRD_OFLOW 0x00000200 457 #define INTR_DMA_RD_TO_RST 0x00000400 458 #define INTR_DMA_WR_TO_RST 0x00000800 459 #define INTR_GPHY 0x00001000 460 #define INTR_RX_PKT 0x00010000 461 #define INTR_TX_PKT 0x00020000 462 #define INTR_TX_DMA 0x00040000 463 #define INTR_RX_DMA 0x00080000 464 #define INTR_CMB_RX 0x00100000 465 #define INTR_CMB_TX 0x00200000 466 #define INTR_MAC_RX 0x00400000 467 #define INTR_MAC_TX 0x00800000 468 #define INTR_UNDERRUN 0x01000000 469 #define INTR_FRAME_ERROR 0x02000000 470 #define INTR_FRAME_OK 0x04000000 471 #define INTR_CSUM_ERROR 0x08000000 472 #define INTR_PHY_LINK_DOWN 0x10000000 473 #define INTR_DIS_SMB 0x20000000 474 #define INTR_DIS_DMA 0x40000000 475 #define INTR_DIS_INT 0x80000000 476 477 /* Interrupt Mask Register */ 478 #define AGE_INTR_MASK 0x1604 479 480 #define AGE_INTRS \ 481 (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 482 INTR_CMB_TX | INTR_CMB_RX) 483 484 /* Statistics counters collected by the MAC. */ 485 struct smb { 486 /* Rx stats. */ 487 uint32_t rx_frames; 488 uint32_t rx_bcast_frames; 489 uint32_t rx_mcast_frames; 490 uint32_t rx_pause_frames; 491 uint32_t rx_control_frames; 492 uint32_t rx_crcerrs; 493 uint32_t rx_lenerrs; 494 uint32_t rx_bytes; 495 uint32_t rx_runts; 496 uint32_t rx_fragments; 497 uint32_t rx_pkts_64; 498 uint32_t rx_pkts_65_127; 499 uint32_t rx_pkts_128_255; 500 uint32_t rx_pkts_256_511; 501 uint32_t rx_pkts_512_1023; 502 uint32_t rx_pkts_1024_1518; 503 uint32_t rx_pkts_1519_max; 504 uint32_t rx_pkts_truncated; 505 uint32_t rx_fifo_oflows; 506 uint32_t rx_desc_oflows; 507 uint32_t rx_alignerrs; 508 uint32_t rx_bcast_bytes; 509 uint32_t rx_mcast_bytes; 510 uint32_t rx_pkts_filtered; 511 /* Tx stats. */ 512 uint32_t tx_frames; 513 uint32_t tx_bcast_frames; 514 uint32_t tx_mcast_frames; 515 uint32_t tx_pause_frames; 516 uint32_t tx_excess_defer; 517 uint32_t tx_control_frames; 518 uint32_t tx_deferred; 519 uint32_t tx_bytes; 520 uint32_t tx_pkts_64; 521 uint32_t tx_pkts_65_127; 522 uint32_t tx_pkts_128_255; 523 uint32_t tx_pkts_256_511; 524 uint32_t tx_pkts_512_1023; 525 uint32_t tx_pkts_1024_1518; 526 uint32_t tx_pkts_1519_max; 527 uint32_t tx_single_colls; 528 uint32_t tx_multi_colls; 529 uint32_t tx_late_colls; 530 uint32_t tx_excess_colls; 531 uint32_t tx_underrun; 532 uint32_t tx_desc_underrun; 533 uint32_t tx_lenerrs; 534 uint32_t tx_pkts_truncated; 535 uint32_t tx_bcast_bytes; 536 uint32_t tx_mcast_bytes; 537 uint32_t updated; 538 } __packed; 539 540 /* Coalescing message block */ 541 struct cmb { 542 uint32_t intr_status; 543 uint32_t rprod_cons; 544 #define RRD_PROD_MASK 0x0000FFFF 545 #define RD_CONS_MASK 0xFFFF0000 546 #define RRD_PROD_SHIFT 0 547 #define RD_CONS_SHIFT 16 548 uint32_t tpd_cons; 549 #define CMB_UPDATED 0x00000001 550 #define TPD_CONS_MASK 0xFFFF0000 551 #define TPD_CONS_SHIFT 16 552 } __packed; 553 554 /* Rx return descriptor */ 555 struct rx_rdesc { 556 uint32_t index; 557 #define AGE_RRD_NSEGS_MASK 0x000000FF 558 #define AGE_RRD_CONS_MASK 0xFFFF0000 559 #define AGE_RRD_NSEGS_SHIFT 0 560 #define AGE_RRD_CONS_SHIFT 16 561 uint32_t len; 562 #define AGE_RRD_CSUM_MASK 0x0000FFFF 563 #define AGE_RRD_LEN_MASK 0xFFFF0000 564 #define AGE_RRD_CSUM_SHIFT 0 565 #define AGE_RRD_LEN_SHIFT 16 566 uint32_t flags; 567 #define AGE_RRD_ETHERNET 0x00000080 568 #define AGE_RRD_VLAN 0x00000100 569 #define AGE_RRD_ERROR 0x00000200 570 #define AGE_RRD_IPV4 0x00000400 571 #define AGE_RRD_UDP 0x00000800 572 #define AGE_RRD_TCP 0x00001000 573 #define AGE_RRD_BCAST 0x00002000 574 #define AGE_RRD_MCAST 0x00004000 575 #define AGE_RRD_PAUSE 0x00008000 576 #define AGE_RRD_CRC 0x00010000 577 #define AGE_RRD_CODE 0x00020000 578 #define AGE_RRD_DRIBBLE 0x00040000 579 #define AGE_RRD_RUNT 0x00080000 580 #define AGE_RRD_OFLOW 0x00100000 581 #define AGE_RRD_TRUNC 0x00200000 582 #define AGE_RRD_IPCSUM_NOK 0x00400000 583 #define AGE_RRD_TCP_UDPCSUM_NOK 0x00800000 584 #define AGE_RRD_LENGTH_NOK 0x01000000 585 #define AGE_RRD_DES_ADDR_FILTERED 0x02000000 586 uint32_t vtags; 587 #define AGE_RRD_VLAN_MASK 0xFFFF0000 588 #define AGE_RRD_VLAN_SHIFT 16 589 } __packed; 590 591 #define AGE_RX_NSEGS(x) \ 592 (((x) & AGE_RRD_NSEGS_MASK) >> AGE_RRD_NSEGS_SHIFT) 593 #define AGE_RX_CONS(x) \ 594 (((x) & AGE_RRD_CONS_MASK) >> AGE_RRD_CONS_SHIFT) 595 #define AGE_RX_CSUM(x) \ 596 (((x) & AGE_RRD_CSUM_MASK) >> AGE_RRD_CSUM_SHIFT) 597 #define AGE_RX_BYTES(x) \ 598 (((x) & AGE_RRD_LEN_MASK) >> AGE_RRD_LEN_SHIFT) 599 #define AGE_RX_VLAN(x) \ 600 (((x) & AGE_RRD_VLAN_MASK) >> AGE_RRD_VLAN_SHIFT) 601 #define AGE_RX_VLAN_TAG(x) \ 602 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 603 604 /* Rx descriptor. */ 605 struct rx_desc { 606 uint64_t addr; 607 uint32_t len; 608 #define AGE_RD_LEN_MASK 0x0000FFFF 609 #define AGE_CONS_UPD_REQ_MASK 0xFFFF0000 610 #define AGE_RD_LEN_SHIFT 0 611 #define AGE_CONS_UPD_REQ_SHIFT 16 612 } __packed; 613 614 /* Tx descriptor. */ 615 struct tx_desc { 616 uint64_t addr; 617 uint32_t len; 618 #define AGE_TD_VLAN_MASK 0xFFFF0000 619 #define AGE_TD_PKT_INT 0x00008000 620 #define AGE_TD_DMA_INT 0x00004000 621 #define AGE_TD_BUFLEN_MASK 0x00003FFF 622 #define AGE_TD_VLAN_SHIFT 16 623 #define AGE_TX_VLAN_TAG(x) \ 624 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 625 #define AGE_TD_BUFLEN_SHIFT 0 626 #define AGE_TX_BYTES(x) \ 627 (((x) << AGE_TD_BUFLEN_SHIFT) & AGE_TD_BUFLEN_MASK) 628 uint32_t flags; 629 #define AGE_TD_TSO_MSS 0xFFF80000 630 #define AGE_TD_TSO_HDR 0x00040000 631 #define AGE_TD_TSO_TCPHDR_LEN 0x0003C000 632 #define AGE_TD_IPHDR_LEN 0x00003C00 633 #define AGE_TD_LLC_SNAP 0x00000200 634 #define AGE_TD_VLAN_TAGGED 0x00000100 635 #define AGE_TD_UDPCSUM 0x00000080 636 #define AGE_TD_TCPCSUM 0x00000040 637 #define AGE_TD_IPCSUM 0x00000020 638 #define AGE_TD_TSO_IPV4 0x00000010 639 #define AGE_TD_TSO_IPV6 0x00000012 640 #define AGE_TD_CSUM 0x00000008 641 #define AGE_TD_INSERT_VLAN_TAG 0x00000004 642 #define AGE_TD_COALESCE 0x00000002 643 #define AGE_TD_EOP 0x00000001 644 645 #define AGE_TD_CSUM_PLOADOFFSET 0x00FF0000 646 #define AGE_TD_CSUM_XSUMOFFSET 0xFF000000 647 #define AGE_TD_CSUM_XSUMOFFSET_SHIFT 24 648 #define AGE_TD_CSUM_PLOADOFFSET_SHIFT 16 649 #define AGE_TD_TSO_MSS_SHIFT 19 650 #define AGE_TD_TSO_TCPHDR_LEN_SHIFT 14 651 #define AGE_TD_IPHDR_LEN_SHIFT 10 652 } __packed; 653 654 #define AGE_TX_RING_CNT 256 655 #define AGE_RX_RING_CNT 256 656 #define AGE_RR_RING_CNT (AGE_TX_RING_CNT + AGE_RX_RING_CNT) 657 /* The following ring alignments are just guessing. */ 658 #define AGE_TX_RING_ALIGN 16 659 #define AGE_RX_RING_ALIGN 16 660 #define AGE_RR_RING_ALIGN 16 661 #define AGE_CMB_ALIGN 16 662 #define AGE_SMB_ALIGN 16 663 664 #define AGE_TSO_MAXSEGSIZE 4096 665 #define AGE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 666 #define AGE_MAXTXSEGS 32 667 668 #define AGE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 669 #define AGE_ADDR_HI(x) ((uint64_t) (x) >> 32) 670 671 #define AGE_MSI_MESSAGES 1 672 #define AGE_MSIX_MESSAGES 1 673 674 #define AGE_JUMBO_FRAMELEN 10240 675 #define AGE_JUMBO_MTU \ 676 (AGE_JUMBO_FRAMELEN - EVL_ENCAPLEN - \ 677 ETHER_HDR_LEN - ETHER_CRC_LEN) 678 679 #define AGE_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 680 681 #define AGE_PROC_MIN 30 682 #define AGE_PROC_MAX (AGE_RX_RING_CNT - 1) 683 #define AGE_PROC_DEFAULT (AGE_RX_RING_CNT / 2) 684 685 struct age_txdesc { 686 struct mbuf *tx_m; 687 bus_dmamap_t tx_dmamap; 688 struct tx_desc *tx_desc; 689 }; 690 691 struct age_rxdesc { 692 struct mbuf *rx_m; 693 bus_dmamap_t rx_dmamap; 694 struct rx_desc *rx_desc; 695 }; 696 697 struct age_chain_data{ 698 struct age_txdesc age_txdesc[AGE_TX_RING_CNT]; 699 struct age_rxdesc age_rxdesc[AGE_RX_RING_CNT]; 700 bus_dmamap_t age_tx_ring_map; 701 bus_dma_segment_t age_tx_ring_seg; 702 bus_dmamap_t age_rx_ring_map; 703 bus_dma_segment_t age_rx_ring_seg; 704 bus_dmamap_t age_rx_sparemap; 705 bus_dmamap_t age_rr_ring_map; 706 bus_dma_segment_t age_rr_ring_seg; 707 bus_dmamap_t age_cmb_block_map; 708 bus_dma_segment_t age_cmb_block_seg; 709 bus_dmamap_t age_smb_block_map; 710 bus_dma_segment_t age_smb_block_seg; 711 712 int age_tx_prod; 713 int age_tx_cons; 714 int age_tx_cnt; 715 int age_rx_cons; 716 int age_rr_cons; 717 int age_rxlen; 718 719 struct mbuf *age_rxhead; 720 struct mbuf *age_rxtail; 721 struct mbuf *age_rxprev_tail; 722 }; 723 724 struct age_ring_data { 725 struct tx_desc *age_tx_ring; 726 bus_dma_segment_t age_tx_ring_seg; 727 bus_addr_t age_tx_ring_paddr; 728 struct rx_desc *age_rx_ring; 729 bus_dma_segment_t age_rx_ring_seg; 730 bus_addr_t age_rx_ring_paddr; 731 struct rx_rdesc *age_rr_ring; 732 bus_dma_segment_t age_rr_ring_seg; 733 bus_addr_t age_rr_ring_paddr; 734 struct cmb *age_cmb_block; 735 bus_dma_segment_t age_cmb_block_seg; 736 bus_addr_t age_cmb_block_paddr; 737 struct smb *age_smb_block; 738 bus_dma_segment_t age_smb_block_seg; 739 bus_addr_t age_smb_block_paddr; 740 }; 741 742 #define AGE_TX_RING_SZ \ 743 (sizeof(struct tx_desc) * AGE_TX_RING_CNT) 744 #define AGE_RX_RING_SZ \ 745 (sizeof(struct rx_desc) * AGE_RX_RING_CNT) 746 #define AGE_RR_RING_SZ \ 747 (sizeof(struct rx_rdesc) * AGE_RR_RING_CNT) 748 #define AGE_CMB_BLOCK_SZ sizeof(struct cmb) 749 #define AGE_SMB_BLOCK_SZ sizeof(struct smb) 750 751 struct age_stats { 752 /* Rx stats. */ 753 uint64_t rx_frames; 754 uint64_t rx_bcast_frames; 755 uint64_t rx_mcast_frames; 756 uint32_t rx_pause_frames; 757 uint32_t rx_control_frames; 758 uint32_t rx_crcerrs; 759 uint32_t rx_lenerrs; 760 uint64_t rx_bytes; 761 uint32_t rx_runts; 762 uint64_t rx_fragments; 763 uint64_t rx_pkts_64; 764 uint64_t rx_pkts_65_127; 765 uint64_t rx_pkts_128_255; 766 uint64_t rx_pkts_256_511; 767 uint64_t rx_pkts_512_1023; 768 uint64_t rx_pkts_1024_1518; 769 uint64_t rx_pkts_1519_max; 770 uint64_t rx_pkts_truncated; 771 uint32_t rx_fifo_oflows; 772 uint32_t rx_desc_oflows; 773 uint32_t rx_alignerrs; 774 uint64_t rx_bcast_bytes; 775 uint64_t rx_mcast_bytes; 776 uint64_t rx_pkts_filtered; 777 /* Tx stats. */ 778 uint64_t tx_frames; 779 uint64_t tx_bcast_frames; 780 uint64_t tx_mcast_frames; 781 uint32_t tx_pause_frames; 782 uint32_t tx_excess_defer; 783 uint32_t tx_control_frames; 784 uint32_t tx_deferred; 785 uint64_t tx_bytes; 786 uint64_t tx_pkts_64; 787 uint64_t tx_pkts_65_127; 788 uint64_t tx_pkts_128_255; 789 uint64_t tx_pkts_256_511; 790 uint64_t tx_pkts_512_1023; 791 uint64_t tx_pkts_1024_1518; 792 uint64_t tx_pkts_1519_max; 793 uint32_t tx_single_colls; 794 uint32_t tx_multi_colls; 795 uint32_t tx_late_colls; 796 uint32_t tx_excess_colls; 797 uint32_t tx_underrun; 798 uint32_t tx_desc_underrun; 799 uint32_t tx_lenerrs; 800 uint32_t tx_pkts_truncated; 801 uint64_t tx_bcast_bytes; 802 uint64_t tx_mcast_bytes; 803 }; 804 805 /* 806 * Software state per device. 807 */ 808 struct age_softc { 809 device_t sc_dev; 810 struct ethercom sc_ec; 811 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 812 813 bus_space_tag_t sc_mem_bt; 814 bus_space_handle_t sc_mem_bh; 815 bus_size_t sc_mem_size; 816 bus_dma_tag_t sc_dmat; 817 pci_chipset_tag_t sc_pct; 818 pcitag_t sc_pcitag; 819 820 void *sc_irq_handle; 821 822 struct mii_data sc_miibus; 823 int age_rev; 824 int age_chip_rev; 825 int age_phyaddr; 826 827 uint32_t age_dma_rd_burst; 828 uint32_t age_dma_wr_burst; 829 830 uint32_t age_flags; 831 #define AGE_FLAG_PCIE 0x0001 832 #define AGE_FLAG_PCIX 0x0002 833 #define AGE_FLAG_MSI 0x0004 834 #define AGE_FLAG_MSIX 0x0008 835 #define AGE_FLAG_PMCAP 0x0010 836 #define AGE_FLAG_DETACH 0x4000 837 #define AGE_FLAG_LINK 0x8000 838 839 callout_t sc_tick_ch; 840 struct age_stats age_stat; 841 struct age_chain_data age_cdata; 842 struct age_ring_data age_rdata; 843 int age_process_limit; 844 int age_int_mod; 845 int age_max_frame_size; 846 int age_morework; 847 int age_rr_prod; 848 int age_tpd_cons; 849 850 int age_txd_spare; 851 }; 852 853 /* Register access macros. */ 854 #define CSR_WRITE_4(sc, reg, val) \ 855 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 856 #define CSR_WRITE_2(sc, reg, val) \ 857 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 858 #define CSR_READ_2(sc, reg) \ 859 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 860 #define CSR_READ_4(sc, reg) \ 861 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 862 863 864 #define AGE_COMMIT_MBOX(_sc) \ 865 do { \ 866 CSR_WRITE_4(_sc, AGE_MBOX, \ 867 (((_sc)->age_cdata.age_rx_cons << MBOX_RD_PROD_IDX_SHIFT) & \ 868 MBOX_RD_PROD_IDX_MASK) | \ 869 (((_sc)->age_cdata.age_rr_cons << \ 870 MBOX_RRD_CONS_IDX_SHIFT) & MBOX_RRD_CONS_IDX_MASK) | \ 871 (((_sc)->age_cdata.age_tx_prod << MBOX_TD_PROD_IDX_SHIFT) & \ 872 MBOX_TD_PROD_IDX_MASK)); \ 873 } while (0) 874 875 #define AGE_RXCHAIN_RESET(_sc) \ 876 do { \ 877 (_sc)->age_cdata.age_rxhead = NULL; \ 878 (_sc)->age_cdata.age_rxtail = NULL; \ 879 (_sc)->age_cdata.age_rxprev_tail = NULL; \ 880 (_sc)->age_cdata.age_rxlen = 0; \ 881 } while (0) 882 883 #define AGE_TX_TIMEOUT 5 884 #define AGE_RESET_TIMEOUT 100 885 #define AGE_TIMEOUT 1000 886 #define AGE_PHY_TIMEOUT 1000 887 888 #endif /* _IF_AGEREG_H */ 889
Indexes created Mon Sep 29 18:09:42 GMT 2025