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      1 /*	$NetBSD: amdgpu_irq.h,v 1.5 2021/12/19 10:20:17 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2014 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #ifndef __AMDGPU_IRQ_H__
     27 #define __AMDGPU_IRQ_H__
     28 
     29 #include <linux/irqdomain.h>
     30 #include "soc15_ih_clientid.h"
     31 #include "amdgpu_ih.h"
     32 
     33 #define AMDGPU_MAX_IRQ_SRC_ID		0x100
     34 #define AMDGPU_MAX_IRQ_CLIENT_ID	0x100
     35 
     36 #define AMDGPU_IRQ_CLIENTID_LEGACY	0
     37 #define AMDGPU_IRQ_CLIENTID_MAX		SOC15_IH_CLIENTID_MAX
     38 
     39 #define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW	4
     40 
     41 struct amdgpu_device;
     42 
     43 enum amdgpu_interrupt_state {
     44 	AMDGPU_IRQ_STATE_DISABLE,
     45 	AMDGPU_IRQ_STATE_ENABLE,
     46 };
     47 
     48 struct amdgpu_iv_entry {
     49 	unsigned client_id;
     50 	unsigned src_id;
     51 	unsigned ring_id;
     52 	unsigned vmid;
     53 	unsigned vmid_src;
     54 	uint64_t timestamp;
     55 	unsigned timestamp_src;
     56 	unsigned pasid;
     57 	unsigned pasid_src;
     58 	unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
     59 	const uint32_t *iv_entry;
     60 };
     61 
     62 struct amdgpu_irq_src {
     63 	unsigned				num_types;
     64 	atomic_t				*enabled_types;
     65 	const struct amdgpu_irq_src_funcs	*funcs;
     66 	void *data;
     67 };
     68 
     69 struct amdgpu_irq_client {
     70 	struct amdgpu_irq_src **sources;
     71 };
     72 
     73 /* provided by interrupt generating IP blocks */
     74 struct amdgpu_irq_src_funcs {
     75 	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
     76 		   unsigned type, enum amdgpu_interrupt_state state);
     77 
     78 	int (*process)(struct amdgpu_device *adev,
     79 		       struct amdgpu_irq_src *source,
     80 		       struct amdgpu_iv_entry *entry);
     81 };
     82 
     83 struct amdgpu_irq {
     84 	bool				installed;
     85 	spinlock_t			lock;
     86 	/* interrupt sources */
     87 	struct amdgpu_irq_client	client[AMDGPU_IRQ_CLIENTID_MAX];
     88 
     89 	/* status, etc. */
     90 	bool				msi_enabled; /* msi enabled */
     91 
     92 	/* interrupt rings */
     93 	struct amdgpu_ih_ring		ih, ih1, ih2;
     94 	const struct amdgpu_ih_funcs    *ih_funcs;
     95 	struct work_struct		ih1_work, ih2_work;
     96 	struct amdgpu_irq_src		self_irq;
     97 
     98 	/* gen irq stuff */
     99 	struct irq_domain		*domain; /* GPU irq controller domain */
    100 	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
    101 	uint32_t                        srbm_soft_reset;
    102 };
    103 
    104 void amdgpu_irq_disable_all(struct amdgpu_device *adev);
    105 irqreturn_t amdgpu_irq_handler(DRM_IRQ_ARGS);
    106 
    107 int amdgpu_irq_init(struct amdgpu_device *adev);
    108 void amdgpu_irq_fini(struct amdgpu_device *adev);
    109 int amdgpu_irq_add_id(struct amdgpu_device *adev,
    110 		      unsigned client_id, unsigned src_id,
    111 		      struct amdgpu_irq_src *source);
    112 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
    113 			 struct amdgpu_ih_ring *ih);
    114 int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    115 		      unsigned type);
    116 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    117 		   unsigned type);
    118 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    119 		   unsigned type);
    120 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
    121 			unsigned type);
    122 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
    123 
    124 int amdgpu_irq_add_domain(struct amdgpu_device *adev);
    125 void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
    126 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
    127 
    128 #endif
    129