1 /* $NetBSD: aupcmcia.c,v 1.13 2022/09/25 12:41:46 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* #include "opt_pci.h" */ 35 /* #include "pci.h" */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aupcmcia.c,v 1.13 2022/09/25 12:41:46 andvar Exp $"); 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/intr.h> 47 #include <sys/device.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 #include <dev/pcmcia/pcmciachip.h> 52 53 #include <mips/alchemy/include/au_himem_space.h> 54 #include <mips/alchemy/include/aubusvar.h> 55 #include <mips/alchemy/include/aureg.h> 56 #include <mips/alchemy/include/auvar.h> 57 58 #include <mips/alchemy/dev/aupcmciareg.h> 59 #include <mips/alchemy/dev/aupcmciavar.h> 60 61 /* 62 * Borrow PCMCIADEBUG for now. Generally aupcmcia is the only PCMCIA 63 * host on these machines anyway. 64 */ 65 #ifdef PCMCIADEBUG 66 int aupcm_debug = 1; 67 #define DPRINTF(arg) if (aupcm_debug) printf arg 68 #else 69 #define DPRINTF(arg) 70 #endif 71 72 /* 73 * And for information about mappings, etc. use this one. 74 */ 75 #ifdef AUPCMCIANOISY 76 #define NOISY(arg) printf arg 77 #else 78 #define NOISY(arg) 79 #endif 80 81 /* 82 * Note, we use prefix "aupcm" instead of "aupcmcia", even though our 83 * driver is the latter, mostly because my fingers have trouble typing 84 * the former. "aupcm" should be sufficiently unique to avoid 85 * confusion. 86 */ 87 88 static int aupcm_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 89 struct pcmcia_mem_handle *); 90 static void aupcm_mem_free(pcmcia_chipset_handle_t, 91 struct pcmcia_mem_handle *); 92 static int aupcm_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 93 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 94 static void aupcm_mem_unmap(pcmcia_chipset_handle_t, int); 95 96 static int aupcm_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 97 bus_size_t, struct pcmcia_io_handle *); 98 static void aupcm_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 99 static int aupcm_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 100 bus_size_t, struct pcmcia_io_handle *, int *); 101 static void aupcm_io_unmap(pcmcia_chipset_handle_t, int); 102 static void *aupcm_intr_establish(pcmcia_chipset_handle_t, 103 struct pcmcia_function *, int, int (*)(void *), void *); 104 static void aupcm_intr_disestablish(pcmcia_chipset_handle_t, void *); 105 106 static void aupcm_slot_enable(pcmcia_chipset_handle_t); 107 static void aupcm_slot_disable(pcmcia_chipset_handle_t); 108 static void aupcm_slot_settype(pcmcia_chipset_handle_t, int); 109 110 static int aupcm_match(device_t, struct cfdata *, void *); 111 static void aupcm_attach(device_t, device_t, void *); 112 113 static void aupcm_event_thread(void *); 114 static int aupcm_card_intr(void *); 115 static void aupcm_softintr(void *); 116 static int aupcm_print(void *, const char *); 117 118 struct aupcm_slot { 119 struct aupcm_softc *as_softc; 120 int as_slot; 121 int as_status; 122 int as_enabled; 123 int (*as_intr)(void *); 124 int as_card_irq; 125 int as_status_irq; 126 void *as_intrarg; 127 void *as_softint; 128 void *as_hardint; 129 const char *as_name; 130 bus_addr_t as_offset; 131 struct mips_bus_space as_iot; 132 struct mips_bus_space as_attrt; 133 struct mips_bus_space as_memt; 134 void *as_wins[AUPCMCIA_NWINS]; 135 136 device_t as_pcmcia; 137 }; 138 139 /* this structure needs to be exposed... */ 140 struct aupcm_softc { 141 device_t sc_dev; 142 pcmcia_chipset_tag_t sc_pct; 143 144 void (*sc_slot_enable)(int); 145 void (*sc_slot_disable)(int); 146 int (*sc_slot_status)(int); 147 148 paddr_t sc_base; 149 150 int sc_wake; 151 lwp_t *sc_thread; 152 153 int sc_nslots; 154 struct aupcm_slot sc_slots[AUPCMCIA_NSLOTS]; 155 }; 156 157 static struct pcmcia_chip_functions aupcm_functions = { 158 aupcm_mem_alloc, 159 aupcm_mem_free, 160 aupcm_mem_map, 161 aupcm_mem_unmap, 162 163 aupcm_io_alloc, 164 aupcm_io_free, 165 aupcm_io_map, 166 aupcm_io_unmap, 167 168 aupcm_intr_establish, 169 aupcm_intr_disestablish, 170 171 aupcm_slot_enable, 172 aupcm_slot_disable, 173 aupcm_slot_settype, 174 }; 175 176 static struct mips_bus_space aupcm_memt; 177 178 CFATTACH_DECL_NEW(aupcmcia, sizeof (struct aupcm_softc), 179 aupcm_match, aupcm_attach, NULL, NULL); 180 181 int 182 aupcm_match(device_t parent, struct cfdata *cf, void *aux) 183 { 184 struct aubus_attach_args *aa = aux; 185 static int found = 0; 186 187 if (found) 188 return 0; 189 190 if (strcmp(aa->aa_name, "aupcmcia") != 0) 191 return 0; 192 193 found = 1; 194 195 return 1; 196 } 197 198 void 199 aupcm_attach(device_t parent, device_t self, void *aux) 200 { 201 /* struct aubus_attach_args *aa = aux; */ 202 struct aupcm_softc *sc = device_private(self); 203 static int done = 0; 204 int slot; 205 struct aupcmcia_machdep *md; 206 207 sc->sc_dev = self; 208 209 /* initialize bus space */ 210 if (done) { 211 /* there can be only one. */ 212 return; 213 } 214 215 done = 1; 216 /* 217 * PCMCIA memory can live within pretty much the entire 32-bit 218 * space, modulo 64 MB wraps. We don't have to support coexisting 219 * DMA. 220 */ 221 au_himem_space_init(&aupcm_memt, "pcmciamem", 222 PCMCIA_BASE, AUPCMCIA_ATTR_OFFSET, 0xffffffff, 223 AU_HIMEM_SPACE_LITTLE_ENDIAN); 224 225 if ((md = aupcmcia_machdep()) == NULL) { 226 aprint_error(": unable to get machdep structure\n"); 227 return; 228 } 229 230 sc->sc_nslots = md->am_nslots; 231 sc->sc_slot_enable = md->am_slot_enable; 232 sc->sc_slot_disable = md->am_slot_disable; 233 sc->sc_slot_status = md->am_slot_status; 234 235 aprint_normal(": Alchemy PCMCIA, %d slots\n", sc->sc_nslots); 236 aprint_naive("\n"); 237 238 sc->sc_pct = (pcmcia_chipset_tag_t)&aupcm_functions; 239 240 for (slot = 0; slot < sc->sc_nslots; slot++) { 241 struct aupcm_slot *sp; 242 struct pcmciabus_attach_args paa; 243 244 sp = &sc->sc_slots[slot]; 245 sp->as_softc = sc; 246 247 sp->as_slot = slot; 248 sp->as_name = md->am_slot_name(slot); 249 sp->as_offset = md->am_slot_offset(slot); 250 sp->as_card_irq = md->am_slot_irq(slot, AUPCMCIA_IRQ_CARD); 251 sp->as_status_irq = md->am_slot_irq(slot, 252 AUPCMCIA_IRQ_INSERT); 253 254 au_himem_space_init(&sp->as_attrt, "pcmciaattr", 255 PCMCIA_BASE + sp->as_offset + AUPCMCIA_ATTR_OFFSET, 256 0, AUPCMCIA_MAP_SIZE, AU_HIMEM_SPACE_LITTLE_ENDIAN); 257 258 au_himem_space_init(&sp->as_memt, "pcmciamem", 259 PCMCIA_BASE + sp->as_offset + AUPCMCIA_MEM_OFFSET, 260 0, AUPCMCIA_MAP_SIZE, AU_HIMEM_SPACE_LITTLE_ENDIAN); 261 262 au_himem_space_init(&sp->as_iot, "pcmciaio", 263 PCMCIA_BASE + sp->as_offset + AUPCMCIA_IO_OFFSET, 264 0, AUPCMCIA_MAP_SIZE, 265 AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO); 266 267 sp->as_status = 0; 268 269 paa.paa_busname = "pcmcia"; 270 paa.pct = sc->sc_pct; 271 paa.pch = (pcmcia_chipset_handle_t)sp; 272 273 sp->as_pcmcia = config_found(self, &paa, aupcm_print, 274 CFARGS_NONE); 275 276 /* if no pcmcia, make sure slot is powered down */ 277 if (sp->as_pcmcia == NULL) { 278 aupcm_slot_disable(sp); 279 continue; 280 } 281 282 /* this makes sure we probe the slot */ 283 sc->sc_wake |= (1 << slot); 284 } 285 286 /* 287 * XXX: this would be an excellent time time to establish a handler 288 * for the card insertion interrupt, but that's edge triggered, and 289 * au_icu.c won't support it right now. We poll in the event thread 290 * for now. Start by initializing it now. 291 */ 292 if (kthread_create(PRI_NONE, 0, NULL, aupcm_event_thread, sc, 293 &sc->sc_thread, "%s", device_xname(sc->sc_dev)) != 0) 294 panic("%s: unable to create event kthread", 295 device_xname(sc->sc_dev)); 296 } 297 298 int 299 aupcm_print(void *aux, const char *pnp) 300 { 301 struct pcmciabus_attach_args *paa = aux; 302 struct aupcm_slot *sp = paa->pch; 303 304 printf(" socket %d irq %d, %s", sp->as_slot, sp->as_card_irq, 305 sp->as_name); 306 307 return (UNCONF); 308 } 309 310 void * 311 aupcm_intr_establish(pcmcia_chipset_handle_t pch, 312 struct pcmcia_function *pf, int level, int (*handler)(void *), void *arg) 313 { 314 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 315 int s; 316 317 /* 318 * Hmm. perhaps this intr should be a list. well, PCMCIA 319 * devices generally only have one interrupt, and so should 320 * generally have only one handler. So we leave it for now. 321 * (Other PCMCIA bus drivers do it this way.) 322 */ 323 sp->as_intr = handler; 324 sp->as_intrarg = arg; 325 sp->as_softint = softint_establish(IPL_SOFTNET, aupcm_softintr, sp); 326 327 /* set up hard interrupt handler for the card IRQs */ 328 s = splhigh(); 329 sp->as_hardint = au_intr_establish(sp->as_card_irq, 0, 330 IPL_TTY, IST_LEVEL_LOW, aupcm_card_intr, sp); 331 /* if card is not powered up, then leave the IRQ masked */ 332 if (!sp->as_enabled) { 333 au_intr_disable(sp->as_card_irq); 334 } 335 splx(s); 336 337 return (sp->as_softint); 338 } 339 340 void 341 aupcm_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 342 { 343 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 344 345 KASSERT(sp->as_softint == ih); 346 /* KASSERT(sp->as_hardint); */ 347 /* set up hard interrupt handler for the card IRQs */ 348 349 au_intr_disestablish(sp->as_hardint); 350 sp->as_hardint = 0; 351 352 softint_disestablish(ih); 353 sp->as_softint = 0; 354 sp->as_intr = NULL; 355 sp->as_intrarg = NULL; 356 } 357 358 /* 359 * FYI: Hot detach of PCMCIA is supposedly safe because H/W doesn't 360 * fault on accesses to missing hardware. 361 */ 362 void 363 aupcm_event_thread(void *arg) 364 { 365 struct aupcm_softc *sc = arg; 366 struct aupcm_slot *sp; 367 int s, i, attach, detach; 368 369 for (;;) { 370 s = splhigh(); 371 if (sc->sc_wake == 0) { 372 splx(s); 373 /* 374 * XXX: Currently, the au_icu.c lacks support 375 * for edge-triggered interrupts. So we 376 * cannot really use the status change 377 * interrupts. For now we poll (once per sec). 378 * FYI, Linux does it this way, and they *do* 379 * have support for edge triggered interrupts. 380 * Go figure. 381 */ 382 tsleep(&sc->sc_wake, PWAIT, "aupcm_event", hz); 383 s = splhigh(); 384 } 385 sc->sc_wake = 0; 386 387 attach = detach = 0; 388 for (i = 0; i < sc->sc_nslots; i++) { 389 sp = &sc->sc_slots[i]; 390 391 if (sc->sc_slot_status(sp->as_slot) != 0) { 392 if (!sp->as_status) { 393 DPRINTF(("%s: card %d insertion\n", 394 device_xname(sc->sc_dev), i)); 395 attach |= (1 << i); 396 sp->as_status = 1; 397 } 398 } else { 399 if (sp->as_status) { 400 DPRINTF(("%s: card %d removal\n", 401 device_xname(sc->sc_dev), i)); 402 detach |= (1 << i); 403 sp->as_status = 0; 404 } 405 } 406 } 407 splx(s); 408 409 for (i = 0; i < sc->sc_nslots; i++) { 410 sp = &sc->sc_slots[i]; 411 412 if (detach & (1 << i)) { 413 aupcm_slot_disable(sp); 414 pcmcia_card_detach(sp->as_pcmcia, DETACH_FORCE); 415 } else if (attach & (1 << i)) { 416 /* 417 * until the function is enabled, don't 418 * honor interrupts 419 */ 420 sp->as_enabled = 0; 421 au_intr_disable(sp->as_card_irq); 422 pcmcia_card_attach(sp->as_pcmcia); 423 } 424 } 425 } 426 } 427 428 #if 0 429 void 430 aupcm_status_intr(void *arg) 431 { 432 int s; 433 struct aupcm_softc *sc = arg; 434 435 s = splhigh(); 436 437 /* kick the status thread so it does its bit */ 438 sc->sc_wake = 1; 439 wakeup(&sc->sc_wake); 440 441 splx(s); 442 } 443 #endif 444 445 int 446 aupcm_card_intr(void *arg) 447 { 448 struct aupcm_slot *sp = arg; 449 450 /* disable the hard interrupt for now */ 451 au_intr_disable(sp->as_card_irq); 452 453 if (sp->as_intr != NULL) { 454 softint_schedule(sp->as_softint); 455 } 456 457 return 1; 458 } 459 460 void 461 aupcm_softintr(void *arg) 462 { 463 struct aupcm_slot *sp = arg; 464 int s; 465 466 sp->as_intr(sp->as_intrarg); 467 468 s = splhigh(); 469 470 if (sp->as_intr && sp->as_enabled) { 471 au_intr_enable(sp->as_card_irq); 472 } 473 474 splx(s); 475 } 476 477 void 478 aupcm_slot_enable(pcmcia_chipset_handle_t pch) 479 { 480 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 481 int s; 482 483 /* no interrupts while we reset the card, please */ 484 if (sp->as_intr) 485 au_intr_disable(sp->as_card_irq); 486 487 /* 488 * XXX: should probably lock to make sure slot_disable and 489 * enable not called together. However, i believe that the 490 * event thread basically serializes them anyway. 491 */ 492 493 sp->as_softc->sc_slot_enable(sp->as_slot); 494 /* card is powered up now, honor device interrupts */ 495 496 s = splhigh(); 497 sp->as_enabled = 1; 498 if (sp->as_intr) 499 au_intr_enable(sp->as_card_irq); 500 splx(s); 501 } 502 503 void 504 aupcm_slot_disable(pcmcia_chipset_handle_t pch) 505 { 506 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 507 int s; 508 509 s = splhigh(); 510 au_intr_disable(sp->as_card_irq); 511 sp->as_enabled = 0; 512 splx(s); 513 514 sp->as_softc->sc_slot_disable(sp->as_slot); 515 } 516 517 void 518 aupcm_slot_settype(pcmcia_chipset_handle_t pch, int type) 519 { 520 /* we do nothing now : type == PCMCIA_IFTYPE_IO */ 521 } 522 523 int 524 aupcm_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 525 struct pcmcia_mem_handle *pcmh) 526 { 527 pcmh->memt = NULL; 528 pcmh->size = pcmh->realsize = size; 529 pcmh->addr = 0; 530 pcmh->mhandle = 0; 531 532 return 0; 533 } 534 535 void 536 aupcm_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmh) 537 { 538 /* nothing to do */ 539 } 540 541 int 542 aupcm_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t addr, 543 bus_size_t size, struct pcmcia_mem_handle *pcmh, bus_size_t *offsetp, 544 int *windowp) 545 { 546 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 547 int win, err; 548 int s; 549 550 s = splhigh(); 551 for (win = 0; win < AUPCMCIA_NWINS; win++) { 552 if (sp->as_wins[win] == NULL) { 553 sp->as_wins[win] = pcmh; 554 break; 555 } 556 } 557 splx(s); 558 559 if (win >= AUPCMCIA_NWINS) { 560 return ENOMEM; 561 } 562 563 if (kind & PCMCIA_MEM_ATTR) { 564 pcmh->memt = &sp->as_attrt; 565 NOISY(("mapping ATTR addr %x size %x\n", (uint32_t)addr, 566 (uint32_t)size)); 567 } else { 568 pcmh->memt = &sp->as_memt; 569 NOISY(("mapping MEMORY addr %x size %x\n", (uint32_t)addr, 570 (uint32_t)size)); 571 } 572 573 if ((size + addr) > (64 * 1024 * 1024)) 574 return EINVAL; 575 576 pcmh->size = size; 577 578 err = bus_space_map(pcmh->memt, addr, size, 0, &pcmh->memh); 579 if (err != 0) { 580 sp->as_wins[win] = NULL; 581 return err; 582 } 583 *offsetp = 0; 584 *windowp = win; 585 586 return 0; 587 } 588 589 void 590 aupcm_mem_unmap(pcmcia_chipset_handle_t pch, int win) 591 { 592 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 593 struct pcmcia_mem_handle *pcmh; 594 595 pcmh = (struct pcmcia_mem_handle *)sp->as_wins[win]; 596 sp->as_wins[win] = NULL; 597 598 NOISY(("memory umap virtual %x\n", (uint32_t)pcmh->memh)); 599 bus_space_unmap(pcmh->memt, pcmh->memh, pcmh->size); 600 pcmh->memt = NULL; 601 } 602 603 int 604 aupcm_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 605 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pih) 606 { 607 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 608 bus_space_handle_t bush; 609 int err; 610 611 pih->iot = &sp->as_iot; 612 pih->size = size; 613 pih->flags = 0; 614 615 /* 616 * start from the initial offset - this gets us a slot 617 * specific address, while still leaving the addresses more or 618 * less zero-based which is required for x86-style device 619 * drivers. 620 */ 621 err = bus_space_alloc(pih->iot, start, 0x100000, 622 size, align, 0, 0, &pih->addr, &bush); 623 NOISY(("start = %x, addr = %x, size = %x, bush = %x\n", 624 (uint32_t)start, (uint32_t)pih->addr, (uint32_t)size, 625 (uint32_t)bush)); 626 627 /* and we convert it back */ 628 if (err == 0) { 629 pih->ihandle = (void *)bush; 630 } 631 632 return (err); 633 } 634 635 void 636 aupcm_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pih) 637 { 638 bus_space_free(pih->iot, (bus_space_handle_t)pih->ihandle, 639 pih->size); 640 } 641 642 int 643 aupcm_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 644 bus_size_t size, struct pcmcia_io_handle *pih, int *windowp) 645 { 646 int err; 647 648 err = bus_space_subregion(pih->iot, (bus_space_handle_t)pih->ihandle, 649 offset, size, &pih->ioh); 650 NOISY(("io map offset = %x, size = %x, ih = %x, hdl=%x\n", 651 (uint32_t)offset, (uint32_t)size, 652 (uint32_t)pih->ihandle, (uint32_t)pih->ioh)); 653 654 return err; 655 } 656 657 void 658 aupcm_io_unmap(pcmcia_chipset_handle_t pch, int win) 659 { 660 /* We mustn't unmap/free subregion bus space! */ 661 NOISY(("io unmap\n")); 662 } 663
Indexes created Mon Sep 29 18:09:42 GMT 2025