| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv730_dpm.c | 101 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv730_populate_sclk_value
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
105 cg_spll_spread_spectrum |= CLK_S(clk_s);
177 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv730_populate_mclk_value
178 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
181 mpll_ss |= CLK_S(clk_s);
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| radeon_rv740_dpm.c | 169 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv740_populate_sclk_value
170 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
173 cg_spll_spread_spectrum |= CLK_S(clk_s);
258 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); local in function:rv740_populate_mclk_value
260 (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000);
266 mpll_ss2 |= CLKS(clk_s);
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| radeon_cypress_dpm.c | 567 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); local in function:cypress_populate_mclk_value
569 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
575 mpll_ss2 |= CLKS(clk_s);
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| radeon_rv6xx_dpm.c | 320 u32 index, u32 clk_s)
323 CLKS(clk_s), ~CLKS_MASK);
345 u32 clk_s)
347 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK);
560 u32 vco_freq, clk_v, clk_s; local in function:rv6xx_program_engine_spread_spectrum
577 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
581 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
663 u32 vco_freq = 0, clk_v, clk_s; local in function:rv6xx_program_mclk_spread_spectrum_parameters
695 clk_s = rv6xx_calculate_spread_spectrum_clk_s(ss.rate,
699 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
[all...] |
| radeon_rv770_dpm.c | 548 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:rv770_populate_sclk_value
549 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
552 cg_spll_spread_spectrum |= CLKS(clk_s);
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| radeon_ni_dpm.c | 2050 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:ni_calculate_sclk_params
2051 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2054 cg_spll_spread_spectrum |= CLK_S(clk_s);
2102 u32 clk_s; local in function:ni_init_smc_spll_table
2122 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2132 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2135 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2149 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2248 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate) local in function:ni_populate_mclk_value
[all...] |
| radeon_ci_dpm.c | 3199 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:ci_calculate_sclk_params
3200 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3203 cg_spll_spread_spectrum |= CLK_S(clk_s);
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| radeon_si_dpm.c | 2858 u32 clk_s, clk_v; local in function:si_init_smc_spll_table
2878 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2889 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2902 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:si_calculate_sclk_params
4833 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4836 cg_spll_spread_spectrum |= CLK_S(clk_s);
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| amdgpu_ci_smumgr.c | 350 uint32_t clk_s = ref_clock * 5 / local in function:ci_calculate_sclk_params
353 fbdiv / (clk_s * 10000);
356 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
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| amdgpu_fiji_smumgr.c | 918 uint32_t clk_s = ref_clock * 5 / local in function:fiji_calculate_sclk_params
922 fbdiv / (clk_s * 10000);
925 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 2958 u32 clk_s, clk_v; local in function:si_init_smc_spll_table
2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
5296 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); local in function:si_calculate_sclk_params
5297 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5300 cg_spll_spread_spectrum |= CLK_S(clk_s);
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