1 /* $NetBSD: radeon_si_dpm.c,v 1.9 2023/09/30 10:46:45 mrg Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: radeon_si_dpm.c,v 1.9 2023/09/30 10:46:45 mrg Exp $"); 28 29 #include <linux/math64.h> 30 #include <linux/pci.h> 31 #include <linux/seq_file.h> 32 33 #include "atom.h" 34 #include "r600_dpm.h" 35 #include "radeon.h" 36 #include "radeon_asic.h" 37 #include "si_dpm.h" 38 #include "sid.h" 39 40 #define MC_CG_ARB_FREQ_F0 0x0a 41 #define MC_CG_ARB_FREQ_F1 0x0b 42 #define MC_CG_ARB_FREQ_F2 0x0c 43 #define MC_CG_ARB_FREQ_F3 0x0d 44 45 #define SMC_RAM_END 0x20000 46 47 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 48 49 static const struct si_cac_config_reg cac_weights_tahiti[] = 50 { 51 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 52 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 54 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 58 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 59 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 60 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 61 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 63 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 64 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 65 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 66 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 67 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 69 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 71 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 72 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 73 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 82 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 86 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 89 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 91 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 106 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 107 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 108 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 109 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 110 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 111 { 0xFFFFFFFF } 112 }; 113 114 static const struct si_cac_config_reg lcac_tahiti[] = 115 { 116 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 119 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 121 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 123 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 135 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 137 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 139 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 159 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 161 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 163 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 171 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 173 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 175 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 183 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 185 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 187 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 189 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 197 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 198 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 199 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 200 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 201 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 202 { 0xFFFFFFFF } 203 204 }; 205 206 static const struct si_cac_config_reg cac_override_tahiti[] = 207 { 208 { 0xFFFFFFFF } 209 }; 210 211 static const struct si_powertune_data powertune_data_tahiti = 212 { 213 ((1 << 16) | 27027), 214 6, 215 0, 216 4, 217 95, 218 { 219 0UL, 220 0UL, 221 4521550UL, 222 309631529UL, 223 -1270850L, 224 4513710L, 225 40 226 }, 227 595000000UL, 228 12, 229 { 230 0, 231 0, 232 0, 233 0, 234 0, 235 0, 236 0, 237 0 238 }, 239 true 240 }; 241 242 static const struct si_dte_data dte_data_tahiti = 243 { 244 { 1159409, 0, 0, 0, 0 }, 245 { 777, 0, 0, 0, 0 }, 246 2, 247 54000, 248 127000, 249 25, 250 2, 251 10, 252 13, 253 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 254 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 255 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 256 85, 257 false 258 }; 259 260 static const struct si_dte_data dte_data_tahiti_le = 261 { 262 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 263 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 264 0x5, 265 0xAFC8, 266 0x64, 267 0x32, 268 1, 269 0, 270 0x10, 271 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 272 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 273 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 274 85, 275 true 276 }; 277 278 static const struct si_dte_data dte_data_tahiti_pro = 279 { 280 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 281 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 282 5, 283 45000, 284 100, 285 0xA, 286 1, 287 0, 288 0x10, 289 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 290 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 291 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 292 90, 293 true 294 }; 295 296 static const struct si_dte_data dte_data_new_zealand = 297 { 298 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 299 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 300 0x5, 301 0xAFC8, 302 0x69, 303 0x32, 304 1, 305 0, 306 0x10, 307 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 308 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 309 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 310 85, 311 true 312 }; 313 314 static const struct si_dte_data dte_data_aruba_pro = 315 { 316 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 317 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 318 5, 319 45000, 320 100, 321 0xA, 322 1, 323 0, 324 0x10, 325 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 326 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 327 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 328 90, 329 true 330 }; 331 332 static const struct si_dte_data dte_data_malta = 333 { 334 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 335 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 336 5, 337 45000, 338 100, 339 0xA, 340 1, 341 0, 342 0x10, 343 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 344 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 345 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 346 90, 347 true 348 }; 349 350 struct si_cac_config_reg cac_weights_pitcairn[] = 351 { 352 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 353 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 356 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 357 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 358 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 359 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 360 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 362 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 363 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 364 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 365 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 366 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 367 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 368 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 370 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 371 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 372 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 373 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 374 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 375 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 378 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 379 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 383 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 385 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 387 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 388 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 389 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 391 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 406 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 407 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 408 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 409 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 410 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 411 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 412 { 0xFFFFFFFF } 413 }; 414 415 static const struct si_cac_config_reg lcac_pitcairn[] = 416 { 417 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 418 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 420 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 422 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 424 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 426 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 428 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 430 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 432 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 434 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 436 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 438 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 440 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 442 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 444 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 446 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 448 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 450 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 452 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 454 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 456 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 458 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 460 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 462 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 472 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 474 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 476 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 486 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 488 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 490 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 498 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 499 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 500 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 501 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 502 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 503 { 0xFFFFFFFF } 504 }; 505 506 static const struct si_cac_config_reg cac_override_pitcairn[] = 507 { 508 { 0xFFFFFFFF } 509 }; 510 511 static const struct si_powertune_data powertune_data_pitcairn = 512 { 513 ((1 << 16) | 27027), 514 5, 515 0, 516 6, 517 100, 518 { 519 51600000UL, 520 1800000UL, 521 7194395UL, 522 309631529UL, 523 -1270850L, 524 4513710L, 525 100 526 }, 527 117830498UL, 528 12, 529 { 530 0, 531 0, 532 0, 533 0, 534 0, 535 0, 536 0, 537 0 538 }, 539 true 540 }; 541 542 static const struct si_dte_data dte_data_pitcairn = 543 { 544 { 0, 0, 0, 0, 0 }, 545 { 0, 0, 0, 0, 0 }, 546 0, 547 0, 548 0, 549 0, 550 0, 551 0, 552 0, 553 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 554 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 555 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 556 0, 557 false 558 }; 559 560 static const struct si_dte_data dte_data_curacao_xt = 561 { 562 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 563 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 564 5, 565 45000, 566 100, 567 0xA, 568 1, 569 0, 570 0x10, 571 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 572 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 573 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 574 90, 575 true 576 }; 577 578 static const struct si_dte_data dte_data_curacao_pro = 579 { 580 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 581 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 582 5, 583 45000, 584 100, 585 0xA, 586 1, 587 0, 588 0x10, 589 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 590 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 591 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 592 90, 593 true 594 }; 595 596 static const struct si_dte_data dte_data_neptune_xt = 597 { 598 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 599 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 600 5, 601 45000, 602 100, 603 0xA, 604 1, 605 0, 606 0x10, 607 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 608 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 609 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 610 90, 611 true 612 }; 613 614 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 615 { 616 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 617 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 618 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 619 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 620 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 621 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 622 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 623 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 624 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 625 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 626 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 627 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 628 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 629 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 630 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 631 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 632 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 633 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 634 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 635 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 636 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 637 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 638 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 639 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 640 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 641 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 642 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 643 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 644 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 645 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 646 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 647 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 648 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 649 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 650 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 651 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 652 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 654 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 656 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 657 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 670 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 671 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 672 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 673 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 674 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 675 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 676 { 0xFFFFFFFF } 677 }; 678 679 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 680 { 681 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 682 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 683 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 684 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 685 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 686 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 687 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 688 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 689 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 690 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 691 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 692 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 693 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 694 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 695 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 696 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 697 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 698 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 699 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 700 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 701 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 702 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 703 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 704 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 705 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 706 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 707 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 708 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 709 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 710 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 711 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 712 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 713 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 714 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 715 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 716 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 717 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 719 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 721 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 722 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 735 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 736 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 737 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 738 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 739 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 740 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 741 { 0xFFFFFFFF } 742 }; 743 744 static const struct si_cac_config_reg cac_weights_heathrow[] = 745 { 746 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 747 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 748 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 749 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 750 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 751 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 752 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 753 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 754 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 755 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 756 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 757 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 758 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 760 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 761 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 762 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 763 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 764 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 765 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 766 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 767 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 768 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 769 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 770 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 771 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 772 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 773 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 775 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 776 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 777 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 778 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 779 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 780 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 781 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 782 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 784 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 786 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 787 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 800 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 801 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 802 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 803 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 804 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 805 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 806 { 0xFFFFFFFF } 807 }; 808 809 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 810 { 811 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 812 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 813 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 814 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 815 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 816 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 817 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 818 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 819 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 820 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 821 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 822 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 823 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 825 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 826 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 827 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 828 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 829 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 830 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 831 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 832 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 833 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 834 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 835 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 836 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 837 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 838 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 840 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 841 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 842 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 843 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 844 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 845 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 846 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 847 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 849 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 851 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 852 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 865 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 866 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 867 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 868 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 869 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 870 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 871 { 0xFFFFFFFF } 872 }; 873 874 static const struct si_cac_config_reg cac_weights_cape_verde[] = 875 { 876 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 877 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 878 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 879 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 880 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 881 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 882 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 883 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 884 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 885 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 886 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 887 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 888 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 890 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 891 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 892 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 893 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 894 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 895 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 896 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 897 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 898 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 899 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 900 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 901 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 902 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 903 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 905 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 906 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 907 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 908 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 909 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 910 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 911 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 912 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 914 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 916 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 917 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 930 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 931 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 932 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 933 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 934 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 935 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 936 { 0xFFFFFFFF } 937 }; 938 939 static const struct si_cac_config_reg lcac_cape_verde[] = 940 { 941 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 942 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 944 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 946 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 948 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 950 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 954 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 956 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 958 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 960 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 978 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 982 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 986 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 991 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 992 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 993 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 994 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 995 { 0xFFFFFFFF } 996 }; 997 998 static const struct si_cac_config_reg cac_override_cape_verde[] = 999 { 1000 { 0xFFFFFFFF } 1001 }; 1002 1003 static const struct si_powertune_data powertune_data_cape_verde = 1004 { 1005 ((1 << 16) | 0x6993), 1006 5, 1007 0, 1008 7, 1009 105, 1010 { 1011 0UL, 1012 0UL, 1013 7194395UL, 1014 309631529UL, 1015 -1270850L, 1016 4513710L, 1017 100 1018 }, 1019 117830498UL, 1020 12, 1021 { 1022 0, 1023 0, 1024 0, 1025 0, 1026 0, 1027 0, 1028 0, 1029 0 1030 }, 1031 true 1032 }; 1033 1034 static const struct si_dte_data dte_data_cape_verde = 1035 { 1036 { 0, 0, 0, 0, 0 }, 1037 { 0, 0, 0, 0, 0 }, 1038 0, 1039 0, 1040 0, 1041 0, 1042 0, 1043 0, 1044 0, 1045 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1046 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1047 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1048 0, 1049 false 1050 }; 1051 1052 static const struct si_dte_data dte_data_venus_xtx = 1053 { 1054 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1055 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1056 5, 1057 55000, 1058 0x69, 1059 0xA, 1060 1, 1061 0, 1062 0x3, 1063 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1064 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1065 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1066 90, 1067 true 1068 }; 1069 1070 static const struct si_dte_data dte_data_venus_xt = 1071 { 1072 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1073 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1074 5, 1075 55000, 1076 0x69, 1077 0xA, 1078 1, 1079 0, 1080 0x3, 1081 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1082 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1083 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1084 90, 1085 true 1086 }; 1087 1088 static const struct si_dte_data dte_data_venus_pro = 1089 { 1090 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1091 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1092 5, 1093 55000, 1094 0x69, 1095 0xA, 1096 1, 1097 0, 1098 0x3, 1099 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1100 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1101 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1102 90, 1103 true 1104 }; 1105 1106 struct si_cac_config_reg cac_weights_oland[] = 1107 { 1108 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1123 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1124 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1125 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1126 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1130 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1131 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1132 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1133 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1134 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1135 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1164 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1165 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1166 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1168 { 0xFFFFFFFF } 1169 }; 1170 1171 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1172 { 1173 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1188 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1189 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1190 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1191 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1195 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1196 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1197 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1198 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1199 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1200 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xFFFFFFFF } 1234 }; 1235 1236 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1237 { 1238 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1260 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1261 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1262 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1263 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1264 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1265 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xFFFFFFFF } 1299 }; 1300 1301 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1302 { 1303 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1326 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1327 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1328 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1329 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1330 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xFFFFFFFF } 1364 }; 1365 1366 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1367 { 1368 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1391 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1392 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1393 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1394 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1395 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1424 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1425 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1426 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xFFFFFFFF } 1429 }; 1430 1431 static const struct si_cac_config_reg lcac_oland[] = 1432 { 1433 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0xFFFFFFFF } 1476 }; 1477 1478 static const struct si_cac_config_reg lcac_mars_pro[] = 1479 { 1480 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1522 { 0xFFFFFFFF } 1523 }; 1524 1525 static const struct si_cac_config_reg cac_override_oland[] = 1526 { 1527 { 0xFFFFFFFF } 1528 }; 1529 1530 static const struct si_powertune_data powertune_data_oland = 1531 { 1532 ((1 << 16) | 0x6993), 1533 5, 1534 0, 1535 7, 1536 105, 1537 { 1538 0UL, 1539 0UL, 1540 7194395UL, 1541 309631529UL, 1542 -1270850L, 1543 4513710L, 1544 100 1545 }, 1546 117830498UL, 1547 12, 1548 { 1549 0, 1550 0, 1551 0, 1552 0, 1553 0, 1554 0, 1555 0, 1556 0 1557 }, 1558 true 1559 }; 1560 1561 static const struct si_powertune_data powertune_data_mars_pro = 1562 { 1563 ((1 << 16) | 0x6993), 1564 5, 1565 0, 1566 7, 1567 105, 1568 { 1569 0UL, 1570 0UL, 1571 7194395UL, 1572 309631529UL, 1573 -1270850L, 1574 4513710L, 1575 100 1576 }, 1577 117830498UL, 1578 12, 1579 { 1580 0, 1581 0, 1582 0, 1583 0, 1584 0, 1585 0, 1586 0, 1587 0 1588 }, 1589 true 1590 }; 1591 1592 static const struct si_dte_data dte_data_oland = 1593 { 1594 { 0, 0, 0, 0, 0 }, 1595 { 0, 0, 0, 0, 0 }, 1596 0, 1597 0, 1598 0, 1599 0, 1600 0, 1601 0, 1602 0, 1603 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1604 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1605 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1606 0, 1607 false 1608 }; 1609 1610 static const struct si_dte_data dte_data_mars_pro = 1611 { 1612 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1613 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1614 5, 1615 55000, 1616 105, 1617 0xA, 1618 1, 1619 0, 1620 0x10, 1621 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1622 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1623 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1624 90, 1625 true 1626 }; 1627 1628 static const struct si_dte_data dte_data_sun_xt = 1629 { 1630 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1631 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1632 5, 1633 55000, 1634 105, 1635 0xA, 1636 1, 1637 0, 1638 0x10, 1639 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1640 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1641 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1642 90, 1643 true 1644 }; 1645 1646 1647 static const struct si_cac_config_reg cac_weights_hainan[] = 1648 { 1649 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1664 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1665 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1666 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1667 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1671 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1672 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1673 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1675 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1676 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1703 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1704 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1705 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1706 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1707 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1708 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1709 { 0xFFFFFFFF } 1710 }; 1711 1712 static const struct si_powertune_data powertune_data_hainan = 1713 { 1714 ((1 << 16) | 0x6993), 1715 5, 1716 0, 1717 9, 1718 105, 1719 { 1720 0UL, 1721 0UL, 1722 7194395UL, 1723 309631529UL, 1724 -1270850L, 1725 4513710L, 1726 100 1727 }, 1728 117830498UL, 1729 12, 1730 { 1731 0, 1732 0, 1733 0, 1734 0, 1735 0, 1736 0, 1737 0, 1738 0 1739 }, 1740 true 1741 }; 1742 1743 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1744 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1745 struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1746 struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1747 1748 extern int si_mc_load_microcode(struct radeon_device *rdev); 1749 extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1750 1751 static int si_populate_voltage_value(struct radeon_device *rdev, 1752 const struct atom_voltage_table *table, 1753 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1754 static int si_get_std_voltage_value(struct radeon_device *rdev, 1755 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1756 u16 *std_voltage); 1757 static int si_write_smc_soft_register(struct radeon_device *rdev, 1758 u16 reg_offset, u32 value); 1759 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1760 struct rv7xx_pl *pl, 1761 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1762 static int si_calculate_sclk_params(struct radeon_device *rdev, 1763 u32 engine_clock, 1764 SISLANDS_SMC_SCLK_VALUE *sclk); 1765 1766 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1767 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1768 1769 static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1770 { 1771 struct si_power_info *pi = rdev->pm.dpm.priv; 1772 1773 return pi; 1774 } 1775 1776 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1777 u16 v, s32 t, u32 ileakage, u32 *leakage) 1778 { 1779 s64 kt, kv, leakage_w, i_leakage, vddc; 1780 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1781 s64 tmp; 1782 1783 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1784 vddc = div64_s64(drm_int2fixp(v), 1000); 1785 temperature = div64_s64(drm_int2fixp(t), 1000); 1786 1787 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1788 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1789 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1790 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1791 t_ref = drm_int2fixp(coeff->t_ref); 1792 1793 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1794 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1795 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1796 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1797 1798 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1799 1800 *leakage = drm_fixp2int(leakage_w * 1000); 1801 } 1802 1803 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1804 const struct ni_leakage_coeffients *coeff, 1805 u16 v, 1806 s32 t, 1807 u32 i_leakage, 1808 u32 *leakage) 1809 { 1810 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1811 } 1812 1813 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1814 const u32 fixed_kt, u16 v, 1815 u32 ileakage, u32 *leakage) 1816 { 1817 s64 kt, kv, leakage_w, i_leakage, vddc; 1818 1819 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1820 vddc = div64_s64(drm_int2fixp(v), 1000); 1821 1822 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1823 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1824 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1825 1826 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1827 1828 *leakage = drm_fixp2int(leakage_w * 1000); 1829 } 1830 1831 static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1832 const struct ni_leakage_coeffients *coeff, 1833 const u32 fixed_kt, 1834 u16 v, 1835 u32 i_leakage, 1836 u32 *leakage) 1837 { 1838 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1839 } 1840 1841 1842 static void si_update_dte_from_pl2(struct radeon_device *rdev, 1843 struct si_dte_data *dte_data) 1844 { 1845 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1846 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1847 u32 k = dte_data->k; 1848 u32 t_max = dte_data->max_t; 1849 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1850 u32 t_0 = dte_data->t0; 1851 u32 i; 1852 1853 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1854 dte_data->tdep_count = 3; 1855 1856 for (i = 0; i < k; i++) { 1857 dte_data->r[i] = 1858 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1859 (p_limit2 * (u32)100); 1860 } 1861 1862 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1863 1864 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1865 dte_data->tdep_r[i] = dte_data->r[4]; 1866 } 1867 } else { 1868 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1869 } 1870 } 1871 1872 static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1873 { 1874 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1875 struct si_power_info *si_pi = si_get_pi(rdev); 1876 bool update_dte_from_pl2 = false; 1877 1878 if (rdev->family == CHIP_TAHITI) { 1879 si_pi->cac_weights = cac_weights_tahiti; 1880 si_pi->lcac_config = lcac_tahiti; 1881 si_pi->cac_override = cac_override_tahiti; 1882 si_pi->powertune_data = &powertune_data_tahiti; 1883 si_pi->dte_data = dte_data_tahiti; 1884 1885 switch (rdev->pdev->device) { 1886 case 0x6798: 1887 si_pi->dte_data.enable_dte_by_default = true; 1888 break; 1889 case 0x6799: 1890 si_pi->dte_data = dte_data_new_zealand; 1891 break; 1892 case 0x6790: 1893 case 0x6791: 1894 case 0x6792: 1895 case 0x679E: 1896 si_pi->dte_data = dte_data_aruba_pro; 1897 update_dte_from_pl2 = true; 1898 break; 1899 case 0x679B: 1900 si_pi->dte_data = dte_data_malta; 1901 update_dte_from_pl2 = true; 1902 break; 1903 case 0x679A: 1904 si_pi->dte_data = dte_data_tahiti_pro; 1905 update_dte_from_pl2 = true; 1906 break; 1907 default: 1908 if (si_pi->dte_data.enable_dte_by_default == true) 1909 DRM_ERROR("DTE is not enabled!\n"); 1910 break; 1911 } 1912 } else if (rdev->family == CHIP_PITCAIRN) { 1913 switch (rdev->pdev->device) { 1914 case 0x6810: 1915 case 0x6818: 1916 si_pi->cac_weights = cac_weights_pitcairn; 1917 si_pi->lcac_config = lcac_pitcairn; 1918 si_pi->cac_override = cac_override_pitcairn; 1919 si_pi->powertune_data = &powertune_data_pitcairn; 1920 si_pi->dte_data = dte_data_curacao_xt; 1921 update_dte_from_pl2 = true; 1922 break; 1923 case 0x6819: 1924 case 0x6811: 1925 si_pi->cac_weights = cac_weights_pitcairn; 1926 si_pi->lcac_config = lcac_pitcairn; 1927 si_pi->cac_override = cac_override_pitcairn; 1928 si_pi->powertune_data = &powertune_data_pitcairn; 1929 si_pi->dte_data = dte_data_curacao_pro; 1930 update_dte_from_pl2 = true; 1931 break; 1932 case 0x6800: 1933 case 0x6806: 1934 si_pi->cac_weights = cac_weights_pitcairn; 1935 si_pi->lcac_config = lcac_pitcairn; 1936 si_pi->cac_override = cac_override_pitcairn; 1937 si_pi->powertune_data = &powertune_data_pitcairn; 1938 si_pi->dte_data = dte_data_neptune_xt; 1939 update_dte_from_pl2 = true; 1940 break; 1941 default: 1942 si_pi->cac_weights = cac_weights_pitcairn; 1943 si_pi->lcac_config = lcac_pitcairn; 1944 si_pi->cac_override = cac_override_pitcairn; 1945 si_pi->powertune_data = &powertune_data_pitcairn; 1946 si_pi->dte_data = dte_data_pitcairn; 1947 break; 1948 } 1949 } else if (rdev->family == CHIP_VERDE) { 1950 si_pi->lcac_config = lcac_cape_verde; 1951 si_pi->cac_override = cac_override_cape_verde; 1952 si_pi->powertune_data = &powertune_data_cape_verde; 1953 1954 switch (rdev->pdev->device) { 1955 case 0x683B: 1956 case 0x683F: 1957 case 0x6829: 1958 case 0x6835: 1959 si_pi->cac_weights = cac_weights_cape_verde_pro; 1960 si_pi->dte_data = dte_data_cape_verde; 1961 break; 1962 case 0x682C: 1963 si_pi->cac_weights = cac_weights_cape_verde_pro; 1964 si_pi->dte_data = dte_data_sun_xt; 1965 update_dte_from_pl2 = true; 1966 break; 1967 case 0x6825: 1968 case 0x6827: 1969 si_pi->cac_weights = cac_weights_heathrow; 1970 si_pi->dte_data = dte_data_cape_verde; 1971 break; 1972 case 0x6824: 1973 case 0x682D: 1974 si_pi->cac_weights = cac_weights_chelsea_xt; 1975 si_pi->dte_data = dte_data_cape_verde; 1976 break; 1977 case 0x682F: 1978 si_pi->cac_weights = cac_weights_chelsea_pro; 1979 si_pi->dte_data = dte_data_cape_verde; 1980 break; 1981 case 0x6820: 1982 si_pi->cac_weights = cac_weights_heathrow; 1983 si_pi->dte_data = dte_data_venus_xtx; 1984 break; 1985 case 0x6821: 1986 si_pi->cac_weights = cac_weights_heathrow; 1987 si_pi->dte_data = dte_data_venus_xt; 1988 break; 1989 case 0x6823: 1990 case 0x682B: 1991 case 0x6822: 1992 case 0x682A: 1993 si_pi->cac_weights = cac_weights_chelsea_pro; 1994 si_pi->dte_data = dte_data_venus_pro; 1995 break; 1996 default: 1997 si_pi->cac_weights = cac_weights_cape_verde; 1998 si_pi->dte_data = dte_data_cape_verde; 1999 break; 2000 } 2001 } else if (rdev->family == CHIP_OLAND) { 2002 switch (rdev->pdev->device) { 2003 case 0x6601: 2004 case 0x6621: 2005 case 0x6603: 2006 case 0x6605: 2007 si_pi->cac_weights = cac_weights_mars_pro; 2008 si_pi->lcac_config = lcac_mars_pro; 2009 si_pi->cac_override = cac_override_oland; 2010 si_pi->powertune_data = &powertune_data_mars_pro; 2011 si_pi->dte_data = dte_data_mars_pro; 2012 update_dte_from_pl2 = true; 2013 break; 2014 case 0x6600: 2015 case 0x6606: 2016 case 0x6620: 2017 case 0x6604: 2018 si_pi->cac_weights = cac_weights_mars_xt; 2019 si_pi->lcac_config = lcac_mars_pro; 2020 si_pi->cac_override = cac_override_oland; 2021 si_pi->powertune_data = &powertune_data_mars_pro; 2022 si_pi->dte_data = dte_data_mars_pro; 2023 update_dte_from_pl2 = true; 2024 break; 2025 case 0x6611: 2026 case 0x6613: 2027 case 0x6608: 2028 si_pi->cac_weights = cac_weights_oland_pro; 2029 si_pi->lcac_config = lcac_mars_pro; 2030 si_pi->cac_override = cac_override_oland; 2031 si_pi->powertune_data = &powertune_data_mars_pro; 2032 si_pi->dte_data = dte_data_mars_pro; 2033 update_dte_from_pl2 = true; 2034 break; 2035 case 0x6610: 2036 si_pi->cac_weights = cac_weights_oland_xt; 2037 si_pi->lcac_config = lcac_mars_pro; 2038 si_pi->cac_override = cac_override_oland; 2039 si_pi->powertune_data = &powertune_data_mars_pro; 2040 si_pi->dte_data = dte_data_mars_pro; 2041 update_dte_from_pl2 = true; 2042 break; 2043 default: 2044 si_pi->cac_weights = cac_weights_oland; 2045 si_pi->lcac_config = lcac_oland; 2046 si_pi->cac_override = cac_override_oland; 2047 si_pi->powertune_data = &powertune_data_oland; 2048 si_pi->dte_data = dte_data_oland; 2049 break; 2050 } 2051 } else if (rdev->family == CHIP_HAINAN) { 2052 si_pi->cac_weights = cac_weights_hainan; 2053 si_pi->lcac_config = lcac_oland; 2054 si_pi->cac_override = cac_override_oland; 2055 si_pi->powertune_data = &powertune_data_hainan; 2056 si_pi->dte_data = dte_data_sun_xt; 2057 update_dte_from_pl2 = true; 2058 } else { 2059 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2060 return; 2061 } 2062 2063 ni_pi->enable_power_containment = false; 2064 ni_pi->enable_cac = false; 2065 ni_pi->enable_sq_ramping = false; 2066 si_pi->enable_dte = false; 2067 2068 if (si_pi->powertune_data->enable_powertune_by_default) { 2069 ni_pi->enable_power_containment= true; 2070 ni_pi->enable_cac = true; 2071 if (si_pi->dte_data.enable_dte_by_default) { 2072 si_pi->enable_dte = true; 2073 if (update_dte_from_pl2) 2074 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2075 2076 } 2077 ni_pi->enable_sq_ramping = true; 2078 } 2079 2080 ni_pi->driver_calculate_cac_leakage = true; 2081 ni_pi->cac_configuration_required = true; 2082 2083 if (ni_pi->cac_configuration_required) { 2084 ni_pi->support_cac_long_term_average = true; 2085 si_pi->dyn_powertune_data.l2_lta_window_size = 2086 si_pi->powertune_data->l2_lta_window_size_default; 2087 si_pi->dyn_powertune_data.lts_truncate = 2088 si_pi->powertune_data->lts_truncate_default; 2089 } else { 2090 ni_pi->support_cac_long_term_average = false; 2091 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2092 si_pi->dyn_powertune_data.lts_truncate = 0; 2093 } 2094 2095 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2096 } 2097 2098 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2099 { 2100 return 1; 2101 } 2102 2103 static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2104 { 2105 u32 xclk; 2106 u32 wintime; 2107 u32 cac_window; 2108 u32 cac_window_size; 2109 2110 xclk = radeon_get_xclk(rdev); 2111 2112 if (xclk == 0) 2113 return 0; 2114 2115 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2116 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2117 2118 wintime = (cac_window_size * 100) / xclk; 2119 2120 return wintime; 2121 } 2122 2123 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2124 { 2125 return power_in_watts; 2126 } 2127 2128 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2129 bool adjust_polarity, 2130 u32 tdp_adjustment, 2131 u32 *tdp_limit, 2132 u32 *near_tdp_limit) 2133 { 2134 u32 adjustment_delta, max_tdp_limit; 2135 2136 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2137 return -EINVAL; 2138 2139 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2140 2141 if (adjust_polarity) { 2142 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2143 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2144 } else { 2145 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2146 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2147 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2148 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2149 else 2150 *near_tdp_limit = 0; 2151 } 2152 2153 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2154 return -EINVAL; 2155 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2156 return -EINVAL; 2157 2158 return 0; 2159 } 2160 2161 static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2162 struct radeon_ps *radeon_state) 2163 { 2164 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2165 struct si_power_info *si_pi = si_get_pi(rdev); 2166 2167 if (ni_pi->enable_power_containment) { 2168 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2169 PP_SIslands_PAPMParameters *papm_parm; 2170 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2171 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2172 u32 tdp_limit; 2173 u32 near_tdp_limit; 2174 int ret; 2175 2176 if (scaling_factor == 0) 2177 return -EINVAL; 2178 2179 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2180 2181 ret = si_calculate_adjusted_tdp_limits(rdev, 2182 false, /* ??? */ 2183 rdev->pm.dpm.tdp_adjustment, 2184 &tdp_limit, 2185 &near_tdp_limit); 2186 if (ret) 2187 return ret; 2188 2189 smc_table->dpm2Params.TDPLimit = 2190 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2191 smc_table->dpm2Params.NearTDPLimit = 2192 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2193 smc_table->dpm2Params.SafePowerLimit = 2194 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2195 2196 ret = si_copy_bytes_to_smc(rdev, 2197 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2198 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2199 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2200 sizeof(u32) * 3, 2201 si_pi->sram_end); 2202 if (ret) 2203 return ret; 2204 2205 if (si_pi->enable_ppm) { 2206 papm_parm = &si_pi->papm_parm; 2207 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2208 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2209 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2210 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2211 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2212 papm_parm->PlatformPowerLimit = 0xffffffff; 2213 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2214 2215 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2216 (u8 *)papm_parm, 2217 sizeof(PP_SIslands_PAPMParameters), 2218 si_pi->sram_end); 2219 if (ret) 2220 return ret; 2221 } 2222 } 2223 return 0; 2224 } 2225 2226 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2227 struct radeon_ps *radeon_state) 2228 { 2229 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2230 struct si_power_info *si_pi = si_get_pi(rdev); 2231 2232 if (ni_pi->enable_power_containment) { 2233 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2234 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2235 int ret; 2236 2237 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2238 2239 smc_table->dpm2Params.NearTDPLimit = 2240 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2241 smc_table->dpm2Params.SafePowerLimit = 2242 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2243 2244 ret = si_copy_bytes_to_smc(rdev, 2245 (si_pi->state_table_start + 2246 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2247 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2248 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2249 sizeof(u32) * 2, 2250 si_pi->sram_end); 2251 if (ret) 2252 return ret; 2253 } 2254 2255 return 0; 2256 } 2257 2258 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2259 const u16 prev_std_vddc, 2260 const u16 curr_std_vddc) 2261 { 2262 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2263 u64 prev_vddc = (u64)prev_std_vddc; 2264 u64 curr_vddc = (u64)curr_std_vddc; 2265 u64 pwr_efficiency_ratio, n, d; 2266 2267 if ((prev_vddc == 0) || (curr_vddc == 0)) 2268 return 0; 2269 2270 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2271 d = prev_vddc * prev_vddc; 2272 pwr_efficiency_ratio = div64_u64(n, d); 2273 2274 if (pwr_efficiency_ratio > (u64)0xFFFF) 2275 return 0; 2276 2277 return (u16)pwr_efficiency_ratio; 2278 } 2279 2280 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2281 struct radeon_ps *radeon_state) 2282 { 2283 struct si_power_info *si_pi = si_get_pi(rdev); 2284 2285 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2286 radeon_state->vclk && radeon_state->dclk) 2287 return true; 2288 2289 return false; 2290 } 2291 2292 static int si_populate_power_containment_values(struct radeon_device *rdev, 2293 struct radeon_ps *radeon_state, 2294 SISLANDS_SMC_SWSTATE *smc_state) 2295 { 2296 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2297 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2298 struct ni_ps *state = ni_get_ps(radeon_state); 2299 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2300 u32 prev_sclk; 2301 u32 max_sclk; 2302 u32 min_sclk; 2303 u16 prev_std_vddc; 2304 u16 curr_std_vddc; 2305 int i; 2306 u16 pwr_efficiency_ratio; 2307 u8 max_ps_percent; 2308 bool disable_uvd_power_tune; 2309 int ret; 2310 2311 if (ni_pi->enable_power_containment == false) 2312 return 0; 2313 2314 if (state->performance_level_count == 0) 2315 return -EINVAL; 2316 2317 if (smc_state->levelCount != state->performance_level_count) 2318 return -EINVAL; 2319 2320 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2321 2322 smc_state->levels[0].dpm2.MaxPS = 0; 2323 smc_state->levels[0].dpm2.NearTDPDec = 0; 2324 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2325 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2326 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2327 2328 for (i = 1; i < state->performance_level_count; i++) { 2329 prev_sclk = state->performance_levels[i-1].sclk; 2330 max_sclk = state->performance_levels[i].sclk; 2331 if (i == 1) 2332 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2333 else 2334 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2335 2336 if (prev_sclk > max_sclk) 2337 return -EINVAL; 2338 2339 if ((max_ps_percent == 0) || 2340 (prev_sclk == max_sclk) || 2341 disable_uvd_power_tune) { 2342 min_sclk = max_sclk; 2343 } else if (i == 1) { 2344 min_sclk = prev_sclk; 2345 } else { 2346 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2347 } 2348 2349 if (min_sclk < state->performance_levels[0].sclk) 2350 min_sclk = state->performance_levels[0].sclk; 2351 2352 if (min_sclk == 0) 2353 return -EINVAL; 2354 2355 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2356 state->performance_levels[i-1].vddc, &vddc); 2357 if (ret) 2358 return ret; 2359 2360 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2361 if (ret) 2362 return ret; 2363 2364 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2365 state->performance_levels[i].vddc, &vddc); 2366 if (ret) 2367 return ret; 2368 2369 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2370 if (ret) 2371 return ret; 2372 2373 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2374 prev_std_vddc, curr_std_vddc); 2375 2376 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2377 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2378 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2379 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2380 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2387 struct radeon_ps *radeon_state, 2388 SISLANDS_SMC_SWSTATE *smc_state) 2389 { 2390 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2391 struct ni_ps *state = ni_get_ps(radeon_state); 2392 u32 sq_power_throttle, sq_power_throttle2; 2393 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2394 int i; 2395 2396 if (state->performance_level_count == 0) 2397 return -EINVAL; 2398 2399 if (smc_state->levelCount != state->performance_level_count) 2400 return -EINVAL; 2401 2402 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2403 return -EINVAL; 2404 2405 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2406 enable_sq_ramping = false; 2407 2408 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2409 enable_sq_ramping = false; 2410 2411 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2412 enable_sq_ramping = false; 2413 2414 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2415 enable_sq_ramping = false; 2416 2417 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2418 enable_sq_ramping = false; 2419 2420 for (i = 0; i < state->performance_level_count; i++) { 2421 sq_power_throttle = 0; 2422 sq_power_throttle2 = 0; 2423 2424 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2425 enable_sq_ramping) { 2426 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2427 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2428 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2429 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2430 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2431 } else { 2432 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2433 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2434 } 2435 2436 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2437 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2438 } 2439 2440 return 0; 2441 } 2442 2443 static int si_enable_power_containment(struct radeon_device *rdev, 2444 struct radeon_ps *radeon_new_state, 2445 bool enable) 2446 { 2447 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2448 PPSMC_Result smc_result; 2449 int ret = 0; 2450 2451 if (ni_pi->enable_power_containment) { 2452 if (enable) { 2453 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2454 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2455 if (smc_result != PPSMC_Result_OK) { 2456 ret = -EINVAL; 2457 ni_pi->pc_enabled = false; 2458 } else { 2459 ni_pi->pc_enabled = true; 2460 } 2461 } 2462 } else { 2463 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2464 if (smc_result != PPSMC_Result_OK) 2465 ret = -EINVAL; 2466 ni_pi->pc_enabled = false; 2467 } 2468 } 2469 2470 return ret; 2471 } 2472 2473 static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2474 { 2475 struct si_power_info *si_pi = si_get_pi(rdev); 2476 int ret = 0; 2477 struct si_dte_data *dte_data = &si_pi->dte_data; 2478 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2479 u32 table_size; 2480 u8 tdep_count; 2481 u32 i; 2482 2483 if (dte_data == NULL) 2484 si_pi->enable_dte = false; 2485 2486 if (si_pi->enable_dte == false) 2487 return 0; 2488 2489 if (dte_data->k <= 0) 2490 return -EINVAL; 2491 2492 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2493 if (dte_tables == NULL) { 2494 si_pi->enable_dte = false; 2495 return -ENOMEM; 2496 } 2497 2498 table_size = dte_data->k; 2499 2500 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2501 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2502 2503 tdep_count = dte_data->tdep_count; 2504 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2505 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2506 2507 dte_tables->K = cpu_to_be32(table_size); 2508 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2509 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2510 dte_tables->WindowSize = dte_data->window_size; 2511 dte_tables->temp_select = dte_data->temp_select; 2512 dte_tables->DTE_mode = dte_data->dte_mode; 2513 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2514 2515 if (tdep_count > 0) 2516 table_size--; 2517 2518 for (i = 0; i < table_size; i++) { 2519 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2520 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2521 } 2522 2523 dte_tables->Tdep_count = tdep_count; 2524 2525 for (i = 0; i < (u32)tdep_count; i++) { 2526 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2527 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2528 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2529 } 2530 2531 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2532 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2533 kfree(dte_tables); 2534 2535 return ret; 2536 } 2537 2538 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2539 u16 *max, u16 *min) 2540 { 2541 struct si_power_info *si_pi = si_get_pi(rdev); 2542 struct radeon_cac_leakage_table *table = 2543 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2544 u32 i; 2545 u32 v0_loadline; 2546 2547 2548 if (table == NULL) 2549 return -EINVAL; 2550 2551 *max = 0; 2552 *min = 0xFFFF; 2553 2554 for (i = 0; i < table->count; i++) { 2555 if (table->entries[i].vddc > *max) 2556 *max = table->entries[i].vddc; 2557 if (table->entries[i].vddc < *min) 2558 *min = table->entries[i].vddc; 2559 } 2560 2561 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2562 return -EINVAL; 2563 2564 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2565 2566 if (v0_loadline > 0xFFFFUL) 2567 return -EINVAL; 2568 2569 *min = (u16)v0_loadline; 2570 2571 if ((*min > *max) || (*max == 0) || (*min == 0)) 2572 return -EINVAL; 2573 2574 return 0; 2575 } 2576 2577 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2578 { 2579 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2580 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2581 } 2582 2583 static int si_init_dte_leakage_table(struct radeon_device *rdev, 2584 PP_SIslands_CacConfig *cac_tables, 2585 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2586 u16 t0, u16 t_step) 2587 { 2588 struct si_power_info *si_pi = si_get_pi(rdev); 2589 u32 leakage; 2590 unsigned int i, j; 2591 s32 t; 2592 u32 smc_leakage; 2593 u32 scaling_factor; 2594 u16 voltage; 2595 2596 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2597 2598 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2599 t = (1000 * (i * t_step + t0)); 2600 2601 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2602 voltage = vddc_max - (vddc_step * j); 2603 2604 si_calculate_leakage_for_v_and_t(rdev, 2605 &si_pi->powertune_data->leakage_coefficients, 2606 voltage, 2607 t, 2608 si_pi->dyn_powertune_data.cac_leakage, 2609 &leakage); 2610 2611 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2612 2613 if (smc_leakage > 0xFFFF) 2614 smc_leakage = 0xFFFF; 2615 2616 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2617 cpu_to_be16((u16)smc_leakage); 2618 } 2619 } 2620 return 0; 2621 } 2622 2623 static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2624 PP_SIslands_CacConfig *cac_tables, 2625 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2626 { 2627 struct si_power_info *si_pi = si_get_pi(rdev); 2628 u32 leakage; 2629 unsigned int i, j; 2630 u32 smc_leakage; 2631 u32 scaling_factor; 2632 u16 voltage; 2633 2634 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2635 2636 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2637 voltage = vddc_max - (vddc_step * j); 2638 2639 si_calculate_leakage_for_v(rdev, 2640 &si_pi->powertune_data->leakage_coefficients, 2641 si_pi->powertune_data->fixed_kt, 2642 voltage, 2643 si_pi->dyn_powertune_data.cac_leakage, 2644 &leakage); 2645 2646 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2647 2648 if (smc_leakage > 0xFFFF) 2649 smc_leakage = 0xFFFF; 2650 2651 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2652 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2653 cpu_to_be16((u16)smc_leakage); 2654 } 2655 return 0; 2656 } 2657 2658 static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2659 { 2660 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2661 struct si_power_info *si_pi = si_get_pi(rdev); 2662 PP_SIslands_CacConfig *cac_tables = NULL; 2663 u16 vddc_max, vddc_min, vddc_step; 2664 u16 t0, t_step; 2665 u32 load_line_slope, reg; 2666 int ret = 0; 2667 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2668 2669 if (ni_pi->enable_cac == false) 2670 return 0; 2671 2672 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2673 if (!cac_tables) 2674 return -ENOMEM; 2675 2676 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2677 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2678 WREG32(CG_CAC_CTRL, reg); 2679 2680 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2681 si_pi->dyn_powertune_data.dc_pwr_value = 2682 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2683 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2684 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2685 2686 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2687 2688 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2689 if (ret) 2690 goto done_free; 2691 2692 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2693 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2694 t_step = 4; 2695 t0 = 60; 2696 2697 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2698 ret = si_init_dte_leakage_table(rdev, cac_tables, 2699 vddc_max, vddc_min, vddc_step, 2700 t0, t_step); 2701 else 2702 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2703 vddc_max, vddc_min, vddc_step); 2704 if (ret) 2705 goto done_free; 2706 2707 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2708 2709 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2710 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2711 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2712 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2713 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2714 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2715 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2716 cac_tables->calculation_repeats = cpu_to_be32(2); 2717 cac_tables->dc_cac = cpu_to_be32(0); 2718 cac_tables->log2_PG_LKG_SCALE = 12; 2719 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2720 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2721 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2722 2723 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2724 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2725 2726 if (ret) 2727 goto done_free; 2728 2729 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2730 2731 done_free: 2732 if (ret) { 2733 ni_pi->enable_cac = false; 2734 ni_pi->enable_power_containment = false; 2735 } 2736 2737 kfree(cac_tables); 2738 2739 return 0; 2740 } 2741 2742 static int si_program_cac_config_registers(struct radeon_device *rdev, 2743 const struct si_cac_config_reg *cac_config_regs) 2744 { 2745 const struct si_cac_config_reg *config_regs = cac_config_regs; 2746 u32 data = 0, offset; 2747 2748 if (!config_regs) 2749 return -EINVAL; 2750 2751 while (config_regs->offset != 0xFFFFFFFF) { 2752 switch (config_regs->type) { 2753 case SISLANDS_CACCONFIG_CGIND: 2754 offset = SMC_CG_IND_START + config_regs->offset; 2755 if (offset < SMC_CG_IND_END) 2756 data = RREG32_SMC(offset); 2757 break; 2758 default: 2759 data = RREG32(config_regs->offset << 2); 2760 break; 2761 } 2762 2763 data &= ~config_regs->mask; 2764 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2765 2766 switch (config_regs->type) { 2767 case SISLANDS_CACCONFIG_CGIND: 2768 offset = SMC_CG_IND_START + config_regs->offset; 2769 if (offset < SMC_CG_IND_END) 2770 WREG32_SMC(offset, data); 2771 break; 2772 default: 2773 WREG32(config_regs->offset << 2, data); 2774 break; 2775 } 2776 config_regs++; 2777 } 2778 return 0; 2779 } 2780 2781 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2782 { 2783 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2784 struct si_power_info *si_pi = si_get_pi(rdev); 2785 int ret; 2786 2787 if ((ni_pi->enable_cac == false) || 2788 (ni_pi->cac_configuration_required == false)) 2789 return 0; 2790 2791 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2792 if (ret) 2793 return ret; 2794 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2795 if (ret) 2796 return ret; 2797 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2798 if (ret) 2799 return ret; 2800 2801 return 0; 2802 } 2803 2804 static int si_enable_smc_cac(struct radeon_device *rdev, 2805 struct radeon_ps *radeon_new_state, 2806 bool enable) 2807 { 2808 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2809 struct si_power_info *si_pi = si_get_pi(rdev); 2810 PPSMC_Result smc_result; 2811 int ret = 0; 2812 2813 if (ni_pi->enable_cac) { 2814 if (enable) { 2815 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2816 if (ni_pi->support_cac_long_term_average) { 2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2818 if (smc_result != PPSMC_Result_OK) 2819 ni_pi->support_cac_long_term_average = false; 2820 } 2821 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2823 if (smc_result != PPSMC_Result_OK) { 2824 ret = -EINVAL; 2825 ni_pi->cac_enabled = false; 2826 } else { 2827 ni_pi->cac_enabled = true; 2828 } 2829 2830 if (si_pi->enable_dte) { 2831 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2832 if (smc_result != PPSMC_Result_OK) 2833 ret = -EINVAL; 2834 } 2835 } 2836 } else if (ni_pi->cac_enabled) { 2837 if (si_pi->enable_dte) 2838 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2839 2840 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2841 2842 ni_pi->cac_enabled = false; 2843 2844 if (ni_pi->support_cac_long_term_average) 2845 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2846 } 2847 } 2848 return ret; 2849 } 2850 2851 static int si_init_smc_spll_table(struct radeon_device *rdev) 2852 { 2853 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2854 struct si_power_info *si_pi = si_get_pi(rdev); 2855 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2856 SISLANDS_SMC_SCLK_VALUE sclk_params; 2857 u32 fb_div, p_div; 2858 u32 clk_s, clk_v; 2859 u32 sclk = 0; 2860 int ret = 0; 2861 u32 tmp; 2862 int i; 2863 2864 if (si_pi->spll_table_start == 0) 2865 return -EINVAL; 2866 2867 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2868 if (spll_table == NULL) 2869 return -ENOMEM; 2870 2871 for (i = 0; i < 256; i++) { 2872 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2873 if (ret) 2874 break; 2875 2876 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2877 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2878 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2879 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2880 2881 fb_div &= ~0x00001FFF; 2882 fb_div >>= 1; 2883 clk_v >>= 6; 2884 2885 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2886 ret = -EINVAL; 2887 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2888 ret = -EINVAL; 2889 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2890 ret = -EINVAL; 2891 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2892 ret = -EINVAL; 2893 2894 if (ret) 2895 break; 2896 2897 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2898 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2899 spll_table->freq[i] = cpu_to_be32(tmp); 2900 2901 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2902 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2903 spll_table->ss[i] = cpu_to_be32(tmp); 2904 2905 sclk += 512; 2906 } 2907 2908 2909 if (!ret) 2910 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2911 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2912 si_pi->sram_end); 2913 2914 if (ret) 2915 ni_pi->enable_power_containment = false; 2916 2917 kfree(spll_table); 2918 2919 return ret; 2920 } 2921 2922 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2923 u16 vce_voltage) 2924 { 2925 u16 highest_leakage = 0; 2926 struct si_power_info *si_pi = si_get_pi(rdev); 2927 int i; 2928 2929 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2930 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2931 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2932 } 2933 2934 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2935 return highest_leakage; 2936 2937 return vce_voltage; 2938 } 2939 2940 static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2941 u32 evclk, u32 ecclk, u16 *voltage) 2942 { 2943 u32 i; 2944 int ret = -EINVAL; 2945 struct radeon_vce_clock_voltage_dependency_table *table = 2946 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2947 2948 if (((evclk == 0) && (ecclk == 0)) || 2949 (table && (table->count == 0))) { 2950 *voltage = 0; 2951 return 0; 2952 } 2953 2954 for (i = 0; i < table->count; i++) { 2955 if ((evclk <= table->entries[i].evclk) && 2956 (ecclk <= table->entries[i].ecclk)) { 2957 *voltage = table->entries[i].v; 2958 ret = 0; 2959 break; 2960 } 2961 } 2962 2963 /* if no match return the highest voltage */ 2964 if (ret) 2965 *voltage = table->entries[table->count - 1].v; 2966 2967 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2968 2969 return ret; 2970 } 2971 2972 static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2973 struct radeon_ps *rps) 2974 { 2975 struct ni_ps *ps = ni_get_ps(rps); 2976 struct radeon_clock_and_voltage_limits *max_limits; 2977 bool disable_mclk_switching = false; 2978 bool disable_sclk_switching = false; 2979 u32 mclk, sclk; 2980 u16 vddc, vddci, min_vce_voltage = 0; 2981 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2982 u32 max_sclk = 0, max_mclk = 0; 2983 int i; 2984 2985 if (rdev->family == CHIP_HAINAN) { 2986 if ((rdev->pdev->revision == 0x81) || 2987 (rdev->pdev->revision == 0x83) || 2988 (rdev->pdev->revision == 0xC3) || 2989 (rdev->pdev->device == 0x6664) || 2990 (rdev->pdev->device == 0x6665) || 2991 (rdev->pdev->device == 0x6667)) { 2992 max_sclk = 75000; 2993 } 2994 if ((rdev->pdev->revision == 0xC3) || 2995 (rdev->pdev->device == 0x6665)) { 2996 max_sclk = 60000; 2997 max_mclk = 80000; 2998 } 2999 } else if (rdev->family == CHIP_OLAND) { 3000 if ((rdev->pdev->revision == 0xC7) || 3001 (rdev->pdev->revision == 0x80) || 3002 (rdev->pdev->revision == 0x81) || 3003 (rdev->pdev->revision == 0x83) || 3004 (rdev->pdev->revision == 0x87) || 3005 (rdev->pdev->device == 0x6604) || 3006 (rdev->pdev->device == 0x6605)) { 3007 max_sclk = 75000; 3008 } 3009 } 3010 3011 if (rps->vce_active) { 3012 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 3013 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 3014 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 3015 &min_vce_voltage); 3016 } else { 3017 rps->evclk = 0; 3018 rps->ecclk = 0; 3019 } 3020 3021 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3022 ni_dpm_vblank_too_short(rdev)) 3023 disable_mclk_switching = true; 3024 3025 if (rps->vclk || rps->dclk) { 3026 disable_mclk_switching = true; 3027 disable_sclk_switching = true; 3028 } 3029 3030 if (rdev->pm.dpm.ac_power) 3031 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3032 else 3033 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3034 3035 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3036 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3037 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3038 } 3039 if (rdev->pm.dpm.ac_power == false) { 3040 for (i = 0; i < ps->performance_level_count; i++) { 3041 if (ps->performance_levels[i].mclk > max_limits->mclk) 3042 ps->performance_levels[i].mclk = max_limits->mclk; 3043 if (ps->performance_levels[i].sclk > max_limits->sclk) 3044 ps->performance_levels[i].sclk = max_limits->sclk; 3045 if (ps->performance_levels[i].vddc > max_limits->vddc) 3046 ps->performance_levels[i].vddc = max_limits->vddc; 3047 if (ps->performance_levels[i].vddci > max_limits->vddci) 3048 ps->performance_levels[i].vddci = max_limits->vddci; 3049 } 3050 } 3051 3052 /* limit clocks to max supported clocks based on voltage dependency tables */ 3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3054 &max_sclk_vddc); 3055 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3056 &max_mclk_vddci); 3057 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3058 &max_mclk_vddc); 3059 3060 for (i = 0; i < ps->performance_level_count; i++) { 3061 if (max_sclk_vddc) { 3062 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3063 ps->performance_levels[i].sclk = max_sclk_vddc; 3064 } 3065 if (max_mclk_vddci) { 3066 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3067 ps->performance_levels[i].mclk = max_mclk_vddci; 3068 } 3069 if (max_mclk_vddc) { 3070 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3071 ps->performance_levels[i].mclk = max_mclk_vddc; 3072 } 3073 if (max_mclk) { 3074 if (ps->performance_levels[i].mclk > max_mclk) 3075 ps->performance_levels[i].mclk = max_mclk; 3076 } 3077 if (max_sclk) { 3078 if (ps->performance_levels[i].sclk > max_sclk) 3079 ps->performance_levels[i].sclk = max_sclk; 3080 } 3081 } 3082 3083 /* XXX validate the min clocks required for display */ 3084 3085 if (disable_mclk_switching) { 3086 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3087 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3088 } else { 3089 mclk = ps->performance_levels[0].mclk; 3090 vddci = ps->performance_levels[0].vddci; 3091 } 3092 3093 if (disable_sclk_switching) { 3094 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3095 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3096 } else { 3097 sclk = ps->performance_levels[0].sclk; 3098 vddc = ps->performance_levels[0].vddc; 3099 } 3100 3101 if (rps->vce_active) { 3102 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3103 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3104 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3105 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3106 } 3107 3108 /* adjusted low state */ 3109 ps->performance_levels[0].sclk = sclk; 3110 ps->performance_levels[0].mclk = mclk; 3111 ps->performance_levels[0].vddc = vddc; 3112 ps->performance_levels[0].vddci = vddci; 3113 3114 if (disable_sclk_switching) { 3115 sclk = ps->performance_levels[0].sclk; 3116 for (i = 1; i < ps->performance_level_count; i++) { 3117 if (sclk < ps->performance_levels[i].sclk) 3118 sclk = ps->performance_levels[i].sclk; 3119 } 3120 for (i = 0; i < ps->performance_level_count; i++) { 3121 ps->performance_levels[i].sclk = sclk; 3122 ps->performance_levels[i].vddc = vddc; 3123 } 3124 } else { 3125 for (i = 1; i < ps->performance_level_count; i++) { 3126 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3127 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3128 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3129 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3130 } 3131 } 3132 3133 if (disable_mclk_switching) { 3134 mclk = ps->performance_levels[0].mclk; 3135 for (i = 1; i < ps->performance_level_count; i++) { 3136 if (mclk < ps->performance_levels[i].mclk) 3137 mclk = ps->performance_levels[i].mclk; 3138 } 3139 for (i = 0; i < ps->performance_level_count; i++) { 3140 ps->performance_levels[i].mclk = mclk; 3141 ps->performance_levels[i].vddci = vddci; 3142 } 3143 } else { 3144 for (i = 1; i < ps->performance_level_count; i++) { 3145 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3146 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3147 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3148 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3149 } 3150 } 3151 3152 for (i = 0; i < ps->performance_level_count; i++) 3153 btc_adjust_clock_combinations(rdev, max_limits, 3154 &ps->performance_levels[i]); 3155 3156 for (i = 0; i < ps->performance_level_count; i++) { 3157 if (ps->performance_levels[i].vddc < min_vce_voltage) 3158 ps->performance_levels[i].vddc = min_vce_voltage; 3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3160 ps->performance_levels[i].sclk, 3161 max_limits->vddc, &ps->performance_levels[i].vddc); 3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3163 ps->performance_levels[i].mclk, 3164 max_limits->vddci, &ps->performance_levels[i].vddci); 3165 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3166 ps->performance_levels[i].mclk, 3167 max_limits->vddc, &ps->performance_levels[i].vddc); 3168 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3169 rdev->clock.current_dispclk, 3170 max_limits->vddc, &ps->performance_levels[i].vddc); 3171 } 3172 3173 for (i = 0; i < ps->performance_level_count; i++) { 3174 btc_apply_voltage_delta_rules(rdev, 3175 max_limits->vddc, max_limits->vddci, 3176 &ps->performance_levels[i].vddc, 3177 &ps->performance_levels[i].vddci); 3178 } 3179 3180 ps->dc_compatible = true; 3181 for (i = 0; i < ps->performance_level_count; i++) { 3182 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3183 ps->dc_compatible = false; 3184 } 3185 } 3186 3187 #if 0 3188 static int si_read_smc_soft_register(struct radeon_device *rdev, 3189 u16 reg_offset, u32 *value) 3190 { 3191 struct si_power_info *si_pi = si_get_pi(rdev); 3192 3193 return si_read_smc_sram_dword(rdev, 3194 si_pi->soft_regs_start + reg_offset, value, 3195 si_pi->sram_end); 3196 } 3197 #endif 3198 3199 static int si_write_smc_soft_register(struct radeon_device *rdev, 3200 u16 reg_offset, u32 value) 3201 { 3202 struct si_power_info *si_pi = si_get_pi(rdev); 3203 3204 return si_write_smc_sram_dword(rdev, 3205 si_pi->soft_regs_start + reg_offset, 3206 value, si_pi->sram_end); 3207 } 3208 3209 static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3210 { 3211 bool ret = false; 3212 u32 tmp, width, row, column, bank, density; 3213 bool is_memory_gddr5, is_special; 3214 3215 tmp = RREG32(MC_SEQ_MISC0); 3216 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3217 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3218 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3219 3220 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3221 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3222 3223 tmp = RREG32(MC_ARB_RAMCFG); 3224 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3225 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3226 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3227 3228 density = (1 << (row + column - 20 + bank)) * width; 3229 3230 if ((rdev->pdev->device == 0x6819) && 3231 is_memory_gddr5 && is_special && (density == 0x400)) 3232 ret = true; 3233 3234 return ret; 3235 } 3236 3237 static void si_get_leakage_vddc(struct radeon_device *rdev) 3238 { 3239 struct si_power_info *si_pi = si_get_pi(rdev); 3240 u16 vddc, count = 0; 3241 int i, ret; 3242 3243 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3244 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3245 3246 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3247 si_pi->leakage_voltage.entries[count].voltage = vddc; 3248 si_pi->leakage_voltage.entries[count].leakage_index = 3249 SISLANDS_LEAKAGE_INDEX0 + i; 3250 count++; 3251 } 3252 } 3253 si_pi->leakage_voltage.count = count; 3254 } 3255 3256 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3257 u32 index, u16 *leakage_voltage) 3258 { 3259 struct si_power_info *si_pi = si_get_pi(rdev); 3260 int i; 3261 3262 if (leakage_voltage == NULL) 3263 return -EINVAL; 3264 3265 if ((index & 0xff00) != 0xff00) 3266 return -EINVAL; 3267 3268 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3269 return -EINVAL; 3270 3271 if (index < SISLANDS_LEAKAGE_INDEX0) 3272 return -EINVAL; 3273 3274 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3275 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3276 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3277 return 0; 3278 } 3279 } 3280 return -EAGAIN; 3281 } 3282 3283 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3284 { 3285 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3286 bool want_thermal_protection; 3287 enum radeon_dpm_event_src dpm_event_src; 3288 3289 switch (sources) { 3290 case 0: 3291 default: 3292 want_thermal_protection = false; 3293 break; 3294 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3295 want_thermal_protection = true; 3296 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3297 break; 3298 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3299 want_thermal_protection = true; 3300 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3301 break; 3302 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3303 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3304 want_thermal_protection = true; 3305 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3306 break; 3307 } 3308 3309 if (want_thermal_protection) { 3310 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3311 if (pi->thermal_protection) 3312 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3313 } else { 3314 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3315 } 3316 } 3317 3318 static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3319 enum radeon_dpm_auto_throttle_src source, 3320 bool enable) 3321 { 3322 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3323 3324 if (enable) { 3325 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3326 pi->active_auto_throttle_sources |= 1 << source; 3327 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3328 } 3329 } else { 3330 if (pi->active_auto_throttle_sources & (1 << source)) { 3331 pi->active_auto_throttle_sources &= ~(1 << source); 3332 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3333 } 3334 } 3335 } 3336 3337 static void si_start_dpm(struct radeon_device *rdev) 3338 { 3339 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3340 } 3341 3342 static void si_stop_dpm(struct radeon_device *rdev) 3343 { 3344 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3345 } 3346 3347 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3348 { 3349 if (enable) 3350 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3351 else 3352 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3353 3354 } 3355 3356 #if 0 3357 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3358 u32 thermal_level) 3359 { 3360 PPSMC_Result ret; 3361 3362 if (thermal_level == 0) { 3363 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3364 if (ret == PPSMC_Result_OK) 3365 return 0; 3366 else 3367 return -EINVAL; 3368 } 3369 return 0; 3370 } 3371 3372 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3373 { 3374 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3375 } 3376 #endif 3377 3378 #if 0 3379 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3380 { 3381 if (ac_power) 3382 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3383 0 : -EINVAL; 3384 3385 return 0; 3386 } 3387 #endif 3388 3389 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3390 PPSMC_Msg msg, u32 parameter) 3391 { 3392 WREG32(SMC_SCRATCH0, parameter); 3393 return si_send_msg_to_smc(rdev, msg); 3394 } 3395 3396 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3397 { 3398 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3399 return -EINVAL; 3400 3401 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3402 0 : -EINVAL; 3403 } 3404 3405 int si_dpm_force_performance_level(struct radeon_device *rdev, 3406 enum radeon_dpm_forced_level level) 3407 { 3408 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3409 struct ni_ps *ps = ni_get_ps(rps); 3410 u32 levels = ps->performance_level_count; 3411 3412 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3413 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3414 return -EINVAL; 3415 3416 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3417 return -EINVAL; 3418 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3419 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3420 return -EINVAL; 3421 3422 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3423 return -EINVAL; 3424 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3425 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3426 return -EINVAL; 3427 3428 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3429 return -EINVAL; 3430 } 3431 3432 rdev->pm.dpm.forced_level = level; 3433 3434 return 0; 3435 } 3436 3437 #if 0 3438 static int si_set_boot_state(struct radeon_device *rdev) 3439 { 3440 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3441 0 : -EINVAL; 3442 } 3443 #endif 3444 3445 static int si_set_sw_state(struct radeon_device *rdev) 3446 { 3447 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3448 0 : -EINVAL; 3449 } 3450 3451 static int si_halt_smc(struct radeon_device *rdev) 3452 { 3453 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3454 return -EINVAL; 3455 3456 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3457 0 : -EINVAL; 3458 } 3459 3460 static int si_resume_smc(struct radeon_device *rdev) 3461 { 3462 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3463 return -EINVAL; 3464 3465 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3466 0 : -EINVAL; 3467 } 3468 3469 static void si_dpm_start_smc(struct radeon_device *rdev) 3470 { 3471 si_program_jump_on_start(rdev); 3472 si_start_smc(rdev); 3473 si_start_smc_clock(rdev); 3474 } 3475 3476 static void si_dpm_stop_smc(struct radeon_device *rdev) 3477 { 3478 si_reset_smc(rdev); 3479 si_stop_smc_clock(rdev); 3480 } 3481 3482 static int si_process_firmware_header(struct radeon_device *rdev) 3483 { 3484 struct si_power_info *si_pi = si_get_pi(rdev); 3485 u32 tmp; 3486 int ret; 3487 3488 ret = si_read_smc_sram_dword(rdev, 3489 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3490 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3491 &tmp, si_pi->sram_end); 3492 if (ret) 3493 return ret; 3494 3495 si_pi->state_table_start = tmp; 3496 3497 ret = si_read_smc_sram_dword(rdev, 3498 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3499 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3500 &tmp, si_pi->sram_end); 3501 if (ret) 3502 return ret; 3503 3504 si_pi->soft_regs_start = tmp; 3505 3506 ret = si_read_smc_sram_dword(rdev, 3507 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3508 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3509 &tmp, si_pi->sram_end); 3510 if (ret) 3511 return ret; 3512 3513 si_pi->mc_reg_table_start = tmp; 3514 3515 ret = si_read_smc_sram_dword(rdev, 3516 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3517 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3518 &tmp, si_pi->sram_end); 3519 if (ret) 3520 return ret; 3521 3522 si_pi->fan_table_start = tmp; 3523 3524 ret = si_read_smc_sram_dword(rdev, 3525 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3526 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3527 &tmp, si_pi->sram_end); 3528 if (ret) 3529 return ret; 3530 3531 si_pi->arb_table_start = tmp; 3532 3533 ret = si_read_smc_sram_dword(rdev, 3534 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3535 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3536 &tmp, si_pi->sram_end); 3537 if (ret) 3538 return ret; 3539 3540 si_pi->cac_table_start = tmp; 3541 3542 ret = si_read_smc_sram_dword(rdev, 3543 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3544 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3545 &tmp, si_pi->sram_end); 3546 if (ret) 3547 return ret; 3548 3549 si_pi->dte_table_start = tmp; 3550 3551 ret = si_read_smc_sram_dword(rdev, 3552 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3553 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3554 &tmp, si_pi->sram_end); 3555 if (ret) 3556 return ret; 3557 3558 si_pi->spll_table_start = tmp; 3559 3560 ret = si_read_smc_sram_dword(rdev, 3561 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3562 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3563 &tmp, si_pi->sram_end); 3564 if (ret) 3565 return ret; 3566 3567 si_pi->papm_cfg_table_start = tmp; 3568 3569 return ret; 3570 } 3571 3572 static void si_read_clock_registers(struct radeon_device *rdev) 3573 { 3574 struct si_power_info *si_pi = si_get_pi(rdev); 3575 3576 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3577 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3578 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3579 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3580 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3581 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3582 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3583 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3584 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3585 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3586 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3587 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3588 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3589 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3590 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3591 } 3592 3593 static void si_enable_thermal_protection(struct radeon_device *rdev, 3594 bool enable) 3595 { 3596 if (enable) 3597 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3598 else 3599 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3600 } 3601 3602 static void si_enable_acpi_power_management(struct radeon_device *rdev) 3603 { 3604 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3605 } 3606 3607 #if 0 3608 static int si_enter_ulp_state(struct radeon_device *rdev) 3609 { 3610 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3611 3612 udelay(25000); 3613 3614 return 0; 3615 } 3616 3617 static int si_exit_ulp_state(struct radeon_device *rdev) 3618 { 3619 int i; 3620 3621 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3622 3623 udelay(7000); 3624 3625 for (i = 0; i < rdev->usec_timeout; i++) { 3626 if (RREG32(SMC_RESP_0) == 1) 3627 break; 3628 udelay(1000); 3629 } 3630 3631 return 0; 3632 } 3633 #endif 3634 3635 static int si_notify_smc_display_change(struct radeon_device *rdev, 3636 bool has_display) 3637 { 3638 PPSMC_Msg msg = has_display ? 3639 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3640 3641 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3642 0 : -EINVAL; 3643 } 3644 3645 static void si_program_response_times(struct radeon_device *rdev) 3646 { 3647 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 3648 u32 vddc_dly, acpi_dly, vbi_dly; 3649 u32 reference_clock; 3650 3651 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3652 3653 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3654 3655 if (voltage_response_time == 0) 3656 voltage_response_time = 1000; 3657 3658 acpi_delay_time = 15000; 3659 vbi_time_out = 100000; 3660 3661 reference_clock = radeon_get_xclk(rdev); 3662 3663 vddc_dly = (voltage_response_time * reference_clock) / 100; 3664 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3665 vbi_dly = (vbi_time_out * reference_clock) / 100; 3666 3667 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3668 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3669 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3670 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3671 } 3672 3673 static void si_program_ds_registers(struct radeon_device *rdev) 3674 { 3675 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3676 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3677 3678 if (eg_pi->sclk_deep_sleep) { 3679 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3680 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3681 ~AUTOSCALE_ON_SS_CLEAR); 3682 } 3683 } 3684 3685 static void si_program_display_gap(struct radeon_device *rdev) 3686 { 3687 u32 tmp, pipe; 3688 int i; 3689 3690 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3691 if (rdev->pm.dpm.new_active_crtc_count > 0) 3692 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3693 else 3694 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3695 3696 if (rdev->pm.dpm.new_active_crtc_count > 1) 3697 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3698 else 3699 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3700 3701 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3702 3703 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3704 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3705 3706 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3707 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3708 /* find the first active crtc */ 3709 for (i = 0; i < rdev->num_crtc; i++) { 3710 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3711 break; 3712 } 3713 if (i == rdev->num_crtc) 3714 pipe = 0; 3715 else 3716 pipe = i; 3717 3718 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3719 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3720 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3721 } 3722 3723 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3724 * This can be a problem on PowerXpress systems or if you want to use the card 3725 * for offscreen rendering or compute if there are no crtcs enabled. 3726 */ 3727 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3728 } 3729 3730 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3731 { 3732 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3733 3734 if (enable) { 3735 if (pi->sclk_ss) 3736 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3737 } else { 3738 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3739 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3740 } 3741 } 3742 3743 static void si_setup_bsp(struct radeon_device *rdev) 3744 { 3745 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3746 u32 xclk = radeon_get_xclk(rdev); 3747 3748 r600_calculate_u_and_p(pi->asi, 3749 xclk, 3750 16, 3751 &pi->bsp, 3752 &pi->bsu); 3753 3754 r600_calculate_u_and_p(pi->pasi, 3755 xclk, 3756 16, 3757 &pi->pbsp, 3758 &pi->pbsu); 3759 3760 3761 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3762 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3763 3764 WREG32(CG_BSP, pi->dsp); 3765 } 3766 3767 static void si_program_git(struct radeon_device *rdev) 3768 { 3769 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3770 } 3771 3772 static void si_program_tp(struct radeon_device *rdev) 3773 { 3774 int i; 3775 enum r600_td td = R600_TD_DFLT; 3776 3777 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3778 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3779 3780 if (td == R600_TD_AUTO) 3781 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3782 else 3783 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3784 3785 if (td == R600_TD_UP) 3786 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3787 3788 if (td == R600_TD_DOWN) 3789 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3790 } 3791 3792 static void si_program_tpp(struct radeon_device *rdev) 3793 { 3794 WREG32(CG_TPC, R600_TPC_DFLT); 3795 } 3796 3797 static void si_program_sstp(struct radeon_device *rdev) 3798 { 3799 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3800 } 3801 3802 static void si_enable_display_gap(struct radeon_device *rdev) 3803 { 3804 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3805 3806 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3807 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3808 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3809 3810 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3811 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3812 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3813 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3814 } 3815 3816 static void si_program_vc(struct radeon_device *rdev) 3817 { 3818 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3819 3820 WREG32(CG_FTV, pi->vrc); 3821 } 3822 3823 static void si_clear_vc(struct radeon_device *rdev) 3824 { 3825 WREG32(CG_FTV, 0); 3826 } 3827 3828 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3829 { 3830 u8 mc_para_index; 3831 3832 if (memory_clock < 10000) 3833 mc_para_index = 0; 3834 else if (memory_clock >= 80000) 3835 mc_para_index = 0x0f; 3836 else 3837 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3838 return mc_para_index; 3839 } 3840 3841 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3842 { 3843 u8 mc_para_index; 3844 3845 if (strobe_mode) { 3846 if (memory_clock < 12500) 3847 mc_para_index = 0x00; 3848 else if (memory_clock > 47500) 3849 mc_para_index = 0x0f; 3850 else 3851 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3852 } else { 3853 if (memory_clock < 65000) 3854 mc_para_index = 0x00; 3855 else if (memory_clock > 135000) 3856 mc_para_index = 0x0f; 3857 else 3858 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3859 } 3860 return mc_para_index; 3861 } 3862 3863 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3864 { 3865 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3866 bool strobe_mode = false; 3867 u8 result = 0; 3868 3869 if (mclk <= pi->mclk_strobe_mode_threshold) 3870 strobe_mode = true; 3871 3872 if (pi->mem_gddr5) 3873 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3874 else 3875 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3876 3877 if (strobe_mode) 3878 result |= SISLANDS_SMC_STROBE_ENABLE; 3879 3880 return result; 3881 } 3882 3883 static int si_upload_firmware(struct radeon_device *rdev) 3884 { 3885 struct si_power_info *si_pi = si_get_pi(rdev); 3886 int ret; 3887 3888 si_reset_smc(rdev); 3889 si_stop_smc_clock(rdev); 3890 3891 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3892 3893 return ret; 3894 } 3895 3896 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3897 const struct atom_voltage_table *table, 3898 const struct radeon_phase_shedding_limits_table *limits) 3899 { 3900 u32 data, num_bits, num_levels; 3901 3902 if ((table == NULL) || (limits == NULL)) 3903 return false; 3904 3905 data = table->mask_low; 3906 3907 num_bits = hweight32(data); 3908 3909 if (num_bits == 0) 3910 return false; 3911 3912 num_levels = (1 << num_bits); 3913 3914 if (table->count != num_levels) 3915 return false; 3916 3917 if (limits->count != (num_levels - 1)) 3918 return false; 3919 3920 return true; 3921 } 3922 3923 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3924 u32 max_voltage_steps, 3925 struct atom_voltage_table *voltage_table) 3926 { 3927 unsigned int i, diff; 3928 3929 if (voltage_table->count <= max_voltage_steps) 3930 return; 3931 3932 diff = voltage_table->count - max_voltage_steps; 3933 3934 for (i= 0; i < max_voltage_steps; i++) 3935 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3936 3937 voltage_table->count = max_voltage_steps; 3938 } 3939 3940 static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3941 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3942 struct atom_voltage_table *voltage_table) 3943 { 3944 u32 i; 3945 3946 if (voltage_dependency_table == NULL) 3947 return -EINVAL; 3948 3949 voltage_table->mask_low = 0; 3950 voltage_table->phase_delay = 0; 3951 3952 voltage_table->count = voltage_dependency_table->count; 3953 for (i = 0; i < voltage_table->count; i++) { 3954 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3955 voltage_table->entries[i].smio_low = 0; 3956 } 3957 3958 return 0; 3959 } 3960 3961 static int si_construct_voltage_tables(struct radeon_device *rdev) 3962 { 3963 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3965 struct si_power_info *si_pi = si_get_pi(rdev); 3966 int ret; 3967 3968 if (pi->voltage_control) { 3969 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3970 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3971 if (ret) 3972 return ret; 3973 3974 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3975 si_trim_voltage_table_to_fit_state_table(rdev, 3976 SISLANDS_MAX_NO_VREG_STEPS, 3977 &eg_pi->vddc_voltage_table); 3978 } else if (si_pi->voltage_control_svi2) { 3979 ret = si_get_svi2_voltage_table(rdev, 3980 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3981 &eg_pi->vddc_voltage_table); 3982 if (ret) 3983 return ret; 3984 } else { 3985 return -EINVAL; 3986 } 3987 3988 if (eg_pi->vddci_control) { 3989 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3990 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3991 if (ret) 3992 return ret; 3993 3994 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3995 si_trim_voltage_table_to_fit_state_table(rdev, 3996 SISLANDS_MAX_NO_VREG_STEPS, 3997 &eg_pi->vddci_voltage_table); 3998 } 3999 if (si_pi->vddci_control_svi2) { 4000 ret = si_get_svi2_voltage_table(rdev, 4001 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4002 &eg_pi->vddci_voltage_table); 4003 if (ret) 4004 return ret; 4005 } 4006 4007 if (pi->mvdd_control) { 4008 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 4009 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4010 4011 if (ret) { 4012 pi->mvdd_control = false; 4013 return ret; 4014 } 4015 4016 if (si_pi->mvdd_voltage_table.count == 0) { 4017 pi->mvdd_control = false; 4018 return -EINVAL; 4019 } 4020 4021 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4022 si_trim_voltage_table_to_fit_state_table(rdev, 4023 SISLANDS_MAX_NO_VREG_STEPS, 4024 &si_pi->mvdd_voltage_table); 4025 } 4026 4027 if (si_pi->vddc_phase_shed_control) { 4028 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4029 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4030 if (ret) 4031 si_pi->vddc_phase_shed_control = false; 4032 4033 if ((si_pi->vddc_phase_shed_table.count == 0) || 4034 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4035 si_pi->vddc_phase_shed_control = false; 4036 } 4037 4038 return 0; 4039 } 4040 4041 static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4042 const struct atom_voltage_table *voltage_table, 4043 SISLANDS_SMC_STATETABLE *table) 4044 { 4045 unsigned int i; 4046 4047 for (i = 0; i < voltage_table->count; i++) 4048 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4049 } 4050 4051 static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4052 SISLANDS_SMC_STATETABLE *table) 4053 { 4054 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4055 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4056 struct si_power_info *si_pi = si_get_pi(rdev); 4057 u8 i; 4058 4059 if (si_pi->voltage_control_svi2) { 4060 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4061 si_pi->svc_gpio_id); 4062 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4063 si_pi->svd_gpio_id); 4064 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4065 2); 4066 } else { 4067 if (eg_pi->vddc_voltage_table.count) { 4068 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4069 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4070 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4071 4072 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4073 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4074 table->maxVDDCIndexInPPTable = i; 4075 break; 4076 } 4077 } 4078 } 4079 4080 if (eg_pi->vddci_voltage_table.count) { 4081 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4082 4083 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4084 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4085 } 4086 4087 4088 if (si_pi->mvdd_voltage_table.count) { 4089 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4090 4091 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4092 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4093 } 4094 4095 if (si_pi->vddc_phase_shed_control) { 4096 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4097 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4098 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4099 4100 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4101 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4102 4103 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4104 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4105 } else { 4106 si_pi->vddc_phase_shed_control = false; 4107 } 4108 } 4109 } 4110 4111 return 0; 4112 } 4113 4114 static int si_populate_voltage_value(struct radeon_device *rdev, 4115 const struct atom_voltage_table *table, 4116 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4117 { 4118 unsigned int i; 4119 4120 for (i = 0; i < table->count; i++) { 4121 if (value <= table->entries[i].value) { 4122 voltage->index = (u8)i; 4123 voltage->value = cpu_to_be16(table->entries[i].value); 4124 break; 4125 } 4126 } 4127 4128 if (i >= table->count) 4129 return -EINVAL; 4130 4131 return 0; 4132 } 4133 4134 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4135 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4136 { 4137 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4138 struct si_power_info *si_pi = si_get_pi(rdev); 4139 4140 if (pi->mvdd_control) { 4141 if (mclk <= pi->mvdd_split_frequency) 4142 voltage->index = 0; 4143 else 4144 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4145 4146 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4147 } 4148 return 0; 4149 } 4150 4151 static int si_get_std_voltage_value(struct radeon_device *rdev, 4152 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4153 u16 *std_voltage) 4154 { 4155 u16 v_index; 4156 bool voltage_found = false; 4157 *std_voltage = be16_to_cpu(voltage->value); 4158 4159 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4160 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4161 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4162 return -EINVAL; 4163 4164 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4165 if (be16_to_cpu(voltage->value) == 4166 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4167 voltage_found = true; 4168 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4169 *std_voltage = 4170 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4171 else 4172 *std_voltage = 4173 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4174 break; 4175 } 4176 } 4177 4178 if (!voltage_found) { 4179 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4180 if (be16_to_cpu(voltage->value) <= 4181 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4182 voltage_found = true; 4183 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4184 *std_voltage = 4185 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4186 else 4187 *std_voltage = 4188 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4189 break; 4190 } 4191 } 4192 } 4193 } else { 4194 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4195 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4196 } 4197 } 4198 4199 return 0; 4200 } 4201 4202 static int si_populate_std_voltage_value(struct radeon_device *rdev, 4203 u16 value, u8 index, 4204 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4205 { 4206 voltage->index = index; 4207 voltage->value = cpu_to_be16(value); 4208 4209 return 0; 4210 } 4211 4212 static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4213 const struct radeon_phase_shedding_limits_table *limits, 4214 u16 voltage, u32 sclk, u32 mclk, 4215 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4216 { 4217 unsigned int i; 4218 4219 for (i = 0; i < limits->count; i++) { 4220 if ((voltage <= limits->entries[i].voltage) && 4221 (sclk <= limits->entries[i].sclk) && 4222 (mclk <= limits->entries[i].mclk)) 4223 break; 4224 } 4225 4226 smc_voltage->phase_settings = (u8)i; 4227 4228 return 0; 4229 } 4230 4231 static int si_init_arb_table_index(struct radeon_device *rdev) 4232 { 4233 struct si_power_info *si_pi = si_get_pi(rdev); 4234 u32 tmp; 4235 int ret; 4236 4237 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4238 if (ret) 4239 return ret; 4240 4241 tmp &= 0x00FFFFFF; 4242 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4243 4244 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4245 } 4246 4247 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4248 { 4249 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4250 } 4251 4252 static int si_reset_to_default(struct radeon_device *rdev) 4253 { 4254 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4255 0 : -EINVAL; 4256 } 4257 4258 static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4259 { 4260 struct si_power_info *si_pi = si_get_pi(rdev); 4261 u32 tmp; 4262 int ret; 4263 4264 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4265 &tmp, si_pi->sram_end); 4266 if (ret) 4267 return ret; 4268 4269 tmp = (tmp >> 24) & 0xff; 4270 4271 if (tmp == MC_CG_ARB_FREQ_F0) 4272 return 0; 4273 4274 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4275 } 4276 4277 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4278 u32 engine_clock) 4279 { 4280 u32 dram_rows; 4281 u32 dram_refresh_rate; 4282 u32 mc_arb_rfsh_rate; 4283 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4284 4285 if (tmp >= 4) 4286 dram_rows = 16384; 4287 else 4288 dram_rows = 1 << (tmp + 10); 4289 4290 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4291 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4292 4293 return mc_arb_rfsh_rate; 4294 } 4295 4296 static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4297 struct rv7xx_pl *pl, 4298 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4299 { 4300 u32 dram_timing; 4301 u32 dram_timing2; 4302 u32 burst_time; 4303 4304 arb_regs->mc_arb_rfsh_rate = 4305 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4306 4307 radeon_atom_set_engine_dram_timings(rdev, 4308 pl->sclk, 4309 pl->mclk); 4310 4311 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4312 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4313 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4314 4315 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4316 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4317 arb_regs->mc_arb_burst_time = (u8)burst_time; 4318 4319 return 0; 4320 } 4321 4322 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4323 struct radeon_ps *radeon_state, 4324 unsigned int first_arb_set) 4325 { 4326 struct si_power_info *si_pi = si_get_pi(rdev); 4327 struct ni_ps *state = ni_get_ps(radeon_state); 4328 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4329 int i, ret = 0; 4330 4331 for (i = 0; i < state->performance_level_count; i++) { 4332 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4333 if (ret) 4334 break; 4335 ret = si_copy_bytes_to_smc(rdev, 4336 si_pi->arb_table_start + 4337 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4338 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4339 (u8 *)&arb_regs, 4340 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4341 si_pi->sram_end); 4342 if (ret) 4343 break; 4344 } 4345 4346 return ret; 4347 } 4348 4349 static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4350 struct radeon_ps *radeon_new_state) 4351 { 4352 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4353 SISLANDS_DRIVER_STATE_ARB_INDEX); 4354 } 4355 4356 static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4357 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4358 { 4359 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4360 struct si_power_info *si_pi = si_get_pi(rdev); 4361 4362 if (pi->mvdd_control) 4363 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4364 si_pi->mvdd_bootup_value, voltage); 4365 4366 return 0; 4367 } 4368 4369 static int si_populate_smc_initial_state(struct radeon_device *rdev, 4370 struct radeon_ps *radeon_initial_state, 4371 SISLANDS_SMC_STATETABLE *table) 4372 { 4373 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4374 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4375 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4376 struct si_power_info *si_pi = si_get_pi(rdev); 4377 u32 reg; 4378 int ret; 4379 4380 table->initialState.levels[0].mclk.vDLL_CNTL = 4381 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4382 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4383 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4384 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4385 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4386 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4387 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4388 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4389 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4390 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4391 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4392 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4393 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4394 table->initialState.levels[0].mclk.vMPLL_SS = 4395 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4396 table->initialState.levels[0].mclk.vMPLL_SS2 = 4397 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4398 4399 table->initialState.levels[0].mclk.mclk_value = 4400 cpu_to_be32(initial_state->performance_levels[0].mclk); 4401 4402 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4403 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4404 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4405 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4406 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4407 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4408 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4409 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4410 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4411 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4412 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4413 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4414 4415 table->initialState.levels[0].sclk.sclk_value = 4416 cpu_to_be32(initial_state->performance_levels[0].sclk); 4417 4418 table->initialState.levels[0].arbRefreshState = 4419 SISLANDS_INITIAL_STATE_ARB_INDEX; 4420 4421 table->initialState.levels[0].ACIndex = 0; 4422 4423 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4424 initial_state->performance_levels[0].vddc, 4425 &table->initialState.levels[0].vddc); 4426 4427 if (!ret) { 4428 u16 std_vddc; 4429 4430 ret = si_get_std_voltage_value(rdev, 4431 &table->initialState.levels[0].vddc, 4432 &std_vddc); 4433 if (!ret) 4434 si_populate_std_voltage_value(rdev, std_vddc, 4435 table->initialState.levels[0].vddc.index, 4436 &table->initialState.levels[0].std_vddc); 4437 } 4438 4439 if (eg_pi->vddci_control) 4440 si_populate_voltage_value(rdev, 4441 &eg_pi->vddci_voltage_table, 4442 initial_state->performance_levels[0].vddci, 4443 &table->initialState.levels[0].vddci); 4444 4445 if (si_pi->vddc_phase_shed_control) 4446 si_populate_phase_shedding_value(rdev, 4447 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4448 initial_state->performance_levels[0].vddc, 4449 initial_state->performance_levels[0].sclk, 4450 initial_state->performance_levels[0].mclk, 4451 &table->initialState.levels[0].vddc); 4452 4453 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4454 4455 reg = CG_R(0xffff) | CG_L(0); 4456 table->initialState.levels[0].aT = cpu_to_be32(reg); 4457 4458 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4459 4460 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4461 4462 if (pi->mem_gddr5) { 4463 table->initialState.levels[0].strobeMode = 4464 si_get_strobe_mode_settings(rdev, 4465 initial_state->performance_levels[0].mclk); 4466 4467 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4468 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4469 else 4470 table->initialState.levels[0].mcFlags = 0; 4471 } 4472 4473 table->initialState.levelCount = 1; 4474 4475 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4476 4477 table->initialState.levels[0].dpm2.MaxPS = 0; 4478 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4479 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4480 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4481 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4482 4483 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4484 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4485 4486 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4487 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4488 4489 return 0; 4490 } 4491 4492 static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4493 SISLANDS_SMC_STATETABLE *table) 4494 { 4495 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4496 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4497 struct si_power_info *si_pi = si_get_pi(rdev); 4498 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4499 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4500 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4501 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4502 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4503 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4504 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4505 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4506 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4507 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4508 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4509 u32 reg; 4510 int ret; 4511 4512 table->ACPIState = table->initialState; 4513 4514 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4515 4516 if (pi->acpi_vddc) { 4517 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4518 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4519 if (!ret) { 4520 u16 std_vddc; 4521 4522 ret = si_get_std_voltage_value(rdev, 4523 &table->ACPIState.levels[0].vddc, &std_vddc); 4524 if (!ret) 4525 si_populate_std_voltage_value(rdev, std_vddc, 4526 table->ACPIState.levels[0].vddc.index, 4527 &table->ACPIState.levels[0].std_vddc); 4528 } 4529 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4530 4531 if (si_pi->vddc_phase_shed_control) { 4532 si_populate_phase_shedding_value(rdev, 4533 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4534 pi->acpi_vddc, 4535 0, 4536 0, 4537 &table->ACPIState.levels[0].vddc); 4538 } 4539 } else { 4540 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4541 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4542 if (!ret) { 4543 u16 std_vddc; 4544 4545 ret = si_get_std_voltage_value(rdev, 4546 &table->ACPIState.levels[0].vddc, &std_vddc); 4547 4548 if (!ret) 4549 si_populate_std_voltage_value(rdev, std_vddc, 4550 table->ACPIState.levels[0].vddc.index, 4551 &table->ACPIState.levels[0].std_vddc); 4552 } 4553 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4554 si_pi->sys_pcie_mask, 4555 si_pi->boot_pcie_gen, 4556 RADEON_PCIE_GEN1); 4557 4558 if (si_pi->vddc_phase_shed_control) 4559 si_populate_phase_shedding_value(rdev, 4560 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4561 pi->min_vddc_in_table, 4562 0, 4563 0, 4564 &table->ACPIState.levels[0].vddc); 4565 } 4566 4567 if (pi->acpi_vddc) { 4568 if (eg_pi->acpi_vddci) 4569 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4570 eg_pi->acpi_vddci, 4571 &table->ACPIState.levels[0].vddci); 4572 } 4573 4574 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4575 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4576 4577 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4578 4579 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4580 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4581 4582 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4583 cpu_to_be32(dll_cntl); 4584 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4585 cpu_to_be32(mclk_pwrmgt_cntl); 4586 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4587 cpu_to_be32(mpll_ad_func_cntl); 4588 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4589 cpu_to_be32(mpll_dq_func_cntl); 4590 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4591 cpu_to_be32(mpll_func_cntl); 4592 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4593 cpu_to_be32(mpll_func_cntl_1); 4594 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4595 cpu_to_be32(mpll_func_cntl_2); 4596 table->ACPIState.levels[0].mclk.vMPLL_SS = 4597 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4598 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4599 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4600 4601 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4602 cpu_to_be32(spll_func_cntl); 4603 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4604 cpu_to_be32(spll_func_cntl_2); 4605 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4606 cpu_to_be32(spll_func_cntl_3); 4607 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4608 cpu_to_be32(spll_func_cntl_4); 4609 4610 table->ACPIState.levels[0].mclk.mclk_value = 0; 4611 table->ACPIState.levels[0].sclk.sclk_value = 0; 4612 4613 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4614 4615 if (eg_pi->dynamic_ac_timing) 4616 table->ACPIState.levels[0].ACIndex = 0; 4617 4618 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4619 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4620 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4621 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4622 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4623 4624 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4625 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4626 4627 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4628 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4629 4630 return 0; 4631 } 4632 4633 static int si_populate_ulv_state(struct radeon_device *rdev, 4634 SISLANDS_SMC_SWSTATE *state) 4635 { 4636 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4637 struct si_power_info *si_pi = si_get_pi(rdev); 4638 struct si_ulv_param *ulv = &si_pi->ulv; 4639 u32 sclk_in_sr = 1350; /* ??? */ 4640 int ret; 4641 4642 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4643 &state->levels[0]); 4644 if (!ret) { 4645 if (eg_pi->sclk_deep_sleep) { 4646 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4647 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4648 else 4649 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4650 } 4651 if (ulv->one_pcie_lane_in_ulv) 4652 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4653 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4654 state->levels[0].ACIndex = 1; 4655 state->levels[0].std_vddc = state->levels[0].vddc; 4656 state->levelCount = 1; 4657 4658 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4659 } 4660 4661 return ret; 4662 } 4663 4664 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4665 { 4666 struct si_power_info *si_pi = si_get_pi(rdev); 4667 struct si_ulv_param *ulv = &si_pi->ulv; 4668 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4669 int ret; 4670 4671 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4672 &arb_regs); 4673 if (ret) 4674 return ret; 4675 4676 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4677 ulv->volt_change_delay); 4678 4679 ret = si_copy_bytes_to_smc(rdev, 4680 si_pi->arb_table_start + 4681 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4682 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4683 (u8 *)&arb_regs, 4684 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4685 si_pi->sram_end); 4686 4687 return ret; 4688 } 4689 4690 static void si_get_mvdd_configuration(struct radeon_device *rdev) 4691 { 4692 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4693 4694 pi->mvdd_split_frequency = 30000; 4695 } 4696 4697 static int si_init_smc_table(struct radeon_device *rdev) 4698 { 4699 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4700 struct si_power_info *si_pi = si_get_pi(rdev); 4701 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4702 const struct si_ulv_param *ulv = &si_pi->ulv; 4703 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4704 int ret; 4705 u32 lane_width; 4706 u32 vr_hot_gpio; 4707 4708 si_populate_smc_voltage_tables(rdev, table); 4709 4710 switch (rdev->pm.int_thermal_type) { 4711 case THERMAL_TYPE_SI: 4712 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4713 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4714 break; 4715 case THERMAL_TYPE_NONE: 4716 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4717 break; 4718 default: 4719 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4720 break; 4721 } 4722 4723 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4724 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4725 4726 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4727 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4728 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4729 } 4730 4731 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4732 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4733 4734 if (pi->mem_gddr5) 4735 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4736 4737 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4738 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4739 4740 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4741 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4742 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4743 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4744 vr_hot_gpio); 4745 } 4746 4747 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4748 if (ret) 4749 return ret; 4750 4751 ret = si_populate_smc_acpi_state(rdev, table); 4752 if (ret) 4753 return ret; 4754 4755 table->driverState = table->initialState; 4756 4757 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4758 SISLANDS_INITIAL_STATE_ARB_INDEX); 4759 if (ret) 4760 return ret; 4761 4762 if (ulv->supported && ulv->pl.vddc) { 4763 ret = si_populate_ulv_state(rdev, &table->ULVState); 4764 if (ret) 4765 return ret; 4766 4767 ret = si_program_ulv_memory_timing_parameters(rdev); 4768 if (ret) 4769 return ret; 4770 4771 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4772 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4773 4774 lane_width = radeon_get_pcie_lanes(rdev); 4775 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4776 } else { 4777 table->ULVState = table->initialState; 4778 } 4779 4780 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4781 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4782 si_pi->sram_end); 4783 } 4784 4785 static int si_calculate_sclk_params(struct radeon_device *rdev, 4786 u32 engine_clock, 4787 SISLANDS_SMC_SCLK_VALUE *sclk) 4788 { 4789 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4790 struct si_power_info *si_pi = si_get_pi(rdev); 4791 struct atom_clock_dividers dividers; 4792 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4793 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4794 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4795 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4796 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4797 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4798 u64 tmp; 4799 u32 reference_clock = rdev->clock.spll.reference_freq; 4800 u32 reference_divider; 4801 u32 fbdiv; 4802 int ret; 4803 4804 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4805 engine_clock, false, ÷rs); 4806 if (ret) 4807 return ret; 4808 4809 reference_divider = 1 + dividers.ref_div; 4810 4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4812 do_div(tmp, reference_clock); 4813 fbdiv = (u32) tmp; 4814 4815 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4816 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4817 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4818 4819 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4820 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4821 4822 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4823 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4824 spll_func_cntl_3 |= SPLL_DITHEN; 4825 4826 if (pi->sclk_ss) { 4827 struct radeon_atom_ss ss; 4828 u32 vco_freq = engine_clock * dividers.post_div; 4829 4830 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4831 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4833 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4834 4835 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4836 cg_spll_spread_spectrum |= CLK_S(clk_s); 4837 cg_spll_spread_spectrum |= SSEN; 4838 4839 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4840 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4841 } 4842 } 4843 4844 sclk->sclk_value = engine_clock; 4845 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4846 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4847 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4848 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4849 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4850 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4851 4852 return 0; 4853 } 4854 4855 static int si_populate_sclk_value(struct radeon_device *rdev, 4856 u32 engine_clock, 4857 SISLANDS_SMC_SCLK_VALUE *sclk) 4858 { 4859 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4860 int ret; 4861 4862 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4863 if (!ret) { 4864 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4865 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4866 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4867 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4868 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4869 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4870 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4871 } 4872 4873 return ret; 4874 } 4875 4876 static int si_populate_mclk_value(struct radeon_device *rdev, 4877 u32 engine_clock, 4878 u32 memory_clock, 4879 SISLANDS_SMC_MCLK_VALUE *mclk, 4880 bool strobe_mode, 4881 bool dll_state_on) 4882 { 4883 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4884 struct si_power_info *si_pi = si_get_pi(rdev); 4885 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4886 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4887 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4888 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4889 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4890 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4891 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4892 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4893 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4894 struct atom_mpll_param mpll_param; 4895 int ret; 4896 4897 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4898 if (ret) 4899 return ret; 4900 4901 mpll_func_cntl &= ~BWCTRL_MASK; 4902 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4903 4904 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4905 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4906 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4907 4908 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4909 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4910 4911 if (pi->mem_gddr5) { 4912 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4913 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4914 YCLK_POST_DIV(mpll_param.post_div); 4915 } 4916 4917 if (pi->mclk_ss) { 4918 struct radeon_atom_ss ss; 4919 u32 freq_nom; 4920 u32 tmp; 4921 u32 reference_clock = rdev->clock.mpll.reference_freq; 4922 4923 if (pi->mem_gddr5) 4924 freq_nom = memory_clock * 4; 4925 else 4926 freq_nom = memory_clock * 2; 4927 4928 tmp = freq_nom / reference_clock; 4929 tmp = tmp * tmp; 4930 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4931 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4932 u32 clks = reference_clock * 5 / ss.rate; 4933 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4934 4935 mpll_ss1 &= ~CLKV_MASK; 4936 mpll_ss1 |= CLKV(clkv); 4937 4938 mpll_ss2 &= ~CLKS_MASK; 4939 mpll_ss2 |= CLKS(clks); 4940 } 4941 } 4942 4943 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4944 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4945 4946 if (dll_state_on) 4947 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4948 else 4949 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4950 4951 mclk->mclk_value = cpu_to_be32(memory_clock); 4952 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4953 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4954 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4955 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4956 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4957 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4958 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4959 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4960 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4961 4962 return 0; 4963 } 4964 4965 static void si_populate_smc_sp(struct radeon_device *rdev, 4966 struct radeon_ps *radeon_state, 4967 SISLANDS_SMC_SWSTATE *smc_state) 4968 { 4969 struct ni_ps *ps = ni_get_ps(radeon_state); 4970 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4971 int i; 4972 4973 for (i = 0; i < ps->performance_level_count - 1; i++) 4974 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4975 4976 smc_state->levels[ps->performance_level_count - 1].bSP = 4977 cpu_to_be32(pi->psp); 4978 } 4979 4980 static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4981 struct rv7xx_pl *pl, 4982 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4983 { 4984 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4985 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4986 struct si_power_info *si_pi = si_get_pi(rdev); 4987 int ret; 4988 bool dll_state_on; 4989 u16 std_vddc; 4990 bool gmc_pg = false; 4991 4992 if (eg_pi->pcie_performance_request && 4993 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4994 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4995 else 4996 level->gen2PCIE = (u8)pl->pcie_gen; 4997 4998 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4999 if (ret) 5000 return ret; 5001 5002 level->mcFlags = 0; 5003 5004 if (pi->mclk_stutter_mode_threshold && 5005 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5006 !eg_pi->uvd_enabled && 5007 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5008 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 5009 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5010 5011 if (gmc_pg) 5012 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5013 } 5014 5015 if (pi->mem_gddr5) { 5016 if (pl->mclk > pi->mclk_edc_enable_threshold) 5017 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5018 5019 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5020 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5021 5022 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5023 5024 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5025 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5026 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5027 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5028 else 5029 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5030 } else { 5031 dll_state_on = false; 5032 } 5033 } else { 5034 level->strobeMode = si_get_strobe_mode_settings(rdev, 5035 pl->mclk); 5036 5037 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5038 } 5039 5040 ret = si_populate_mclk_value(rdev, 5041 pl->sclk, 5042 pl->mclk, 5043 &level->mclk, 5044 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5045 if (ret) 5046 return ret; 5047 5048 ret = si_populate_voltage_value(rdev, 5049 &eg_pi->vddc_voltage_table, 5050 pl->vddc, &level->vddc); 5051 if (ret) 5052 return ret; 5053 5054 5055 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5056 if (ret) 5057 return ret; 5058 5059 ret = si_populate_std_voltage_value(rdev, std_vddc, 5060 level->vddc.index, &level->std_vddc); 5061 if (ret) 5062 return ret; 5063 5064 if (eg_pi->vddci_control) { 5065 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5066 pl->vddci, &level->vddci); 5067 if (ret) 5068 return ret; 5069 } 5070 5071 if (si_pi->vddc_phase_shed_control) { 5072 ret = si_populate_phase_shedding_value(rdev, 5073 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5074 pl->vddc, 5075 pl->sclk, 5076 pl->mclk, 5077 &level->vddc); 5078 if (ret) 5079 return ret; 5080 } 5081 5082 level->MaxPoweredUpCU = si_pi->max_cu; 5083 5084 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5085 5086 return ret; 5087 } 5088 5089 static int si_populate_smc_t(struct radeon_device *rdev, 5090 struct radeon_ps *radeon_state, 5091 SISLANDS_SMC_SWSTATE *smc_state) 5092 { 5093 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5094 struct ni_ps *state = ni_get_ps(radeon_state); 5095 u32 a_t; 5096 u32 t_l, t_h; 5097 u32 high_bsp; 5098 int i, ret; 5099 5100 if (state->performance_level_count >= 9) 5101 return -EINVAL; 5102 5103 if (state->performance_level_count < 2) { 5104 a_t = CG_R(0xffff) | CG_L(0); 5105 smc_state->levels[0].aT = cpu_to_be32(a_t); 5106 return 0; 5107 } 5108 5109 smc_state->levels[0].aT = cpu_to_be32(0); 5110 5111 for (i = 0; i <= state->performance_level_count - 2; i++) { 5112 ret = r600_calculate_at( 5113 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5114 100 * R600_AH_DFLT, 5115 state->performance_levels[i + 1].sclk, 5116 state->performance_levels[i].sclk, 5117 &t_l, 5118 &t_h); 5119 5120 if (ret) { 5121 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5122 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5123 } 5124 5125 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5126 a_t |= CG_R(t_l * pi->bsp / 20000); 5127 smc_state->levels[i].aT = cpu_to_be32(a_t); 5128 5129 high_bsp = (i == state->performance_level_count - 2) ? 5130 pi->pbsp : pi->bsp; 5131 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5132 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5133 } 5134 5135 return 0; 5136 } 5137 5138 static int si_disable_ulv(struct radeon_device *rdev) 5139 { 5140 struct si_power_info *si_pi = si_get_pi(rdev); 5141 struct si_ulv_param *ulv = &si_pi->ulv; 5142 5143 if (ulv->supported) 5144 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5145 0 : -EINVAL; 5146 5147 return 0; 5148 } 5149 5150 static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5151 struct radeon_ps *radeon_state) 5152 { 5153 const struct si_power_info *si_pi = si_get_pi(rdev); 5154 const struct si_ulv_param *ulv = &si_pi->ulv; 5155 const struct ni_ps *state = ni_get_ps(radeon_state); 5156 int i; 5157 5158 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5159 return false; 5160 5161 /* XXX validate against display requirements! */ 5162 5163 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5164 if (rdev->clock.current_dispclk <= 5165 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5166 if (ulv->pl.vddc < 5167 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5168 return false; 5169 } 5170 } 5171 5172 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5173 return false; 5174 5175 return true; 5176 } 5177 5178 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5179 struct radeon_ps *radeon_new_state) 5180 { 5181 const struct si_power_info *si_pi = si_get_pi(rdev); 5182 const struct si_ulv_param *ulv = &si_pi->ulv; 5183 5184 if (ulv->supported) { 5185 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5186 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5187 0 : -EINVAL; 5188 } 5189 return 0; 5190 } 5191 5192 static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5193 struct radeon_ps *radeon_state, 5194 SISLANDS_SMC_SWSTATE *smc_state) 5195 { 5196 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5197 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5198 struct si_power_info *si_pi = si_get_pi(rdev); 5199 struct ni_ps *state = ni_get_ps(radeon_state); 5200 int i, ret; 5201 u32 threshold; 5202 u32 sclk_in_sr = 1350; /* ??? */ 5203 5204 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5205 return -EINVAL; 5206 5207 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5208 5209 if (radeon_state->vclk && radeon_state->dclk) { 5210 eg_pi->uvd_enabled = true; 5211 if (eg_pi->smu_uvd_hs) 5212 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5213 } else { 5214 eg_pi->uvd_enabled = false; 5215 } 5216 5217 if (state->dc_compatible) 5218 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5219 5220 smc_state->levelCount = 0; 5221 for (i = 0; i < state->performance_level_count; i++) { 5222 if (eg_pi->sclk_deep_sleep) { 5223 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5224 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5225 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5226 else 5227 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5228 } 5229 } 5230 5231 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5232 &smc_state->levels[i]); 5233 smc_state->levels[i].arbRefreshState = 5234 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5235 5236 if (ret) 5237 return ret; 5238 5239 if (ni_pi->enable_power_containment) 5240 smc_state->levels[i].displayWatermark = 5241 (state->performance_levels[i].sclk < threshold) ? 5242 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5243 else 5244 smc_state->levels[i].displayWatermark = (i < 2) ? 5245 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5246 5247 if (eg_pi->dynamic_ac_timing) 5248 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5249 else 5250 smc_state->levels[i].ACIndex = 0; 5251 5252 smc_state->levelCount++; 5253 } 5254 5255 si_write_smc_soft_register(rdev, 5256 SI_SMC_SOFT_REGISTER_watermark_threshold, 5257 threshold / 512); 5258 5259 si_populate_smc_sp(rdev, radeon_state, smc_state); 5260 5261 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5262 if (ret) 5263 ni_pi->enable_power_containment = false; 5264 5265 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5266 if (ret) 5267 ni_pi->enable_sq_ramping = false; 5268 5269 return si_populate_smc_t(rdev, radeon_state, smc_state); 5270 } 5271 5272 static int si_upload_sw_state(struct radeon_device *rdev, 5273 struct radeon_ps *radeon_new_state) 5274 { 5275 struct si_power_info *si_pi = si_get_pi(rdev); 5276 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5277 int ret; 5278 u32 address = si_pi->state_table_start + 5279 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5280 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5281 ((new_state->performance_level_count - 1) * 5282 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5283 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5284 5285 memset(smc_state, 0, state_size); 5286 5287 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5288 if (ret) 5289 return ret; 5290 5291 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5292 state_size, si_pi->sram_end); 5293 5294 return ret; 5295 } 5296 5297 static int si_upload_ulv_state(struct radeon_device *rdev) 5298 { 5299 struct si_power_info *si_pi = si_get_pi(rdev); 5300 struct si_ulv_param *ulv = &si_pi->ulv; 5301 int ret = 0; 5302 5303 if (ulv->supported && ulv->pl.vddc) { 5304 u32 address = si_pi->state_table_start + 5305 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5306 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5307 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5308 5309 memset(smc_state, 0, state_size); 5310 5311 ret = si_populate_ulv_state(rdev, smc_state); 5312 if (!ret) 5313 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5314 state_size, si_pi->sram_end); 5315 } 5316 5317 return ret; 5318 } 5319 5320 static int si_upload_smc_data(struct radeon_device *rdev) 5321 { 5322 struct radeon_crtc *radeon_crtc = NULL; 5323 int i; 5324 5325 if (rdev->pm.dpm.new_active_crtc_count == 0) 5326 return 0; 5327 5328 for (i = 0; i < rdev->num_crtc; i++) { 5329 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5330 radeon_crtc = rdev->mode_info.crtcs[i]; 5331 break; 5332 } 5333 } 5334 5335 if (radeon_crtc == NULL) 5336 return 0; 5337 5338 if (radeon_crtc->line_time <= 0) 5339 return 0; 5340 5341 if (si_write_smc_soft_register(rdev, 5342 SI_SMC_SOFT_REGISTER_crtc_index, 5343 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5344 return 0; 5345 5346 if (si_write_smc_soft_register(rdev, 5347 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5348 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5349 return 0; 5350 5351 if (si_write_smc_soft_register(rdev, 5352 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5353 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5354 return 0; 5355 5356 return 0; 5357 } 5358 5359 static int si_set_mc_special_registers(struct radeon_device *rdev, 5360 struct si_mc_reg_table *table) 5361 { 5362 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5363 u8 i, j, k; 5364 u32 temp_reg; 5365 5366 for (i = 0, j = table->last; i < table->last; i++) { 5367 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5368 return -EINVAL; 5369 switch (table->mc_reg_address[i].s1 << 2) { 5370 case MC_SEQ_MISC1: 5371 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5372 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5373 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5374 for (k = 0; k < table->num_entries; k++) 5375 table->mc_reg_table_entry[k].mc_data[j] = 5376 ((temp_reg & 0xffff0000)) | 5377 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5378 j++; 5379 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5380 return -EINVAL; 5381 5382 temp_reg = RREG32(MC_PMG_CMD_MRS); 5383 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5384 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5385 for (k = 0; k < table->num_entries; k++) { 5386 table->mc_reg_table_entry[k].mc_data[j] = 5387 (temp_reg & 0xffff0000) | 5388 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5389 if (!pi->mem_gddr5) 5390 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5391 } 5392 j++; 5393 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5394 return -EINVAL; 5395 5396 if (!pi->mem_gddr5) { 5397 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5398 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5399 for (k = 0; k < table->num_entries; k++) 5400 table->mc_reg_table_entry[k].mc_data[j] = 5401 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5402 j++; 5403 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5404 return -EINVAL; 5405 } 5406 break; 5407 case MC_SEQ_RESERVE_M: 5408 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5409 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5410 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5411 for(k = 0; k < table->num_entries; k++) 5412 table->mc_reg_table_entry[k].mc_data[j] = 5413 (temp_reg & 0xffff0000) | 5414 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5415 j++; 5416 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5417 return -EINVAL; 5418 break; 5419 default: 5420 break; 5421 } 5422 } 5423 5424 table->last = j; 5425 5426 return 0; 5427 } 5428 5429 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5430 { 5431 bool result = true; 5432 5433 switch (in_reg) { 5434 case MC_SEQ_RAS_TIMING >> 2: 5435 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5436 break; 5437 case MC_SEQ_CAS_TIMING >> 2: 5438 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5439 break; 5440 case MC_SEQ_MISC_TIMING >> 2: 5441 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5442 break; 5443 case MC_SEQ_MISC_TIMING2 >> 2: 5444 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5445 break; 5446 case MC_SEQ_RD_CTL_D0 >> 2: 5447 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5448 break; 5449 case MC_SEQ_RD_CTL_D1 >> 2: 5450 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5451 break; 5452 case MC_SEQ_WR_CTL_D0 >> 2: 5453 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5454 break; 5455 case MC_SEQ_WR_CTL_D1 >> 2: 5456 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5457 break; 5458 case MC_PMG_CMD_EMRS >> 2: 5459 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5460 break; 5461 case MC_PMG_CMD_MRS >> 2: 5462 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5463 break; 5464 case MC_PMG_CMD_MRS1 >> 2: 5465 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5466 break; 5467 case MC_SEQ_PMG_TIMING >> 2: 5468 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5469 break; 5470 case MC_PMG_CMD_MRS2 >> 2: 5471 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5472 break; 5473 case MC_SEQ_WR_CTL_2 >> 2: 5474 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5475 break; 5476 default: 5477 result = false; 5478 break; 5479 } 5480 5481 return result; 5482 } 5483 5484 static void si_set_valid_flag(struct si_mc_reg_table *table) 5485 { 5486 u8 i, j; 5487 5488 for (i = 0; i < table->last; i++) { 5489 for (j = 1; j < table->num_entries; j++) { 5490 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5491 table->valid_flag |= 1 << i; 5492 break; 5493 } 5494 } 5495 } 5496 } 5497 5498 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5499 { 5500 u32 i; 5501 u16 address; 5502 5503 for (i = 0; i < table->last; i++) 5504 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5505 address : table->mc_reg_address[i].s1; 5506 5507 } 5508 5509 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5510 struct si_mc_reg_table *si_table) 5511 { 5512 u8 i, j; 5513 5514 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5515 return -EINVAL; 5516 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5517 return -EINVAL; 5518 5519 for (i = 0; i < table->last; i++) 5520 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5521 si_table->last = table->last; 5522 5523 for (i = 0; i < table->num_entries; i++) { 5524 si_table->mc_reg_table_entry[i].mclk_max = 5525 table->mc_reg_table_entry[i].mclk_max; 5526 for (j = 0; j < table->last; j++) { 5527 si_table->mc_reg_table_entry[i].mc_data[j] = 5528 table->mc_reg_table_entry[i].mc_data[j]; 5529 } 5530 } 5531 si_table->num_entries = table->num_entries; 5532 5533 return 0; 5534 } 5535 5536 static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5537 { 5538 struct si_power_info *si_pi = si_get_pi(rdev); 5539 struct atom_mc_reg_table *table; 5540 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5541 u8 module_index = rv770_get_memory_module_index(rdev); 5542 int ret; 5543 5544 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5545 if (!table) 5546 return -ENOMEM; 5547 5548 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5549 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5550 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5551 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5552 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5553 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5554 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5555 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5556 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5557 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5558 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5559 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5560 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5561 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5562 5563 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5564 if (ret) 5565 goto init_mc_done; 5566 5567 ret = si_copy_vbios_mc_reg_table(table, si_table); 5568 if (ret) 5569 goto init_mc_done; 5570 5571 si_set_s0_mc_reg_index(si_table); 5572 5573 ret = si_set_mc_special_registers(rdev, si_table); 5574 if (ret) 5575 goto init_mc_done; 5576 5577 si_set_valid_flag(si_table); 5578 5579 init_mc_done: 5580 kfree(table); 5581 5582 return ret; 5583 5584 } 5585 5586 static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5587 SMC_SIslands_MCRegisters *mc_reg_table) 5588 { 5589 struct si_power_info *si_pi = si_get_pi(rdev); 5590 u32 i, j; 5591 5592 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5593 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5594 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5595 break; 5596 mc_reg_table->address[i].s0 = 5597 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5598 mc_reg_table->address[i].s1 = 5599 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5600 i++; 5601 } 5602 } 5603 mc_reg_table->last = (u8)i; 5604 } 5605 5606 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5607 SMC_SIslands_MCRegisterSet *data, 5608 u32 num_entries, u32 valid_flag) 5609 { 5610 u32 i, j; 5611 5612 for(i = 0, j = 0; j < num_entries; j++) { 5613 if (valid_flag & (1 << j)) { 5614 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5615 i++; 5616 } 5617 } 5618 } 5619 5620 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5621 struct rv7xx_pl *pl, 5622 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5623 { 5624 struct si_power_info *si_pi = si_get_pi(rdev); 5625 u32 i = 0; 5626 5627 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5628 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5629 break; 5630 } 5631 5632 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5633 --i; 5634 5635 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5636 mc_reg_table_data, si_pi->mc_reg_table.last, 5637 si_pi->mc_reg_table.valid_flag); 5638 } 5639 5640 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5641 struct radeon_ps *radeon_state, 5642 SMC_SIslands_MCRegisters *mc_reg_table) 5643 { 5644 struct ni_ps *state = ni_get_ps(radeon_state); 5645 int i; 5646 5647 for (i = 0; i < state->performance_level_count; i++) { 5648 si_convert_mc_reg_table_entry_to_smc(rdev, 5649 &state->performance_levels[i], 5650 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5651 } 5652 } 5653 5654 static int si_populate_mc_reg_table(struct radeon_device *rdev, 5655 struct radeon_ps *radeon_boot_state) 5656 { 5657 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5658 struct si_power_info *si_pi = si_get_pi(rdev); 5659 struct si_ulv_param *ulv = &si_pi->ulv; 5660 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5661 5662 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5663 5664 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5665 5666 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5667 5668 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5669 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5670 5671 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5672 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5673 si_pi->mc_reg_table.last, 5674 si_pi->mc_reg_table.valid_flag); 5675 5676 if (ulv->supported && ulv->pl.vddc != 0) 5677 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5678 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5679 else 5680 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5681 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5682 si_pi->mc_reg_table.last, 5683 si_pi->mc_reg_table.valid_flag); 5684 5685 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5686 5687 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5688 (u8 *)smc_mc_reg_table, 5689 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5690 } 5691 5692 static int si_upload_mc_reg_table(struct radeon_device *rdev, 5693 struct radeon_ps *radeon_new_state) 5694 { 5695 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5696 struct si_power_info *si_pi = si_get_pi(rdev); 5697 u32 address = si_pi->mc_reg_table_start + 5698 offsetof(SMC_SIslands_MCRegisters, 5699 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5700 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5701 5702 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5703 5704 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5705 5706 5707 return si_copy_bytes_to_smc(rdev, address, 5708 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5709 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5710 si_pi->sram_end); 5711 5712 } 5713 5714 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5715 { 5716 if (enable) 5717 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5718 else 5719 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5720 } 5721 5722 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5723 struct radeon_ps *radeon_state) 5724 { 5725 struct ni_ps *state = ni_get_ps(radeon_state); 5726 int i; 5727 u16 pcie_speed, max_speed = 0; 5728 5729 for (i = 0; i < state->performance_level_count; i++) { 5730 pcie_speed = state->performance_levels[i].pcie_gen; 5731 if (max_speed < pcie_speed) 5732 max_speed = pcie_speed; 5733 } 5734 return max_speed; 5735 } 5736 5737 static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5738 { 5739 u32 speed_cntl; 5740 5741 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5742 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5743 5744 return (u16)speed_cntl; 5745 } 5746 5747 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5748 struct radeon_ps *radeon_new_state, 5749 struct radeon_ps *radeon_current_state) 5750 { 5751 struct si_power_info *si_pi = si_get_pi(rdev); 5752 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5753 enum radeon_pcie_gen current_link_speed; 5754 5755 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5756 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5757 else 5758 current_link_speed = si_pi->force_pcie_gen; 5759 5760 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5761 si_pi->pspp_notify_required = false; 5762 if (target_link_speed > current_link_speed) { 5763 switch (target_link_speed) { 5764 #if defined(CONFIG_ACPI) 5765 case RADEON_PCIE_GEN3: 5766 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5767 break; 5768 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5769 if (current_link_speed == RADEON_PCIE_GEN2) 5770 break; 5771 /* fall through */ 5772 case RADEON_PCIE_GEN2: 5773 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5774 break; 5775 #endif 5776 /* fall through */ 5777 default: 5778 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5779 break; 5780 } 5781 } else { 5782 if (target_link_speed < current_link_speed) 5783 si_pi->pspp_notify_required = true; 5784 } 5785 } 5786 5787 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5788 struct radeon_ps *radeon_new_state, 5789 struct radeon_ps *radeon_current_state) 5790 { 5791 struct si_power_info *si_pi = si_get_pi(rdev); 5792 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5793 u8 request; 5794 5795 if (si_pi->pspp_notify_required) { 5796 if (target_link_speed == RADEON_PCIE_GEN3) 5797 request = PCIE_PERF_REQ_PECI_GEN3; 5798 else if (target_link_speed == RADEON_PCIE_GEN2) 5799 request = PCIE_PERF_REQ_PECI_GEN2; 5800 else 5801 request = PCIE_PERF_REQ_PECI_GEN1; 5802 5803 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5804 (si_get_current_pcie_speed(rdev) > 0)) 5805 return; 5806 5807 #if defined(CONFIG_ACPI) 5808 radeon_acpi_pcie_performance_request(rdev, request, false); 5809 #endif 5810 } 5811 } 5812 5813 #if 0 5814 static int si_ds_request(struct radeon_device *rdev, 5815 bool ds_status_on, u32 count_write) 5816 { 5817 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5818 5819 if (eg_pi->sclk_deep_sleep) { 5820 if (ds_status_on) 5821 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5822 PPSMC_Result_OK) ? 5823 0 : -EINVAL; 5824 else 5825 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5826 PPSMC_Result_OK) ? 0 : -EINVAL; 5827 } 5828 return 0; 5829 } 5830 #endif 5831 5832 static void si_set_max_cu_value(struct radeon_device *rdev) 5833 { 5834 struct si_power_info *si_pi = si_get_pi(rdev); 5835 5836 if (rdev->family == CHIP_VERDE) { 5837 switch (rdev->pdev->device) { 5838 case 0x6820: 5839 case 0x6825: 5840 case 0x6821: 5841 case 0x6823: 5842 case 0x6827: 5843 si_pi->max_cu = 10; 5844 break; 5845 case 0x682D: 5846 case 0x6824: 5847 case 0x682F: 5848 case 0x6826: 5849 si_pi->max_cu = 8; 5850 break; 5851 case 0x6828: 5852 case 0x6830: 5853 case 0x6831: 5854 case 0x6838: 5855 case 0x6839: 5856 case 0x683D: 5857 si_pi->max_cu = 10; 5858 break; 5859 case 0x683B: 5860 case 0x683F: 5861 case 0x6829: 5862 si_pi->max_cu = 8; 5863 break; 5864 default: 5865 si_pi->max_cu = 0; 5866 break; 5867 } 5868 } else { 5869 si_pi->max_cu = 0; 5870 } 5871 } 5872 5873 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5874 struct radeon_clock_voltage_dependency_table *table) 5875 { 5876 u32 i; 5877 int j; 5878 u16 leakage_voltage; 5879 5880 if (table) { 5881 for (i = 0; i < table->count; i++) { 5882 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5883 table->entries[i].v, 5884 &leakage_voltage)) { 5885 case 0: 5886 table->entries[i].v = leakage_voltage; 5887 break; 5888 case -EAGAIN: 5889 return -EINVAL; 5890 case -EINVAL: 5891 default: 5892 break; 5893 } 5894 } 5895 5896 for (j = (table->count - 2); j >= 0; j--) { 5897 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5898 table->entries[j].v : table->entries[j + 1].v; 5899 } 5900 } 5901 return 0; 5902 } 5903 5904 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5905 { 5906 int ret; 5907 5908 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5909 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5910 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5911 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5912 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5913 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5914 return ret; 5915 } 5916 5917 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5918 struct radeon_ps *radeon_new_state, 5919 struct radeon_ps *radeon_current_state) 5920 { 5921 u32 lane_width; 5922 u32 new_lane_width = 5923 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5924 u32 current_lane_width = 5925 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5926 5927 if (new_lane_width != current_lane_width) { 5928 radeon_set_pcie_lanes(rdev, new_lane_width); 5929 lane_width = radeon_get_pcie_lanes(rdev); 5930 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5931 } 5932 } 5933 5934 static void si_set_vce_clock(struct radeon_device *rdev, 5935 struct radeon_ps *new_rps, 5936 struct radeon_ps *old_rps) 5937 { 5938 if ((old_rps->evclk != new_rps->evclk) || 5939 (old_rps->ecclk != new_rps->ecclk)) { 5940 /* turn the clocks on when encoding, off otherwise */ 5941 if (new_rps->evclk || new_rps->ecclk) 5942 vce_v1_0_enable_mgcg(rdev, false); 5943 else 5944 vce_v1_0_enable_mgcg(rdev, true); 5945 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5946 } 5947 } 5948 5949 void si_dpm_setup_asic(struct radeon_device *rdev) 5950 { 5951 int r; 5952 5953 r = si_mc_load_microcode(rdev); 5954 if (r) 5955 DRM_ERROR("Failed to load MC firmware!\n"); 5956 rv770_get_memory_type(rdev); 5957 si_read_clock_registers(rdev); 5958 si_enable_acpi_power_management(rdev); 5959 } 5960 5961 static int si_thermal_enable_alert(struct radeon_device *rdev, 5962 bool enable) 5963 { 5964 u32 thermal_int = RREG32(CG_THERMAL_INT); 5965 5966 if (enable) { 5967 PPSMC_Result result; 5968 5969 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5970 WREG32(CG_THERMAL_INT, thermal_int); 5971 rdev->irq.dpm_thermal = false; 5972 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5973 if (result != PPSMC_Result_OK) { 5974 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5975 return -EINVAL; 5976 } 5977 } else { 5978 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5979 WREG32(CG_THERMAL_INT, thermal_int); 5980 rdev->irq.dpm_thermal = true; 5981 } 5982 5983 return 0; 5984 } 5985 5986 static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5987 int min_temp, int max_temp) 5988 { 5989 int low_temp = 0 * 1000; 5990 int high_temp = 255 * 1000; 5991 5992 if (low_temp < min_temp) 5993 low_temp = min_temp; 5994 if (high_temp > max_temp) 5995 high_temp = max_temp; 5996 if (high_temp < low_temp) { 5997 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5998 return -EINVAL; 5999 } 6000 6001 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6002 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6003 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6004 6005 rdev->pm.dpm.thermal.min_temp = low_temp; 6006 rdev->pm.dpm.thermal.max_temp = high_temp; 6007 6008 return 0; 6009 } 6010 6011 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 6012 { 6013 struct si_power_info *si_pi = si_get_pi(rdev); 6014 u32 tmp; 6015 6016 if (si_pi->fan_ctrl_is_in_default_mode) { 6017 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6018 si_pi->fan_ctrl_default_mode = tmp; 6019 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6020 si_pi->t_min = tmp; 6021 si_pi->fan_ctrl_is_in_default_mode = false; 6022 } 6023 6024 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6025 tmp |= TMIN(0); 6026 WREG32(CG_FDO_CTRL2, tmp); 6027 6028 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6029 tmp |= FDO_PWM_MODE(mode); 6030 WREG32(CG_FDO_CTRL2, tmp); 6031 } 6032 6033 static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6034 { 6035 struct si_power_info *si_pi = si_get_pi(rdev); 6036 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6037 u32 duty100; 6038 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6039 u16 fdo_min, slope1, slope2; 6040 u32 reference_clock, tmp; 6041 int ret; 6042 u64 tmp64; 6043 6044 if (!si_pi->fan_table_start) { 6045 rdev->pm.dpm.fan.ucode_fan_control = false; 6046 return 0; 6047 } 6048 6049 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6050 6051 if (duty100 == 0) { 6052 rdev->pm.dpm.fan.ucode_fan_control = false; 6053 return 0; 6054 } 6055 6056 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6057 do_div(tmp64, 10000); 6058 fdo_min = (u16)tmp64; 6059 6060 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6061 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6062 6063 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6064 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6065 6066 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6067 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6068 6069 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6070 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6071 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6072 6073 fan_table.slope1 = cpu_to_be16(slope1); 6074 fan_table.slope2 = cpu_to_be16(slope2); 6075 6076 fan_table.fdo_min = cpu_to_be16(fdo_min); 6077 6078 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6079 6080 fan_table.hys_up = cpu_to_be16(1); 6081 6082 fan_table.hys_slope = cpu_to_be16(1); 6083 6084 fan_table.temp_resp_lim = cpu_to_be16(5); 6085 6086 reference_clock = radeon_get_xclk(rdev); 6087 6088 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6089 reference_clock) / 1600); 6090 6091 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6092 6093 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6094 fan_table.temp_src = (uint8_t)tmp; 6095 6096 ret = si_copy_bytes_to_smc(rdev, 6097 si_pi->fan_table_start, 6098 (u8 *)(&fan_table), 6099 sizeof(fan_table), 6100 si_pi->sram_end); 6101 6102 if (ret) { 6103 DRM_ERROR("Failed to load fan table to the SMC."); 6104 rdev->pm.dpm.fan.ucode_fan_control = false; 6105 } 6106 6107 return 0; 6108 } 6109 6110 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6111 { 6112 struct si_power_info *si_pi = si_get_pi(rdev); 6113 PPSMC_Result ret; 6114 6115 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6116 if (ret == PPSMC_Result_OK) { 6117 si_pi->fan_is_controlled_by_smc = true; 6118 return 0; 6119 } else { 6120 return -EINVAL; 6121 } 6122 } 6123 6124 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6125 { 6126 struct si_power_info *si_pi = si_get_pi(rdev); 6127 PPSMC_Result ret; 6128 6129 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6130 6131 if (ret == PPSMC_Result_OK) { 6132 si_pi->fan_is_controlled_by_smc = false; 6133 return 0; 6134 } else { 6135 return -EINVAL; 6136 } 6137 } 6138 6139 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6140 u32 *speed) 6141 { 6142 u32 duty, duty100; 6143 u64 tmp64; 6144 6145 if (rdev->pm.no_fan) 6146 return -ENOENT; 6147 6148 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6149 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6150 6151 if (duty100 == 0) 6152 return -EINVAL; 6153 6154 tmp64 = (u64)duty * 100; 6155 do_div(tmp64, duty100); 6156 *speed = (u32)tmp64; 6157 6158 if (*speed > 100) 6159 *speed = 100; 6160 6161 return 0; 6162 } 6163 6164 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6165 u32 speed) 6166 { 6167 struct si_power_info *si_pi = si_get_pi(rdev); 6168 u32 tmp; 6169 u32 duty, duty100; 6170 u64 tmp64; 6171 6172 if (rdev->pm.no_fan) 6173 return -ENOENT; 6174 6175 if (si_pi->fan_is_controlled_by_smc) 6176 return -EINVAL; 6177 6178 if (speed > 100) 6179 return -EINVAL; 6180 6181 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6182 6183 if (duty100 == 0) 6184 return -EINVAL; 6185 6186 tmp64 = (u64)speed * duty100; 6187 do_div(tmp64, 100); 6188 duty = (u32)tmp64; 6189 6190 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6191 tmp |= FDO_STATIC_DUTY(duty); 6192 WREG32(CG_FDO_CTRL0, tmp); 6193 6194 return 0; 6195 } 6196 6197 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6198 { 6199 if (mode) { 6200 /* stop auto-manage */ 6201 if (rdev->pm.dpm.fan.ucode_fan_control) 6202 si_fan_ctrl_stop_smc_fan_control(rdev); 6203 si_fan_ctrl_set_static_mode(rdev, mode); 6204 } else { 6205 /* restart auto-manage */ 6206 if (rdev->pm.dpm.fan.ucode_fan_control) 6207 si_thermal_start_smc_fan_control(rdev); 6208 else 6209 si_fan_ctrl_set_default_mode(rdev); 6210 } 6211 } 6212 6213 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6214 { 6215 struct si_power_info *si_pi = si_get_pi(rdev); 6216 u32 tmp; 6217 6218 if (si_pi->fan_is_controlled_by_smc) 6219 return 0; 6220 6221 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6222 return (tmp >> FDO_PWM_MODE_SHIFT); 6223 } 6224 6225 #if 0 6226 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6227 u32 *speed) 6228 { 6229 u32 tach_period; 6230 u32 xclk = radeon_get_xclk(rdev); 6231 6232 if (rdev->pm.no_fan) 6233 return -ENOENT; 6234 6235 if (rdev->pm.fan_pulses_per_revolution == 0) 6236 return -ENOENT; 6237 6238 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6239 if (tach_period == 0) 6240 return -ENOENT; 6241 6242 *speed = 60 * xclk * 10000 / tach_period; 6243 6244 return 0; 6245 } 6246 6247 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6248 u32 speed) 6249 { 6250 u32 tach_period, tmp; 6251 u32 xclk = radeon_get_xclk(rdev); 6252 6253 if (rdev->pm.no_fan) 6254 return -ENOENT; 6255 6256 if (rdev->pm.fan_pulses_per_revolution == 0) 6257 return -ENOENT; 6258 6259 if ((speed < rdev->pm.fan_min_rpm) || 6260 (speed > rdev->pm.fan_max_rpm)) 6261 return -EINVAL; 6262 6263 if (rdev->pm.dpm.fan.ucode_fan_control) 6264 si_fan_ctrl_stop_smc_fan_control(rdev); 6265 6266 tach_period = 60 * xclk * 10000 / (8 * speed); 6267 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6268 tmp |= TARGET_PERIOD(tach_period); 6269 WREG32(CG_TACH_CTRL, tmp); 6270 6271 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6272 6273 return 0; 6274 } 6275 #endif 6276 6277 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6278 { 6279 struct si_power_info *si_pi = si_get_pi(rdev); 6280 u32 tmp; 6281 6282 if (!si_pi->fan_ctrl_is_in_default_mode) { 6283 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6284 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6285 WREG32(CG_FDO_CTRL2, tmp); 6286 6287 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6288 tmp |= TMIN(si_pi->t_min); 6289 WREG32(CG_FDO_CTRL2, tmp); 6290 si_pi->fan_ctrl_is_in_default_mode = true; 6291 } 6292 } 6293 6294 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6295 { 6296 if (rdev->pm.dpm.fan.ucode_fan_control) { 6297 si_fan_ctrl_start_smc_fan_control(rdev); 6298 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6299 } 6300 } 6301 6302 static void si_thermal_initialize(struct radeon_device *rdev) 6303 { 6304 u32 tmp; 6305 6306 if (rdev->pm.fan_pulses_per_revolution) { 6307 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6308 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6309 WREG32(CG_TACH_CTRL, tmp); 6310 } 6311 6312 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6313 tmp |= TACH_PWM_RESP_RATE(0x28); 6314 WREG32(CG_FDO_CTRL2, tmp); 6315 } 6316 6317 static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6318 { 6319 int ret; 6320 6321 si_thermal_initialize(rdev); 6322 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6323 if (ret) 6324 return ret; 6325 ret = si_thermal_enable_alert(rdev, true); 6326 if (ret) 6327 return ret; 6328 if (rdev->pm.dpm.fan.ucode_fan_control) { 6329 ret = si_halt_smc(rdev); 6330 if (ret) 6331 return ret; 6332 ret = si_thermal_setup_fan_table(rdev); 6333 if (ret) 6334 return ret; 6335 ret = si_resume_smc(rdev); 6336 if (ret) 6337 return ret; 6338 si_thermal_start_smc_fan_control(rdev); 6339 } 6340 6341 return 0; 6342 } 6343 6344 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6345 { 6346 if (!rdev->pm.no_fan) { 6347 si_fan_ctrl_set_default_mode(rdev); 6348 si_fan_ctrl_stop_smc_fan_control(rdev); 6349 } 6350 } 6351 6352 int si_dpm_enable(struct radeon_device *rdev) 6353 { 6354 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6355 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6356 struct si_power_info *si_pi = si_get_pi(rdev); 6357 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6358 int ret; 6359 6360 if (si_is_smc_running(rdev)) 6361 return -EINVAL; 6362 if (pi->voltage_control || si_pi->voltage_control_svi2) 6363 si_enable_voltage_control(rdev, true); 6364 if (pi->mvdd_control) 6365 si_get_mvdd_configuration(rdev); 6366 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6367 ret = si_construct_voltage_tables(rdev); 6368 if (ret) { 6369 DRM_ERROR("si_construct_voltage_tables failed\n"); 6370 return ret; 6371 } 6372 } 6373 if (eg_pi->dynamic_ac_timing) { 6374 ret = si_initialize_mc_reg_table(rdev); 6375 if (ret) 6376 eg_pi->dynamic_ac_timing = false; 6377 } 6378 if (pi->dynamic_ss) 6379 si_enable_spread_spectrum(rdev, true); 6380 if (pi->thermal_protection) 6381 si_enable_thermal_protection(rdev, true); 6382 si_setup_bsp(rdev); 6383 si_program_git(rdev); 6384 si_program_tp(rdev); 6385 si_program_tpp(rdev); 6386 si_program_sstp(rdev); 6387 si_enable_display_gap(rdev); 6388 si_program_vc(rdev); 6389 ret = si_upload_firmware(rdev); 6390 if (ret) { 6391 DRM_ERROR("si_upload_firmware failed\n"); 6392 return ret; 6393 } 6394 ret = si_process_firmware_header(rdev); 6395 if (ret) { 6396 DRM_ERROR("si_process_firmware_header failed\n"); 6397 return ret; 6398 } 6399 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6400 if (ret) { 6401 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6402 return ret; 6403 } 6404 ret = si_init_smc_table(rdev); 6405 if (ret) { 6406 DRM_ERROR("si_init_smc_table failed\n"); 6407 return ret; 6408 } 6409 ret = si_init_smc_spll_table(rdev); 6410 if (ret) { 6411 DRM_ERROR("si_init_smc_spll_table failed\n"); 6412 return ret; 6413 } 6414 ret = si_init_arb_table_index(rdev); 6415 if (ret) { 6416 DRM_ERROR("si_init_arb_table_index failed\n"); 6417 return ret; 6418 } 6419 if (eg_pi->dynamic_ac_timing) { 6420 ret = si_populate_mc_reg_table(rdev, boot_ps); 6421 if (ret) { 6422 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6423 return ret; 6424 } 6425 } 6426 ret = si_initialize_smc_cac_tables(rdev); 6427 if (ret) { 6428 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6429 return ret; 6430 } 6431 ret = si_initialize_hardware_cac_manager(rdev); 6432 if (ret) { 6433 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6434 return ret; 6435 } 6436 ret = si_initialize_smc_dte_tables(rdev); 6437 if (ret) { 6438 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6439 return ret; 6440 } 6441 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6442 if (ret) { 6443 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6444 return ret; 6445 } 6446 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6447 if (ret) { 6448 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6449 return ret; 6450 } 6451 si_program_response_times(rdev); 6452 si_program_ds_registers(rdev); 6453 si_dpm_start_smc(rdev); 6454 ret = si_notify_smc_display_change(rdev, false); 6455 if (ret) { 6456 DRM_ERROR("si_notify_smc_display_change failed\n"); 6457 return ret; 6458 } 6459 si_enable_sclk_control(rdev, true); 6460 si_start_dpm(rdev); 6461 6462 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6463 6464 si_thermal_start_thermal_controller(rdev); 6465 6466 ni_update_current_ps(rdev, boot_ps); 6467 6468 return 0; 6469 } 6470 6471 static int si_set_temperature_range(struct radeon_device *rdev) 6472 { 6473 int ret; 6474 6475 ret = si_thermal_enable_alert(rdev, false); 6476 if (ret) 6477 return ret; 6478 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6479 if (ret) 6480 return ret; 6481 ret = si_thermal_enable_alert(rdev, true); 6482 if (ret) 6483 return ret; 6484 6485 return ret; 6486 } 6487 6488 int si_dpm_late_enable(struct radeon_device *rdev) 6489 { 6490 int ret; 6491 6492 ret = si_set_temperature_range(rdev); 6493 if (ret) 6494 return ret; 6495 6496 return ret; 6497 } 6498 6499 void si_dpm_disable(struct radeon_device *rdev) 6500 { 6501 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6502 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6503 6504 if (!si_is_smc_running(rdev)) 6505 return; 6506 si_thermal_stop_thermal_controller(rdev); 6507 si_disable_ulv(rdev); 6508 si_clear_vc(rdev); 6509 if (pi->thermal_protection) 6510 si_enable_thermal_protection(rdev, false); 6511 si_enable_power_containment(rdev, boot_ps, false); 6512 si_enable_smc_cac(rdev, boot_ps, false); 6513 si_enable_spread_spectrum(rdev, false); 6514 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6515 si_stop_dpm(rdev); 6516 si_reset_to_default(rdev); 6517 si_dpm_stop_smc(rdev); 6518 si_force_switch_to_arb_f0(rdev); 6519 6520 ni_update_current_ps(rdev, boot_ps); 6521 } 6522 6523 int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6524 { 6525 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6526 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6527 struct radeon_ps *new_ps = &requested_ps; 6528 6529 ni_update_requested_ps(rdev, new_ps); 6530 6531 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6532 6533 return 0; 6534 } 6535 6536 static int si_power_control_set_level(struct radeon_device *rdev) 6537 { 6538 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6539 int ret; 6540 6541 ret = si_restrict_performance_levels_before_switch(rdev); 6542 if (ret) 6543 return ret; 6544 ret = si_halt_smc(rdev); 6545 if (ret) 6546 return ret; 6547 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6548 if (ret) 6549 return ret; 6550 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6551 if (ret) 6552 return ret; 6553 ret = si_resume_smc(rdev); 6554 if (ret) 6555 return ret; 6556 ret = si_set_sw_state(rdev); 6557 if (ret) 6558 return ret; 6559 return 0; 6560 } 6561 6562 int si_dpm_set_power_state(struct radeon_device *rdev) 6563 { 6564 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6565 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6566 struct radeon_ps *old_ps = &eg_pi->current_rps; 6567 int ret; 6568 6569 ret = si_disable_ulv(rdev); 6570 if (ret) { 6571 DRM_ERROR("si_disable_ulv failed\n"); 6572 return ret; 6573 } 6574 ret = si_restrict_performance_levels_before_switch(rdev); 6575 if (ret) { 6576 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6577 return ret; 6578 } 6579 if (eg_pi->pcie_performance_request) 6580 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6581 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6582 ret = si_enable_power_containment(rdev, new_ps, false); 6583 if (ret) { 6584 DRM_ERROR("si_enable_power_containment failed\n"); 6585 return ret; 6586 } 6587 ret = si_enable_smc_cac(rdev, new_ps, false); 6588 if (ret) { 6589 DRM_ERROR("si_enable_smc_cac failed\n"); 6590 return ret; 6591 } 6592 ret = si_halt_smc(rdev); 6593 if (ret) { 6594 DRM_ERROR("si_halt_smc failed\n"); 6595 return ret; 6596 } 6597 ret = si_upload_sw_state(rdev, new_ps); 6598 if (ret) { 6599 DRM_ERROR("si_upload_sw_state failed\n"); 6600 return ret; 6601 } 6602 ret = si_upload_smc_data(rdev); 6603 if (ret) { 6604 DRM_ERROR("si_upload_smc_data failed\n"); 6605 return ret; 6606 } 6607 ret = si_upload_ulv_state(rdev); 6608 if (ret) { 6609 DRM_ERROR("si_upload_ulv_state failed\n"); 6610 return ret; 6611 } 6612 if (eg_pi->dynamic_ac_timing) { 6613 ret = si_upload_mc_reg_table(rdev, new_ps); 6614 if (ret) { 6615 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6616 return ret; 6617 } 6618 } 6619 ret = si_program_memory_timing_parameters(rdev, new_ps); 6620 if (ret) { 6621 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6622 return ret; 6623 } 6624 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6625 6626 ret = si_resume_smc(rdev); 6627 if (ret) { 6628 DRM_ERROR("si_resume_smc failed\n"); 6629 return ret; 6630 } 6631 ret = si_set_sw_state(rdev); 6632 if (ret) { 6633 DRM_ERROR("si_set_sw_state failed\n"); 6634 return ret; 6635 } 6636 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6637 si_set_vce_clock(rdev, new_ps, old_ps); 6638 if (eg_pi->pcie_performance_request) 6639 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6640 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6641 if (ret) { 6642 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6643 return ret; 6644 } 6645 ret = si_enable_smc_cac(rdev, new_ps, true); 6646 if (ret) { 6647 DRM_ERROR("si_enable_smc_cac failed\n"); 6648 return ret; 6649 } 6650 ret = si_enable_power_containment(rdev, new_ps, true); 6651 if (ret) { 6652 DRM_ERROR("si_enable_power_containment failed\n"); 6653 return ret; 6654 } 6655 6656 ret = si_power_control_set_level(rdev); 6657 if (ret) { 6658 DRM_ERROR("si_power_control_set_level failed\n"); 6659 return ret; 6660 } 6661 6662 return 0; 6663 } 6664 6665 void si_dpm_post_set_power_state(struct radeon_device *rdev) 6666 { 6667 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6668 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6669 6670 ni_update_current_ps(rdev, new_ps); 6671 } 6672 6673 #if 0 6674 void si_dpm_reset_asic(struct radeon_device *rdev) 6675 { 6676 si_restrict_performance_levels_before_switch(rdev); 6677 si_disable_ulv(rdev); 6678 si_set_boot_state(rdev); 6679 } 6680 #endif 6681 6682 void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6683 { 6684 si_program_display_gap(rdev); 6685 } 6686 6687 union power_info { 6688 struct _ATOM_POWERPLAY_INFO info; 6689 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6690 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6691 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6692 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6693 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6694 }; 6695 6696 union pplib_clock_info { 6697 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6698 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6699 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6700 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6701 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6702 }; 6703 6704 union pplib_power_state { 6705 struct _ATOM_PPLIB_STATE v1; 6706 struct _ATOM_PPLIB_STATE_V2 v2; 6707 }; 6708 6709 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6710 struct radeon_ps *rps, 6711 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6712 u8 table_rev) 6713 { 6714 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6715 rps->class = le16_to_cpu(non_clock_info->usClassification); 6716 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6717 6718 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6719 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6720 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6721 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6722 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6723 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6724 } else { 6725 rps->vclk = 0; 6726 rps->dclk = 0; 6727 } 6728 6729 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6730 rdev->pm.dpm.boot_ps = rps; 6731 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6732 rdev->pm.dpm.uvd_ps = rps; 6733 } 6734 6735 static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6736 struct radeon_ps *rps, int index, 6737 union pplib_clock_info *clock_info) 6738 { 6739 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6740 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6741 struct si_power_info *si_pi = si_get_pi(rdev); 6742 struct ni_ps *ps = ni_get_ps(rps); 6743 u16 leakage_voltage; 6744 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6745 int ret; 6746 6747 ps->performance_level_count = index + 1; 6748 6749 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6750 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6751 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6752 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6753 6754 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6755 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6756 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6757 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6758 si_pi->sys_pcie_mask, 6759 si_pi->boot_pcie_gen, 6760 clock_info->si.ucPCIEGen); 6761 6762 /* patch up vddc if necessary */ 6763 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6764 &leakage_voltage); 6765 if (ret == 0) 6766 pl->vddc = leakage_voltage; 6767 6768 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6769 pi->acpi_vddc = pl->vddc; 6770 eg_pi->acpi_vddci = pl->vddci; 6771 si_pi->acpi_pcie_gen = pl->pcie_gen; 6772 } 6773 6774 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6775 index == 0) { 6776 /* XXX disable for A0 tahiti */ 6777 si_pi->ulv.supported = false; 6778 si_pi->ulv.pl = *pl; 6779 si_pi->ulv.one_pcie_lane_in_ulv = false; 6780 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6781 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6782 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6783 } 6784 6785 if (pi->min_vddc_in_table > pl->vddc) 6786 pi->min_vddc_in_table = pl->vddc; 6787 6788 if (pi->max_vddc_in_table < pl->vddc) 6789 pi->max_vddc_in_table = pl->vddc; 6790 6791 /* patch up boot state */ 6792 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6793 u16 vddc, vddci, mvdd; 6794 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6795 pl->mclk = rdev->clock.default_mclk; 6796 pl->sclk = rdev->clock.default_sclk; 6797 pl->vddc = vddc; 6798 pl->vddci = vddci; 6799 si_pi->mvdd_bootup_value = mvdd; 6800 } 6801 6802 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6803 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6804 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6805 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6806 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6807 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6808 } 6809 } 6810 6811 static int si_parse_power_table(struct radeon_device *rdev) 6812 { 6813 struct radeon_mode_info *mode_info = &rdev->mode_info; 6814 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6815 union pplib_power_state *power_state; 6816 int i, j, k, non_clock_array_index, clock_array_index; 6817 union pplib_clock_info *clock_info; 6818 struct _StateArray *state_array; 6819 struct _ClockInfoArray *clock_info_array; 6820 struct _NonClockInfoArray *non_clock_info_array; 6821 union power_info *power_info; 6822 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6823 u16 data_offset; 6824 u8 frev, crev; 6825 u8 *power_state_offset; 6826 struct ni_ps *ps; 6827 6828 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6829 &frev, &crev, &data_offset)) 6830 return -EINVAL; 6831 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6832 6833 state_array = (struct _StateArray *) 6834 (mode_info->atom_context->bios + data_offset + 6835 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6836 clock_info_array = (struct _ClockInfoArray *) 6837 (mode_info->atom_context->bios + data_offset + 6838 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6839 non_clock_info_array = (struct _NonClockInfoArray *) 6840 (mode_info->atom_context->bios + data_offset + 6841 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6842 6843 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6844 sizeof(struct radeon_ps), 6845 GFP_KERNEL); 6846 if (!rdev->pm.dpm.ps) 6847 return -ENOMEM; 6848 power_state_offset = (u8 *)state_array->states; 6849 for (i = 0; i < state_array->ucNumEntries; i++) { 6850 u8 *idx; 6851 power_state = (union pplib_power_state *)power_state_offset; 6852 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6853 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6854 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6855 if (!rdev->pm.power_state[i].clock_info) 6856 return -EINVAL; 6857 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6858 if (ps == NULL) { 6859 kfree(rdev->pm.dpm.ps); 6860 return -ENOMEM; 6861 } 6862 rdev->pm.dpm.ps[i].ps_priv = ps; 6863 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6864 non_clock_info, 6865 non_clock_info_array->ucEntrySize); 6866 k = 0; 6867 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6868 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6869 clock_array_index = idx[j]; 6870 if (clock_array_index >= clock_info_array->ucNumEntries) 6871 continue; 6872 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6873 break; 6874 clock_info = (union pplib_clock_info *) 6875 ((u8 *)&clock_info_array->clockInfo[0] + 6876 (clock_array_index * clock_info_array->ucEntrySize)); 6877 si_parse_pplib_clock_info(rdev, 6878 &rdev->pm.dpm.ps[i], k, 6879 clock_info); 6880 k++; 6881 } 6882 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6883 } 6884 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6885 6886 /* fill in the vce power states */ 6887 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6888 u32 sclk, mclk; 6889 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6890 clock_info = (union pplib_clock_info *) 6891 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6892 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6893 sclk |= clock_info->si.ucEngineClockHigh << 16; 6894 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6895 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6896 rdev->pm.dpm.vce_states[i].sclk = sclk; 6897 rdev->pm.dpm.vce_states[i].mclk = mclk; 6898 } 6899 6900 return 0; 6901 } 6902 6903 int si_dpm_init(struct radeon_device *rdev) 6904 { 6905 struct rv7xx_power_info *pi; 6906 struct evergreen_power_info *eg_pi; 6907 struct ni_power_info *ni_pi; 6908 struct si_power_info *si_pi; 6909 struct atom_clock_dividers dividers; 6910 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6911 struct pci_dev *root = rdev->pdev->bus->self; 6912 int ret; 6913 6914 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6915 if (si_pi == NULL) 6916 return -ENOMEM; 6917 rdev->pm.dpm.priv = si_pi; 6918 ni_pi = &si_pi->ni; 6919 eg_pi = &ni_pi->eg; 6920 pi = &eg_pi->rv7xx; 6921 6922 if (!pci_is_root_bus(rdev->pdev->bus)) 6923 speed_cap = pcie_get_speed_cap(root); 6924 if (speed_cap == PCI_SPEED_UNKNOWN) { 6925 si_pi->sys_pcie_mask = 0; 6926 } else { 6927 if (speed_cap == PCIE_SPEED_8_0GT) 6928 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6929 RADEON_PCIE_SPEED_50 | 6930 RADEON_PCIE_SPEED_80; 6931 else if (speed_cap == PCIE_SPEED_5_0GT) 6932 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6933 RADEON_PCIE_SPEED_50; 6934 else 6935 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6936 } 6937 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6938 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6939 6940 si_set_max_cu_value(rdev); 6941 6942 rv770_get_max_vddc(rdev); 6943 si_get_leakage_vddc(rdev); 6944 si_patch_dependency_tables_based_on_leakage(rdev); 6945 6946 pi->acpi_vddc = 0; 6947 eg_pi->acpi_vddci = 0; 6948 pi->min_vddc_in_table = 0; 6949 pi->max_vddc_in_table = 0; 6950 6951 ret = r600_get_platform_caps(rdev); 6952 if (ret) 6953 return ret; 6954 6955 ret = r600_parse_extended_power_table(rdev); 6956 if (ret) 6957 return ret; 6958 6959 ret = si_parse_power_table(rdev); 6960 if (ret) 6961 return ret; 6962 6963 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6964 kcalloc(4, 6965 sizeof(struct radeon_clock_voltage_dependency_entry), 6966 GFP_KERNEL); 6967 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6968 r600_free_extended_power_table(rdev); 6969 return -ENOMEM; 6970 } 6971 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6972 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6973 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6974 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6975 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6976 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6977 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6978 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6979 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6980 6981 if (rdev->pm.dpm.voltage_response_time == 0) 6982 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6983 if (rdev->pm.dpm.backbias_response_time == 0) 6984 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6985 6986 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6987 0, false, ÷rs); 6988 if (ret) 6989 pi->ref_div = dividers.ref_div + 1; 6990 else 6991 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6992 6993 eg_pi->smu_uvd_hs = false; 6994 6995 pi->mclk_strobe_mode_threshold = 40000; 6996 if (si_is_special_1gb_platform(rdev)) 6997 pi->mclk_stutter_mode_threshold = 0; 6998 else 6999 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7000 pi->mclk_edc_enable_threshold = 40000; 7001 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7002 7003 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7004 7005 pi->voltage_control = 7006 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7007 VOLTAGE_OBJ_GPIO_LUT); 7008 if (!pi->voltage_control) { 7009 si_pi->voltage_control_svi2 = 7010 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7011 VOLTAGE_OBJ_SVID2); 7012 if (si_pi->voltage_control_svi2) 7013 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7014 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7015 } 7016 7017 pi->mvdd_control = 7018 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7019 VOLTAGE_OBJ_GPIO_LUT); 7020 7021 eg_pi->vddci_control = 7022 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7023 VOLTAGE_OBJ_GPIO_LUT); 7024 if (!eg_pi->vddci_control) 7025 si_pi->vddci_control_svi2 = 7026 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7027 VOLTAGE_OBJ_SVID2); 7028 7029 si_pi->vddc_phase_shed_control = 7030 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7031 VOLTAGE_OBJ_PHASE_LUT); 7032 7033 rv770_get_engine_memory_ss(rdev); 7034 7035 pi->asi = RV770_ASI_DFLT; 7036 pi->pasi = CYPRESS_HASI_DFLT; 7037 pi->vrc = SISLANDS_VRC_DFLT; 7038 7039 pi->gfx_clock_gating = true; 7040 7041 eg_pi->sclk_deep_sleep = true; 7042 si_pi->sclk_deep_sleep_above_low = false; 7043 7044 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7045 pi->thermal_protection = true; 7046 else 7047 pi->thermal_protection = false; 7048 7049 eg_pi->dynamic_ac_timing = true; 7050 7051 eg_pi->light_sleep = true; 7052 #if defined(CONFIG_ACPI) 7053 eg_pi->pcie_performance_request = 7054 radeon_acpi_is_pcie_performance_request_supported(rdev); 7055 #else 7056 eg_pi->pcie_performance_request = false; 7057 #endif 7058 7059 si_pi->sram_end = SMC_RAM_END; 7060 7061 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7062 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7063 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7064 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7065 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7066 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7067 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7068 7069 si_initialize_powertune_defaults(rdev); 7070 7071 /* make sure dc limits are valid */ 7072 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7073 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7074 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7075 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7076 7077 si_pi->fan_ctrl_is_in_default_mode = true; 7078 7079 return 0; 7080 } 7081 7082 void si_dpm_fini(struct radeon_device *rdev) 7083 { 7084 int i; 7085 7086 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7087 kfree(rdev->pm.dpm.ps[i].ps_priv); 7088 } 7089 kfree(rdev->pm.dpm.ps); 7090 kfree(rdev->pm.dpm.priv); 7091 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7092 r600_free_extended_power_table(rdev); 7093 } 7094 7095 #ifdef CONFIG_DEBUG_FS 7096 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7097 struct seq_file *m) 7098 { 7099 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7100 struct radeon_ps *rps = &eg_pi->current_rps; 7101 struct ni_ps *ps = ni_get_ps(rps); 7102 struct rv7xx_pl *pl; 7103 u32 current_index = 7104 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7105 CURRENT_STATE_INDEX_SHIFT; 7106 7107 if (current_index >= ps->performance_level_count) { 7108 seq_printf(m, "invalid dpm profile %d\n", current_index); 7109 } else { 7110 pl = &ps->performance_levels[current_index]; 7111 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7112 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7113 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7114 } 7115 } 7116 #endif 7117 7118 u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7119 { 7120 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7121 struct radeon_ps *rps = &eg_pi->current_rps; 7122 struct ni_ps *ps = ni_get_ps(rps); 7123 struct rv7xx_pl *pl; 7124 u32 current_index = 7125 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7126 CURRENT_STATE_INDEX_SHIFT; 7127 7128 if (current_index >= ps->performance_level_count) { 7129 return 0; 7130 } else { 7131 pl = &ps->performance_levels[current_index]; 7132 return pl->sclk; 7133 } 7134 } 7135 7136 u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7137 { 7138 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7139 struct radeon_ps *rps = &eg_pi->current_rps; 7140 struct ni_ps *ps = ni_get_ps(rps); 7141 struct rv7xx_pl *pl; 7142 u32 current_index = 7143 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7144 CURRENT_STATE_INDEX_SHIFT; 7145 7146 if (current_index >= ps->performance_level_count) { 7147 return 0; 7148 } else { 7149 pl = &ps->performance_levels[current_index]; 7150 return pl->mclk; 7151 } 7152 } 7153
Indexes created Sat Sep 20 22:09:52 GMT 2025