1 /* $NetBSD: if_etreg.h,v 1.5 2024/02/09 22:08:35 andvar Exp $ */ 2 /* $OpenBSD: if_etreg.h,v 1.3 2008/06/08 06:18:07 jsg Exp $ */ 3 4 /* 5 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 6 * 7 * This code is derived from software contributed to The DragonFly Project 8 * by Sepherosa Ziehau <sepherosa (at) gmail.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * 3. Neither the name of The DragonFly Project nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific, prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 28 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ 38 */ 39 40 #ifndef _IF_ETREG_H 41 #define _IF_ETREG_H 42 43 #define ET_INTERN_MEM_SIZE 0x400 44 #define ET_INTERN_MEM_END (ET_INTERN_MEM_SIZE - 1) 45 46 /* 47 * PCI registers 48 * 49 * ET_PCIV_ACK_LATENCY_{128,256} are from 50 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 51 * 52 * ET_PCIV_REPLAY_TIMER_{128,256} are from 53 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 54 */ 55 #define ET_PCIR_BAR 0x10 56 57 #define ET_PCIR_DEVICE_CAPS 0x4c 58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 61 62 #define ET_PCIR_DEVICE_CTRL 0x50 63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 65 66 #define ET_PCIR_MACADDR_LO 0xa4 67 #define ET_PCIR_MACADDR_HI 0xa8 68 69 #define ET_PCIR_EEPROM_MISC 0xb0 70 #define ET_PCIR_EEPROM_STATUS_MASK 0x0000ff00 71 #define ET_PCIM_EEPROM_STATUS_ERROR 0x00004c00 72 73 #define ET_PCIR_ACK_LATENCY 0xc0 74 #define ET_PCIV_ACK_LATENCY_128 237 75 #define ET_PCIV_ACK_LATENCY_256 416 76 77 #define ET_PCIR_REPLAY_TIMER 0xc2 78 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX inferred from default */ 79 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 80 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 81 82 #define ET_PCIR_L0S_L1_LATENCY 0xcf 83 #define ET_PCIM_L0S_LATENCY (7 << 0) 84 #define ET_PCIM_L1_LATENCY (7 << 3) 85 86 /* 87 * CSR 88 */ 89 #define ET_TXQ_START 0x0000 90 #define ET_TXQ_END 0x0004 91 #define ET_RXQ_START 0x0008 92 #define ET_RXQ_END 0x000c 93 94 #define ET_PM 0x0010 95 #define EM_PM_GIGEPHY_ENB (1 << 0) 96 #define ET_PM_SYSCLK_GATE (1 << 3) 97 #define ET_PM_TXCLK_GATE (1 << 4) 98 #define ET_PM_RXCLK_GATE (1 << 5) 99 100 #define ET_INTR_STATUS 0x0018 101 #define ET_INTR_MASK 0x001c 102 103 #define ET_SWRST 0x0028 104 #define ET_SWRST_TXDMA (1 << 0) 105 #define ET_SWRST_RXDMA (1 << 1) 106 #define ET_SWRST_TXMAC (1 << 2) 107 #define ET_SWRST_RXMAC (1 << 3) 108 #define ET_SWRST_MAC (1 << 4) 109 #define ET_SWRST_MAC_STAT (1 << 5) 110 #define ET_SWRST_MMC (1 << 6) 111 #define ET_SWRST_SELFCLR_DISABLE (1 << 31) 112 113 #define ET_MSI_CFG 0x0030 114 115 #define ET_LOOPBACK 0x0034 116 117 #define ET_TIMER 0x0038 118 119 #define ET_TXDMA_CTRL 0x1000 120 #define ET_TXDMA_CTRL_HALT (1 << 0) 121 #define ET_TXDMA_CTRL_CACHE_THR 0xf0 122 #define ET_TXDMA_CTRL_SINGLE_EPKT (1 << 8) 123 124 #define ET_TX_RING_HI 0x1004 125 #define ET_TX_RING_LO 0x1008 126 #define ET_TX_RING_CNT 0x100c 127 128 #define ET_TX_STATUS_HI 0x101c 129 #define ET_TX_STATUS_LO 0x1020 130 131 #define ET_TX_READY_POS 0x1024 132 #define ET_TX_READY_POS_INDEX 0x03ff 133 #define ET_TX_READY_POS_WRAP (1 << 10) 134 135 #define ET_TX_DONE_POS 0x1060 136 #define ET_TX_DONE_POS_INDEX 0x03ff 137 #define ET_TX_DONE_POS_WRAP (1 << 10) 138 139 #define ET_RXDMA_CTRL 0x2000 140 #define ET_RXDMA_CTRL_HALT (1 << 0) 141 #define ET_RXDMA_CTRL_RING0_SIZE (3 << 8) 142 #define ET_RXDMA_CTRL_RING0_ENABLE (1 << 10) 143 #define ET_RXDMA_CTRL_RING1_SIZE (3 << 11) 144 #define ET_RXDMA_CTRL_RING1_ENABLE (1 << 13) 145 #define ET_RXDMA_CTRL_HALTED (1 << 17) 146 147 #define ET_RX_STATUS_LO 0x2004 148 #define ET_RX_STATUS_HI 0x2008 149 150 #define ET_RX_INTR_NPKTS 0x200c 151 #define ET_RX_INTR_DELAY 0x2010 152 153 #define ET_RXSTAT_LO 0x2020 154 #define ET_RXSTAT_HI 0x2024 155 #define ET_RXSTAT_CNT 0x2028 156 157 #define ET_RXSTAT_POS 0x2030 158 #define ET_RXSTAT_POS_INDEX 0x0fff 159 #define ET_RXSTAT_POS_WRAP (1 << 12) 160 161 #define ET_RXSTAT_MINCNT 0x2038 162 163 #define ET_RX_RING0_LO 0x203c 164 #define ET_RX_RING0_HI 0x2040 165 #define ET_RX_RING0_CNT 0x2044 166 167 #define ET_RX_RING0_POS 0x204c 168 #define ET_RX_RING0_POS_INDEX 0x03ff 169 #define ET_RX_RING0_POS_WRAP (1 << 10) 170 171 #define ET_RX_RING0_MINCNT 0x2054 172 173 #define ET_RX_RING1_LO 0x2058 174 #define ET_RX_RING1_HI 0x205c 175 #define ET_RX_RING1_CNT 0x2060 176 177 #define ET_RX_RING1_POS 0x2068 178 #define ET_RX_RING1_POS_INDEX 0x03ff 179 #define ET_RX_RING1_POS_WRAP (1 << 10) 180 181 #define ET_RX_RING1_MINCNT 0x2070 182 183 #define ET_TXMAC_CTRL 0x3000 184 #define ET_TXMAC_CTRL_ENABLE (1 << 0) 185 #define ET_TXMAC_CTRL_FC_DISABLE (1 << 3) 186 187 #define ET_TXMAC_FLOWCTRL 0x3010 188 189 #define ET_RXMAC_CTRL 0x4000 190 #define ET_RXMAC_CTRL_ENABLE (1 << 0) 191 #define ET_RXMAC_CTRL_NO_PKTFILT (1 << 2) 192 #define ET_RXMAC_CTRL_WOL_DISABLE (1 << 3) 193 194 #define ET_WOL_CRC 0x4004 195 #define ET_WOL_SA_LO 0x4010 196 #define ET_WOL_SA_HI 0x4014 197 #define ET_WOL_MASK 0x4018 198 199 #define ET_UCAST_FILTADDR1 0x4068 200 #define ET_UCAST_FILTADDR2 0x406c 201 #define ET_UCAST_FILTADDR3 0x4070 202 203 #define ET_MULTI_HASH 0x4074 204 205 #define ET_PKTFILT 0x4084 206 #define ET_PKTFILT_BCAST (1 << 0) 207 #define ET_PKTFILT_MCAST (1 << 1) 208 #define ET_PKTFILT_UCAST (1 << 2) 209 #define ET_PKTFILT_FRAG (1 << 3) 210 #define ET_PKTFILT_MINLEN 0x7f0000 211 212 #define ET_RXMAC_MC_SEGSZ 0x4088 213 #define ET_RXMAC_MC_SEGSZ_ENABLE (1 << 0) 214 #define ET_RXMAC_MC_SEGSZ_FC (1 << 1) 215 #define ET_RXMAC_MC_SEGSZ_MAX 0x03fc 216 217 #define ET_RXMAC_MC_WATERMARK 0x408c 218 #define ET_RXMAC_SPACE_AVL 0x4094 219 220 #define ET_RXMAC_MGT 0x4098 221 #define ET_RXMAC_MGT_PASS_ECRC (1 << 4) 222 #define ET_RXMAC_MGT_PASS_ELEN (1 << 5) 223 #define ET_RXMAC_MGT_PASS_ETRUNC (1 << 16) 224 #define ET_RXMAC_MGT_CHECK_PKT (1 << 17) 225 226 #define ET_MAC_CFG1 0x5000 227 #define ET_MAC_CFG1_TXEN (1 << 0) 228 #define ET_MAC_CFG1_SYNC_TXEN (1 << 1) 229 #define ET_MAC_CFG1_RXEN (1 << 2) 230 #define ET_MAC_CFG1_SYNC_RXEN (1 << 3) 231 #define ET_MAC_CFG1_TXFLOW (1 << 4) 232 #define ET_MAC_CFG1_RXFLOW (1 << 5) 233 #define ET_MAC_CFG1_LOOPBACK (1 << 8) 234 #define ET_MAC_CFG1_RST_TXFUNC (1 << 16) 235 #define ET_MAC_CFG1_RST_RXFUNC (1 << 17) 236 #define ET_MAC_CFG1_RST_TXMC (1 << 18) 237 #define ET_MAC_CFG1_RST_RXMC (1 << 19) 238 #define ET_MAC_CFG1_SIM_RST (1 << 30) 239 #define ET_MAC_CFG1_SOFT_RST __BIT(31) 240 241 #define ET_MAC_CFG2 0x5004 242 #define ET_MAC_CFG2_FDX (1 << 0) 243 #define ET_MAC_CFG2_CRC (1 << 1) 244 #define ET_MAC_CFG2_PADCRC (1 << 2) 245 #define ET_MAC_CFG2_LENCHK (1 << 4) 246 #define ET_MAC_CFG2_BIGFRM (1 << 5) 247 #define ET_MAC_CFG2_MODE_MII (1 << 8) 248 #define ET_MAC_CFG2_MODE_GMII (1 << 9) 249 #define ET_MAC_CFG2_PREAMBLE_LEN 0xf000 250 251 #define ET_IPG 0x5008 252 #define ET_IPG_B2B 0x0000007f 253 #define ET_IPG_MINIFG 0x0000ff00 254 #define ET_IPG_NONB2B_2 0x007f0000 255 #define ET_IPG_NONB2B_1 0x7f000000 256 257 #define ET_MAC_HDX 0x500c 258 #define ET_MAC_HDX_COLLWIN 0x0003ff 259 #define ET_MAC_HDX_REXMIT_MAX 0x00f000 260 #define ET_MAC_HDX_REXMIT_MAX 0x00f000 261 #define ET_MAC_HDX_EXC_DEFER (1 << 16) 262 #define ET_MAC_HDX_NOBACKOFF (1 << 17) 263 #define ET_MAC_HDX_BP_NOBACKOFF (1 << 18) 264 #define ET_MAC_HDX_ALT_BEB (1 << 19) 265 #define ET_MAC_HDX_ALT_BEB_TRUNC 0xf00000 266 267 #define ET_MAX_FRMLEN 0x5010 268 269 #define ET_MII_CFG 0x5020 270 #define ET_MII_CFG_CLKRST (7 << 0) 271 #define ET_MII_CFG_PREAMBLE_SUP (1 << 4) 272 #define ET_MII_CFG_SCAN_AUTOINC (1 << 5) 273 #define ET_MII_CFG_RST (1 << 31) 274 275 #define ET_MII_CMD 0x5024 276 #define ET_MII_CMD_READ (1 << 0) 277 278 #define ET_MII_ADDR 0x5028 279 #define ET_MII_ADDR_REG 0x001f 280 #define ET_MII_ADDR_PHY 0x1f00 281 #define ET_MII_ADDR_SHIFT 8 282 283 284 #define ET_MII_CTRL 0x502c 285 #define ET_MII_CTRL_VALUE 0xffff 286 287 #define ET_MII_STAT 0x5030 288 #define ET_MII_STAT_VALUE 0xffff 289 290 #define ET_MII_IND 0x5034 291 #define ET_MII_IND_BUSY (1 << 0) 292 #define ET_MII_IND_INVALID (1 << 2) 293 294 #define ET_MAC_CTRL 0x5038 295 #define ET_MAC_CTRL_MODE_MII (1 << 24) 296 #define ET_MAC_CTRL_LHDX (1 << 25) 297 #define ET_MAC_CTRL_GHDX (1 << 26) 298 299 #define ET_MAC_ADDR1 0x5040 300 #define ET_MAC_ADDR2 0x5044 301 302 #define ET_MMC_CTRL 0x7000 303 #define ET_MMC_CTRL_ENABLE (1 << 0) 304 #define ET_MMC_CTRL_ARB_DISABLE (1 << 1) 305 #define ET_MMC_CTRL_RXMAC_DISABLE (1 << 2) 306 #define ET_MMC_CTRL_TXMAC_DISABLE (1 << 3) 307 #define ET_MMC_CTRL_TXDMA_DISABLE (1 << 4) 308 #define ET_MMC_CTRL_RXDMA_DISABLE (1 << 5) 309 #define ET_MMC_CTRL_FORCE_CE (1 << 6) 310 311 /* 312 * Interrupts 313 */ 314 #define ET_INTR_TXEOF (1 << 3) 315 #define ET_INTR_TXDMA_ERROR (1 << 4) 316 #define ET_INTR_RXEOF (1 << 5) 317 #define ET_INTR_RXRING0_LOW (1 << 6) 318 #define ET_INTR_RXRING1_LOW (1 << 7) 319 #define ET_INTR_RXSTAT_LOW (1 << 8) 320 #define ET_INTR_RXDMA_ERROR (1 << 9) 321 #define ET_INTR_TIMER (1 << 10) 322 #define ET_INTR_WOL (1 << 15) 323 #define ET_INTR_PHY (1 << 16) 324 #define ET_INTR_TXMAC (1 << 17) 325 #define ET_INTR_RXMAC (1 << 18) 326 #define ET_INTR_MAC_STATS (1 << 19) 327 #define ET_INTR_SLAVE_TO (1 << 20) 328 329 #define ET_INTRS (ET_INTR_TXEOF | \ 330 ET_INTR_RXEOF | \ 331 ET_INTR_TIMER) 332 333 /* 334 * RX ring position uses same layout 335 */ 336 #define ET_RX_RING_POS_INDEX (0x03ff << 0) 337 #define ET_RX_RING_POS_WRAP (1 << 10) 338 339 340 /* $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ */ 341 342 #define ET_ALIGN 0x1000 343 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 344 #define ET_NSEG_SPARE 5 345 346 #define ET_TX_NDESC 512 347 #define ET_RX_NDESC 512 348 #define ET_RX_NRING 2 349 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 350 351 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 352 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 353 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 354 355 #define CSR_WRITE_4(sc, reg, val) \ 356 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 357 #define CSR_READ_4(sc, reg) \ 358 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 359 360 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 361 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 362 363 struct et_txdesc { 364 uint32_t td_addr_hi; 365 uint32_t td_addr_lo; 366 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 367 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 368 } __packed; 369 370 #define ET_TDCTRL1_LEN 0xffff 371 372 #define ET_TDCTRL2_LAST_FRAG (1 << 0) 373 #define ET_TDCTRL2_FIRST_FRAG (1 << 1) 374 #define ET_TDCTRL2_INTR (1 << 2) 375 376 struct et_rxdesc { 377 uint32_t rd_addr_lo; 378 uint32_t rd_addr_hi; 379 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 380 } __packed; 381 382 #define ET_RDCTRL_BUFIDX 0x03ff 383 384 struct et_rxstat { 385 uint32_t rxst_info1; 386 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 387 } __packed; 388 389 #define ET_RXST_INFO2_LEN 0x000ffff 390 #define ET_RXST_INFO2_BUFIDX 0x3ff0000 391 #define ET_RXST_INFO2_RINGIDX (3 << 26) 392 393 struct et_rxstatus { 394 uint32_t rxs_ring; 395 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 396 } __packed; 397 398 #define ET_RXS_STATRING_INDEX 0xfff0000 399 #define ET_RXS_STATRING_WRAP (1 << 28) 400 401 struct et_txbuf { 402 struct mbuf *tb_mbuf; 403 bus_dmamap_t tb_dmap; 404 bus_dma_segment_t tb_seg; 405 }; 406 407 struct et_rxbuf { 408 struct mbuf *rb_mbuf; 409 bus_dmamap_t rb_dmap; 410 bus_dma_segment_t rb_seg; 411 bus_addr_t rb_paddr; 412 }; 413 414 struct et_txstatus_data { 415 uint32_t *txsd_status; 416 bus_addr_t txsd_paddr; 417 bus_dma_tag_t txsd_dtag; 418 bus_dmamap_t txsd_dmap; 419 bus_dma_segment_t txsd_seg; 420 }; 421 422 struct et_rxstatus_data { 423 struct et_rxstatus *rxsd_status; 424 bus_addr_t rxsd_paddr; 425 bus_dma_tag_t rxsd_dtag; 426 bus_dmamap_t rxsd_dmap; 427 bus_dma_segment_t rxsd_seg; 428 }; 429 430 struct et_rxstat_ring { 431 struct et_rxstat *rsr_stat; 432 bus_addr_t rsr_paddr; 433 bus_dma_tag_t rsr_dtag; 434 bus_dmamap_t rsr_dmap; 435 bus_dma_segment_t rsr_seg; 436 437 int rsr_index; 438 int rsr_wrap; 439 }; 440 441 struct et_txdesc_ring { 442 struct et_txdesc *tr_desc; 443 bus_addr_t tr_paddr; 444 bus_dma_tag_t tr_dtag; 445 bus_dmamap_t tr_dmap; 446 bus_dma_segment_t tr_seg; 447 448 int tr_ready_index; 449 int tr_ready_wrap; 450 }; 451 452 struct et_rxdesc_ring { 453 struct et_rxdesc *rr_desc; 454 bus_addr_t rr_paddr; 455 bus_dma_tag_t rr_dtag; 456 bus_dmamap_t rr_dmap; 457 bus_dma_segment_t rr_seg; 458 459 uint32_t rr_posreg; 460 int rr_index; 461 int rr_wrap; 462 }; 463 464 struct et_txbuf_data { 465 struct et_txbuf tbd_buf[ET_TX_NDESC]; 466 467 int tbd_start_index; 468 int tbd_start_wrap; 469 int tbd_used; 470 }; 471 472 struct et_softc; 473 struct et_rxbuf_data; 474 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 475 476 struct et_rxbuf_data { 477 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 478 479 struct et_softc *rbd_softc; 480 struct et_rxdesc_ring *rbd_ring; 481 482 int rbd_bufsize; 483 et_newbuf_t rbd_newbuf; 484 }; 485 486 struct et_softc { 487 device_t sc_dev; 488 struct ethercom sc_ethercom; 489 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 490 u_short sc_if_flags; 491 uint32_t sc_flags; /* ET_FLAG_ */ 492 493 int sc_mem_rid; 494 struct resource *sc_mem_res; 495 bus_space_tag_t sc_mem_bt; 496 bus_space_handle_t sc_mem_bh; 497 bus_size_t sc_mem_size; 498 bus_dma_tag_t sc_dmat; 499 pci_chipset_tag_t sc_pct; 500 pcitag_t sc_pcitag; 501 502 int sc_irq_rid; 503 struct resource *sc_irq_res; 504 void *sc_irq_handle; 505 506 struct mii_data sc_miibus; 507 callout_t sc_tick; 508 509 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 510 struct et_rxstat_ring sc_rxstat_ring; 511 struct et_rxstatus_data sc_rx_status; 512 513 struct et_txdesc_ring sc_tx_ring; 514 struct et_txstatus_data sc_tx_status; 515 callout_t sc_txtick; 516 517 bus_dmamap_t sc_mbuf_tmp_dmap; 518 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 519 struct et_txbuf_data sc_tx_data; 520 521 uint32_t sc_tx; 522 uint32_t sc_tx_intr; 523 524 /* 525 * Sysctl variables 526 */ 527 int sc_rx_intr_npkts; 528 int sc_rx_intr_delay; 529 int sc_tx_intr_nsegs; 530 uint32_t sc_timer; 531 }; 532 533 #define ET_FLAG_FASTETHER 0x0004 534 #define ET_FLAG_TXRX_ENABLED 0x0100 535 #define ET_FLAG_LINK 0x8000 536 537 #endif /* !_IF_ETREG_H */ 538
Indexes created Mon Sep 29 21:09:56 GMT 2025