1 /* $NetBSD: fpu_emulate.c,v 1.50 2026/10/31 20:14:20 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Gordon W. Ross 5 * some portion Copyright (c) 1995 Ken Nakata 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 4. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Gordon Ross 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * mc68881 emulator 36 * XXX - Just a start at it for now... 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: fpu_emulate.c,v 1.50 2026/10/31 20:14:20 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/types.h> 44 #include <sys/signal.h> 45 #include <sys/systm.h> 46 #include <machine/frame.h> 47 48 #if defined(DDB) && defined(DEBUG_FPE) 49 # include <m68k/db_machdep.h> 50 #endif 51 52 #include "fpu_emulate.h" 53 54 #define fpe_abort(tfp, ksi, signo, code) \ 55 do { \ 56 (ksi)->ksi_signo = (signo); \ 57 (ksi)->ksi_code = (code); \ 58 (ksi)->ksi_addr = (void *)(frame)->f_pc; \ 59 return -1; \ 60 } while (/* CONSTCOND */ 0) 61 62 static int fpu_emul_fmovmcr(struct fpemu *, struct instruction *); 63 static int fpu_emul_fmovm(struct fpemu *, struct instruction *); 64 static int fpu_emul_arith(struct fpemu *, struct instruction *); 65 static int fpu_emul_type1(struct fpemu *, struct instruction *); 66 static int fpu_emul_brcc(struct fpemu *, struct instruction *); 67 static int test_cc(struct fpemu *, int); 68 69 #ifdef DEBUG_FPE 70 #define DUMP_INSN(insn) \ 71 printf("%s: insn={adv=%d,siz=%d,op=%04x,w1=%04x}\n", \ 72 __func__, \ 73 (insn)->is_advance, (insn)->is_datasize, \ 74 (insn)->is_opcode, (insn)->is_word1) 75 #define DPRINTF(x) printf x 76 #else 77 #define DUMP_INSN(insn) do {} while (/* CONSTCOND */ 0) 78 #define DPRINTF(x) do {} while (/* CONSTCOND */ 0) 79 #endif 80 81 /* 82 * Emulate a floating-point instruction. 83 * Return zero for success, else signal number. 84 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 85 */ 86 int 87 fpu_emulate(struct frame *frame, struct fpframe *fpf, ksiginfo_t *ksi) 88 { 89 static struct instruction insn; 90 static struct fpemu fe; 91 int optype, sig; 92 unsigned short sval; 93 94 /* initialize insn.is_datasize to tell it is *not* initialized */ 95 insn.is_datasize = -1; 96 97 fe.fe_frame = frame; 98 fe.fe_fpframe = fpf; 99 fe.fe_fpsr = fpf->fpf_fpsr; 100 fe.fe_fpcr = fpf->fpf_fpcr; 101 102 DPRINTF(("%s: ENTERING: FPSR=%08x, FPCR=%08x\n", 103 __func__, fe.fe_fpsr, fe.fe_fpcr)); 104 105 /* always set this (to avoid a warning) */ 106 insn.is_pc = frame->f_pc; 107 insn.is_nextpc = 0; 108 if (frame->f_format == 4) { 109 /* 110 * A format 4 is generated by the 68{EC,LC}040. The PC is 111 * already set to the instruction following the faulting 112 * instruction. We need to calculate that, anyway. The 113 * fslw is the PC of the faulted instruction, which is what 114 * we expect to be in f_pc. 115 * 116 * XXX - This is a hack; it assumes we at least know the 117 * sizes of all instructions we run across. 118 * XXX TODO: This may not be true, so we might want to save 119 * the PC in order to restore it later. 120 */ 121 #if 0 122 insn.is_nextpc = frame->f_pc; 123 #endif 124 insn.is_pc = frame->f_fmt4.f_fslw; 125 frame->f_pc = insn.is_pc; 126 } 127 128 if (ufetch_short((void *)(insn.is_pc), &sval)) { 129 DPRINTF(("%s: fault reading opcode\n", __func__)); 130 fpe_abort(frame, ksi, SIGSEGV, SEGV_ACCERR); 131 } 132 133 if ((sval & 0xf000) != 0xf000) { 134 DPRINTF(("%s: not coproc. insn.: opcode=0x%x\n", 135 __func__, sval)); 136 fpe_abort(frame, ksi, SIGILL, ILL_ILLOPC); 137 } 138 139 if ((sval & 0x0E00) != 0x0200) { 140 DPRINTF(("%s: bad coproc. id: opcode=0x%x\n", __func__, sval)); 141 fpe_abort(frame, ksi, SIGILL, ILL_ILLOPC); 142 } 143 144 insn.is_opcode = sval; 145 optype = (sval & 0x01C0); 146 147 if (ufetch_short((void *)(insn.is_pc + 2), &sval)) { 148 DPRINTF(("%s: fault reading word1\n", __func__)); 149 fpe_abort(frame, ksi, SIGSEGV, SEGV_ACCERR); 150 } 151 152 /* 153 * At this point, we know we're going to execute some sort of 154 * FP instruction. Set the FP frame state to mimic 68881 155 * idle state so that other logic elsewhere can interact with 156 * the FP state in the PCB in natural way. 157 * 158 * If a program never executes an (emulated) FP instruction, then 159 * the version field will remain 0, and e.g. cpu_getmcontext() 160 * won't bother to save it. 161 */ 162 fpf->fpf_version = 0x1f; 163 fpf->fpf_fsize = 0x18; 164 165 insn.is_word1 = sval; 166 /* all FPU instructions are at least 4-byte long */ 167 insn.is_advance = 4; 168 169 DUMP_INSN(&insn); 170 171 /* 172 * Which family (or type) of opcode is it? 173 * Tests ordered by likelihood (hopefully). 174 * Certainly, type 0 is the most common. 175 */ 176 if (optype == 0x0000) { 177 /* type=0: generic */ 178 if ((sval & 0x8000)) { 179 if ((sval & 0x4000)) { 180 DPRINTF(("%s: fmovm FPr\n", __func__)); 181 sig = fpu_emul_fmovm(&fe, &insn); 182 } else { 183 DPRINTF(("%s: fmovm FPcr\n", __func__)); 184 sig = fpu_emul_fmovmcr(&fe, &insn); 185 } 186 } else { 187 if ((sval & 0xe000) == 0x6000) { 188 /* fstore = fmove FPn,mem */ 189 DPRINTF(("%s: fmove to mem\n", __func__)); 190 sig = fpu_emul_fstore(&fe, &insn); 191 } else if ((sval & 0xfc00) == 0x5c00) { 192 /* fmovecr */ 193 DPRINTF(("%s: fmovecr\n", __func__)); 194 sig = fpu_emul_fmovecr(&fe, &insn); 195 } else if ((sval & 0xa07f) == 0x26) { 196 /* fscale */ 197 DPRINTF(("%s: fscale\n", __func__)); 198 sig = fpu_emul_fscale(&fe, &insn); 199 } else { 200 DPRINTF(("%s: other type0\n", __func__)); 201 /* all other type0 insns are arithmetic */ 202 sig = fpu_emul_arith(&fe, &insn); 203 } 204 if (sig == 0) { 205 DPRINTF(("%s: type 0 returned 0\n", __func__)); 206 sig = fpu_upd_excp(&fe); 207 } 208 } 209 } else if (optype == 0x0080 || optype == 0x00C0) { 210 /* type=2 or 3: fbcc, short or long disp. */ 211 DPRINTF(("%s: fbcc %s\n", __func__, 212 (optype & 0x40) ? "long" : "short")); 213 sig = fpu_emul_brcc(&fe, &insn); 214 } else if (optype == 0x0040) { 215 /* type=1: fdbcc, fscc, ftrapcc */ 216 DPRINTF(("%s: type1\n", __func__)); 217 sig = fpu_emul_type1(&fe, &insn); 218 /* real FTRAPcc raises T_TRAPVINST if the condition is met. */ 219 if (sig == SIGFPE) { 220 ksi->ksi_trap = T_TRAPVINST; 221 } 222 } else { 223 /* type=4: fsave (privileged) */ 224 /* type=5: frestore (privileged) */ 225 /* type=6: reserved */ 226 /* type=7: reserved */ 227 DPRINTF(("%s: bad opcode type: opcode=0x%x\n", __func__, 228 insn.is_opcode)); 229 sig = SIGILL; 230 } 231 232 DUMP_INSN(&insn); 233 234 /* 235 * XXX it is not clear to me, if we should progress the PC always, 236 * for SIGFPE || 0, or only for 0; however, without SIGFPE, we 237 * don't pass the signalling regression tests. -is 238 */ 239 if ((sig == 0) || (sig == SIGFPE)) 240 frame->f_pc += insn.is_advance; 241 #if defined(DDB) && defined(DEBUG_FPE) 242 else { 243 printf("%s: sig=%d, opcode=%x, word1=%x\n", __func__, 244 sig, insn.is_opcode, insn.is_word1); 245 kdb_trap(-1, (db_regs_t *)&frame); 246 } 247 #endif 248 #if 0 /* XXX something is wrong */ 249 if (frame->f_format == 4) { 250 /* XXX Restore PC -- 68{EC,LC}040 only */ 251 if (insn.is_nextpc) 252 frame->f_pc = insn.is_nextpc; 253 } 254 #endif 255 256 DPRINTF(("%s: EXITING: w/FPSR=%08x, FPCR=%08x\n", __func__, 257 fe.fe_fpsr, fe.fe_fpcr)); 258 259 if (sig) 260 fpe_abort(frame, ksi, sig, 0); 261 return sig; 262 } 263 264 /* update accrued exception bits and see if there's an FP exception */ 265 int 266 fpu_upd_excp(struct fpemu *fe) 267 { 268 uint32_t fpsr; 269 uint32_t fpcr; 270 271 fpsr = fe->fe_fpsr; 272 fpcr = fe->fe_fpcr; 273 /* 274 * update fpsr accrued exception bits; each insn doesn't have to 275 * update this 276 */ 277 if (fpsr & (FPSR_BSUN | FPSR_SNAN | FPSR_OPERR)) { 278 fpsr |= FPSR_AIOP; 279 } 280 if (fpsr & FPSR_OVFL) { 281 fpsr |= FPSR_AOVFL; 282 } 283 if ((fpsr & FPSR_UNFL) && (fpsr & FPSR_INEX2)) { 284 fpsr |= FPSR_AUNFL; 285 } 286 if (fpsr & FPSR_DZ) { 287 fpsr |= FPSR_ADZ; 288 } 289 if (fpsr & (FPSR_INEX1 | FPSR_INEX2 | FPSR_OVFL)) { 290 fpsr |= FPSR_AINEX; 291 } 292 293 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 294 295 return (fpsr & fpcr & FPSR_EXCP) ? SIGFPE : 0; 296 } 297 298 /* update fpsr according to fp (= result of an fp op) */ 299 uint32_t 300 fpu_upd_fpsr(struct fpemu *fe, struct fpn *fp) 301 { 302 uint32_t fpsr; 303 304 DPRINTF(("%s: previous fpsr=%08x\n", __func__, fe->fe_fpsr)); 305 /* clear all condition code */ 306 fpsr = fe->fe_fpsr & ~FPSR_CCB; 307 308 DPRINTF(("%s: result is a ", __func__)); 309 if (fp->fp_sign) { 310 DPRINTF(("negative ")); 311 fpsr |= FPSR_NEG; 312 } else { 313 DPRINTF(("positive ")); 314 } 315 316 switch (fp->fp_class) { 317 case FPC_SNAN: 318 DPRINTF(("signaling NAN\n")); 319 fpsr |= (FPSR_NAN | FPSR_SNAN); 320 break; 321 case FPC_QNAN: 322 DPRINTF(("quiet NAN\n")); 323 fpsr |= FPSR_NAN; 324 break; 325 case FPC_ZERO: 326 DPRINTF(("Zero\n")); 327 fpsr |= FPSR_ZERO; 328 break; 329 case FPC_INF: 330 DPRINTF(("Inf\n")); 331 fpsr |= FPSR_INF; 332 break; 333 default: 334 DPRINTF(("Number\n")); 335 /* anything else is treated as if it is a number */ 336 break; 337 } 338 339 fe->fe_fpsr = fe->fe_fpframe->fpf_fpsr = fpsr; 340 341 DPRINTF(("%s: new fpsr=%08x\n", __func__, fe->fe_fpframe->fpf_fpsr)); 342 343 return fpsr; 344 } 345 346 static int 347 fpu_emul_fmovmcr(struct fpemu *fe, struct instruction *insn) 348 { 349 struct frame *frame = fe->fe_frame; 350 struct fpframe *fpf = fe->fe_fpframe; 351 int sig; 352 int reglist; 353 int regcount; 354 int fpu_to_mem; 355 int modreg; 356 uint32_t tmp[3]; 357 358 /* move to/from control registers */ 359 reglist = (insn->is_word1 & 0x1c00) >> 10; 360 /* Bit 13 selects direction (FPU to/from Mem) */ 361 fpu_to_mem = insn->is_word1 & 0x2000; 362 363 /* Check an illegal mod/reg. */ 364 modreg = insn->is_opcode & 077; 365 if (fpu_to_mem) { 366 /* PCrel, #imm are illegal. */ 367 if (modreg >= 072) { 368 return SIGILL; 369 } 370 } else { 371 /* All mod/reg can be specified. */ 372 if (modreg >= 075) { 373 return SIGILL; 374 } 375 } 376 377 /* 378 * If reglist is 0b000, treat it as FPIAR. This is not specification 379 * but the behavior described in the 6888x user's manual. 380 */ 381 if (reglist == 0) 382 reglist = 1; 383 384 if (reglist == 7) { 385 regcount = 3; 386 } else if (reglist == 3 || reglist == 5 || reglist == 6) { 387 regcount = 2; 388 } else { 389 regcount = 1; 390 } 391 insn->is_datasize = regcount * 4; 392 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg); 393 if (sig) 394 return sig; 395 396 /* 397 * For data register, only single register can be transferred. 398 * For addr register, only FPIAR can be transferred. 399 */ 400 if ((insn->is_ea.ea_flags & EA_DIRECT)) { 401 if (insn->is_ea.ea_regnum < 8) { 402 if (regcount != 1) { 403 return SIGILL; 404 } 405 } else { 406 if (reglist != 1) { 407 return SIGILL; 408 } 409 } 410 } 411 412 if (fpu_to_mem) { 413 uint32_t *s = &tmp[0]; 414 415 if ((reglist & 4)) { 416 *s++ = fpf->fpf_fpcr; 417 } 418 if ((reglist & 2)) { 419 *s++ = fpf->fpf_fpsr; 420 } 421 if ((reglist & 1)) { 422 *s++ = fpf->fpf_fpiar; 423 } 424 425 sig = fpu_store_ea(frame, insn, &insn->is_ea, (char *)tmp); 426 } else { 427 const uint32_t *d = &tmp[0]; 428 429 sig = fpu_load_ea(frame, insn, &insn->is_ea, (char *)tmp); 430 if (sig) 431 return sig; 432 433 if ((reglist & 4)) { 434 fpf->fpf_fpcr = *d++; 435 fpf->fpf_fpcr &= 0x0000fff0; 436 } 437 if ((reglist & 2)) { 438 fpf->fpf_fpsr = *d++; 439 fpf->fpf_fpsr &= 0x0ffffff8; 440 } 441 if ((reglist & 1)) { 442 fpf->fpf_fpiar = *d++; 443 } 444 } 445 return sig; 446 } 447 448 /* 449 * type 0: fmovem 450 * Separated out of fpu_emul_type0 for efficiency. 451 * In this function, we know: 452 * (opcode & 0x01C0) == 0 453 * (word1 & 0x8000) == 0x8000 454 * 455 * No conversion or rounding is done by this instruction, 456 * and the FPSR is not affected. 457 */ 458 static int 459 fpu_emul_fmovm(struct fpemu *fe, struct instruction *insn) 460 { 461 struct frame *frame = fe->fe_frame; 462 struct fpframe *fpf = fe->fe_fpframe; 463 int word1, sig; 464 int reglist, regmask, regnum; 465 int modreg; 466 int fpu_to_mem, order; 467 /* int w1_post_incr; */ 468 int *fpregs; 469 470 insn->is_datasize = 12; 471 word1 = insn->is_word1; 472 473 /* Bit 13 selects direction (FPU to/from Mem) */ 474 fpu_to_mem = word1 & 0x2000; 475 476 /* 477 * Bits 12,11 select register list mode: 478 * 0,0: Static reg list, pre-decr. 479 * 0,1: Dynamic reg list, pre-decr. 480 * 1,0: Static reg list, post-incr. 481 * 1,1: Dynamic reg list, post-incr 482 */ 483 /* w1_post_incr = word1 & 0x1000; */ 484 if (word1 & 0x0800) { 485 /* dynamic reg list */ 486 reglist = frame->f_regs[(word1 & 0x70) >> 4]; 487 } else { 488 reglist = word1; 489 } 490 reglist &= 0xFF; 491 492 /* Check an illegal mod/reg. */ 493 modreg = insn->is_opcode & 077; 494 if (fpu_to_mem) { 495 /* Dn, An, (An)+, PCrel, #imm are illegal. */ 496 if (modreg < 020 || (modreg >> 3) == 3 || modreg >= 072) { 497 return SIGILL; 498 } 499 } else { 500 /* Dn, An, -(An), #imm are illegal. */ 501 if (modreg < 020 || (modreg >> 3) == 4 || modreg >= 074) { 502 return SIGILL; 503 } 504 } 505 506 /* Get effective address. */ 507 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg); 508 if (sig) 509 return sig; 510 511 /* Get address of soft coprocessor regs. */ 512 fpregs = &fpf->fpf_regs[0]; 513 514 if (insn->is_ea.ea_flags & EA_PREDECR) { 515 regnum = 7; 516 order = -1; 517 } else { 518 regnum = 0; 519 order = 1; 520 } 521 522 regmask = 0x80; 523 while ((0 <= regnum) && (regnum < 8)) { 524 if (regmask & reglist) { 525 if (fpu_to_mem) { 526 sig = fpu_store_ea(frame, insn, &insn->is_ea, 527 (char *)&fpregs[regnum * 3]); 528 DPRINTF(("%s: FP%d (%08x,%08x,%08x) saved\n", 529 __func__, regnum, 530 fpregs[regnum * 3], 531 fpregs[regnum * 3 + 1], 532 fpregs[regnum * 3 + 2])); 533 } else { /* mem to fpu */ 534 sig = fpu_load_ea(frame, insn, &insn->is_ea, 535 (char *)&fpregs[regnum * 3]); 536 DPRINTF(("%s: FP%d (%08x,%08x,%08x) loaded\n", 537 __func__, regnum, 538 fpregs[regnum * 3], 539 fpregs[regnum * 3 + 1], 540 fpregs[regnum * 3 + 2])); 541 } 542 if (sig) 543 break; 544 } 545 regnum += order; 546 regmask >>= 1; 547 } 548 549 return sig; 550 } 551 552 struct fpn * 553 fpu_cmp(struct fpemu *fe) 554 { 555 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2; 556 557 /* take care of special cases */ 558 if (x->fp_class < 0 || y->fp_class < 0) { 559 /* if either of two is a SNAN, result is SNAN */ 560 x->fp_class = 561 (y->fp_class < x->fp_class) ? y->fp_class : x->fp_class; 562 } else if (x->fp_class == FPC_INF) { 563 if (y->fp_class == FPC_INF) { 564 /* both infinities */ 565 if (x->fp_sign == y->fp_sign) { 566 /* return a signed zero */ 567 x->fp_class = FPC_ZERO; 568 } else { 569 /* return a faked number w/x's sign */ 570 x->fp_class = FPC_NUM; 571 x->fp_exp = 16383; 572 x->fp_mant[0] = FP_1; 573 } 574 } else { 575 /* y is a number */ 576 /* return a forged number w/x's sign */ 577 x->fp_class = FPC_NUM; 578 x->fp_exp = 16383; 579 x->fp_mant[0] = FP_1; 580 } 581 } else if (y->fp_class == FPC_INF) { 582 /* x is a Num but y is an Inf */ 583 /* return a forged number w/y's sign inverted */ 584 x->fp_class = FPC_NUM; 585 x->fp_sign = !y->fp_sign; 586 x->fp_exp = 16383; 587 x->fp_mant[0] = FP_1; 588 } else { 589 /* 590 * x and y are both numbers or zeros, 591 * or pair of a number and a zero 592 */ 593 y->fp_sign = !y->fp_sign; 594 x = fpu_add(fe); /* (x - y) */ 595 /* 596 * FCMP does not set Inf bit in CC, so return a forged number 597 * (value doesn't matter) if Inf is the result of fsub. 598 */ 599 if (x->fp_class == FPC_INF) { 600 x->fp_class = FPC_NUM; 601 x->fp_exp = 16383; 602 x->fp_mant[0] = FP_1; 603 } 604 } 605 return x; 606 } 607 608 /* 609 * arithmetic operations 610 */ 611 static int 612 fpu_emul_arith(struct fpemu *fe, struct instruction *insn) 613 { 614 struct frame *frame = fe->fe_frame; 615 uint32_t *fpregs = &(fe->fe_fpframe->fpf_regs[0]); 616 struct fpn *res; 617 int word1, sig = 0; 618 int regnum, format; 619 int modreg; 620 int discard_result = 0; 621 uint32_t buf[3]; 622 #ifdef DEBUG_FPE 623 int flags; 624 char regname; 625 #endif 626 627 fe->fe_fpsr &= ~FPSR_EXCP; 628 629 DUMP_INSN(insn); 630 631 DPRINTF(("%s: FPSR = %08x, FPCR = %08x\n", __func__, 632 fe->fe_fpsr, fe->fe_fpcr)); 633 634 word1 = insn->is_word1; 635 format = (word1 >> 10) & 7; 636 regnum = (word1 >> 7) & 7; 637 638 /* fetch a source operand : may not be used */ 639 DPRINTF(("%s: dst/src FP%d=%08x,%08x,%08x\n", __func__, 640 regnum, fpregs[regnum * 3], fpregs[regnum * 3 + 1], 641 fpregs[regnum * 3 + 2])); 642 643 fpu_explode(fe, &fe->fe_f1, FTYPE_EXT, &fpregs[regnum * 3]); 644 645 DUMP_INSN(insn); 646 647 /* get the other operand which is always the source */ 648 if ((word1 & 0x4000) == 0) { 649 DPRINTF(("%s: FP%d op FP%d => FP%d\n", __func__, 650 format, regnum, regnum)); 651 DPRINTF(("%s: src opr FP%d=%08x,%08x,%08x\n", __func__, 652 format, fpregs[format * 3], fpregs[format * 3 + 1], 653 fpregs[format * 3 + 2])); 654 fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]); 655 } else { 656 /* the operand is in memory */ 657 if (format == FTYPE_DBL) { 658 insn->is_datasize = 8; 659 } else if (format == FTYPE_SNG || format == FTYPE_LNG) { 660 insn->is_datasize = 4; 661 } else if (format == FTYPE_WRD) { 662 insn->is_datasize = 2; 663 } else if (format == FTYPE_BYT) { 664 insn->is_datasize = 1; 665 } else if (format == FTYPE_EXT) { 666 insn->is_datasize = 12; 667 } else { 668 /* invalid or unsupported operand format */ 669 sig = SIGFPE; 670 return sig; 671 } 672 673 /* Check an illegal mod/reg. */ 674 modreg = insn->is_opcode & 077; 675 if ((modreg >> 3) == 1/*An*/ || modreg >= 075) { 676 return SIGILL; 677 } 678 679 /* Get effective address. */ 680 sig = fpu_decode_ea(frame, insn, &insn->is_ea, modreg); 681 if (sig) { 682 DPRINTF(("%s: error in fpu_decode_ea\n", __func__)); 683 return sig; 684 } 685 686 if (insn->is_ea.ea_flags == EA_DIRECT && 687 insn->is_datasize > 4) { 688 DPRINTF(("%s: attempted to fetch dbl/ext from reg\n", 689 __func__)); 690 return SIGILL; 691 } 692 693 DUMP_INSN(insn); 694 695 #ifdef DEBUG_FPE 696 printf("%s: addr mode = ", __func__); 697 flags = insn->is_ea.ea_flags; 698 regname = (insn->is_ea.ea_regnum & 8) ? 'a' : 'd'; 699 700 if (flags & EA_DIRECT) { 701 printf("%c%d\n", regname, insn->is_ea.ea_regnum & 7); 702 } else if (flags & EA_PC_REL) { 703 if (flags & EA_OFFSET) { 704 printf("pc@(%d)\n", insn->is_ea.ea_offset); 705 } else if (flags & EA_INDEXED) { 706 printf("pc@(...)\n"); 707 } 708 } else if (flags & EA_PREDECR) { 709 printf("%c%d@-\n", regname, insn->is_ea.ea_regnum & 7); 710 } else if (flags & EA_POSTINCR) { 711 printf("%c%d@+\n", regname, insn->is_ea.ea_regnum & 7); 712 } else if (flags & EA_OFFSET) { 713 printf("%c%d@(%d)\n", regname, 714 insn->is_ea.ea_regnum & 7, 715 insn->is_ea.ea_offset); 716 } else if (flags & EA_INDEXED) { 717 printf("%c%d@(...)\n", regname, 718 insn->is_ea.ea_regnum & 7); 719 } else if (flags & EA_ABS) { 720 printf("0x%08x\n", insn->is_ea.ea_absaddr); 721 } else if (flags & EA_IMMED) { 722 printf("#0x%08x,%08x,%08x\n", 723 insn->is_ea.ea_immed[0], 724 insn->is_ea.ea_immed[1], 725 insn->is_ea.ea_immed[2]); 726 } else { 727 printf("%c%d@\n", regname, insn->is_ea.ea_regnum & 7); 728 } 729 #endif /* DEBUG_FPE */ 730 731 fpu_load_ea(frame, insn, &insn->is_ea, (char*)buf); 732 if (format == FTYPE_WRD) { 733 /* sign-extend */ 734 buf[0] &= 0xffff; 735 if (buf[0] & 0x8000) 736 buf[0] |= 0xffff0000; 737 format = FTYPE_LNG; 738 } else if (format == FTYPE_BYT) { 739 /* sign-extend */ 740 buf[0] &= 0xff; 741 if (buf[0] & 0x80) 742 buf[0] |= 0xffffff00; 743 format = FTYPE_LNG; 744 } 745 DPRINTF(("%s: src = %08x %08x %08x, siz = %d\n", __func__, 746 buf[0], buf[1], buf[2], insn->is_datasize)); 747 fpu_explode(fe, &fe->fe_f2, format, buf); 748 } 749 750 DUMP_INSN(insn); 751 752 /* 753 * An arithmetic instruction emulate function has a prototype of 754 * struct fpn *fpu_op(struct fpemu *); 755 * 756 * 1) If the instruction is monadic, then fpu_op() must use 757 * fe->fe_f2 as its operand, and return a pointer to the 758 * result. 759 * 760 * 2) If the instruction is diadic, then fpu_op() must use 761 * fe->fe_f1 and fe->fe_f2 as its two operands, and return a 762 * pointer to the result. 763 * 764 */ 765 res = NULL; 766 switch (word1 & 0x7f) { 767 case 0x00: /* fmove */ 768 res = &fe->fe_f2; 769 break; 770 771 case 0x01: /* fint */ 772 res = fpu_int(fe); 773 break; 774 775 case 0x02: /* fsinh */ 776 res = fpu_sinh(fe); 777 break; 778 779 case 0x03: /* fintrz */ 780 res = fpu_intrz(fe); 781 break; 782 783 case 0x04: /* fsqrt */ 784 res = fpu_sqrt(fe); 785 break; 786 787 case 0x06: /* flognp1 */ 788 res = fpu_lognp1(fe); 789 break; 790 791 case 0x08: /* fetoxm1 */ 792 res = fpu_etoxm1(fe); 793 break; 794 795 case 0x09: /* ftanh */ 796 res = fpu_tanh(fe); 797 break; 798 799 case 0x0A: /* fatan */ 800 res = fpu_atan(fe); 801 break; 802 803 case 0x0C: /* fasin */ 804 res = fpu_asin(fe); 805 break; 806 807 case 0x0D: /* fatanh */ 808 res = fpu_atanh(fe); 809 break; 810 811 case 0x0E: /* fsin */ 812 res = fpu_sin(fe); 813 break; 814 815 case 0x0F: /* ftan */ 816 res = fpu_tan(fe); 817 break; 818 819 case 0x10: /* fetox */ 820 res = fpu_etox(fe); 821 break; 822 823 case 0x11: /* ftwotox */ 824 res = fpu_twotox(fe); 825 break; 826 827 case 0x12: /* ftentox */ 828 res = fpu_tentox(fe); 829 break; 830 831 case 0x14: /* flogn */ 832 res = fpu_logn(fe); 833 break; 834 835 case 0x15: /* flog10 */ 836 res = fpu_log10(fe); 837 break; 838 839 case 0x16: /* flog2 */ 840 res = fpu_log2(fe); 841 break; 842 843 case 0x18: /* fabs */ 844 fe->fe_f2.fp_sign = 0; 845 res = &fe->fe_f2; 846 break; 847 848 case 0x19: /* fcosh */ 849 res = fpu_cosh(fe); 850 break; 851 852 case 0x1A: /* fneg */ 853 fe->fe_f2.fp_sign = !fe->fe_f2.fp_sign; 854 res = &fe->fe_f2; 855 break; 856 857 case 0x1C: /* facos */ 858 res = fpu_acos(fe); 859 break; 860 861 case 0x1D: /* fcos */ 862 res = fpu_cos(fe); 863 break; 864 865 case 0x1E: /* fgetexp */ 866 res = fpu_getexp(fe); 867 break; 868 869 case 0x1F: /* fgetman */ 870 res = fpu_getman(fe); 871 break; 872 873 case 0x20: /* fdiv */ 874 case 0x24: /* fsgldiv: cheating - better than nothing */ 875 res = fpu_div(fe); 876 break; 877 878 case 0x21: /* fmod */ 879 res = fpu_mod(fe); 880 break; 881 882 case 0x28: /* fsub */ 883 fe->fe_f2.fp_sign = !fe->fe_f2.fp_sign; /* f2 = -f2 */ 884 /* FALLTHROUGH */ 885 case 0x22: /* fadd */ 886 res = fpu_add(fe); 887 break; 888 889 case 0x23: /* fmul */ 890 case 0x27: /* fsglmul: cheating - better than nothing */ 891 res = fpu_mul(fe); 892 break; 893 894 case 0x25: /* frem */ 895 res = fpu_rem(fe); 896 break; 897 898 case 0x26: 899 /* fscale is handled by a separate function */ 900 break; 901 902 case 0x30: 903 case 0x31: 904 case 0x32: 905 case 0x33: 906 case 0x34: 907 case 0x35: 908 case 0x36: 909 case 0x37: /* fsincos */ 910 res = fpu_sincos(fe, word1 & 7); 911 break; 912 913 case 0x38: /* fcmp */ 914 res = fpu_cmp(fe); 915 discard_result = 1; 916 break; 917 918 case 0x3A: /* ftst */ 919 res = &fe->fe_f2; 920 discard_result = 1; 921 break; 922 923 default: /* possibly 040/060 instructions */ 924 DPRINTF(("%s: bad opcode=0x%x, word1=0x%x\n", __func__, 925 insn->is_opcode, insn->is_word1)); 926 sig = SIGILL; 927 } 928 929 /* for sanity */ 930 if (res == NULL) 931 sig = SIGILL; 932 933 if (sig == 0) { 934 if (!discard_result) 935 fpu_implode(fe, res, FTYPE_EXT, &fpregs[regnum * 3]); 936 937 /* update fpsr according to the result of operation */ 938 fpu_upd_fpsr(fe, res); 939 #ifdef DEBUG_FPE 940 if (!discard_result) { 941 printf("%s: %08x,%08x,%08x stored in FP%d\n", __func__, 942 fpregs[regnum * 3], 943 fpregs[regnum * 3 + 1], 944 fpregs[regnum * 3 + 2], 945 regnum); 946 } else { 947 static const char *class_name[] = 948 { "SNAN", "QNAN", "ZERO", "NUM", "INF" }; 949 printf("%s: result(%s,%c,%d,%08x,%08x,%08x) " 950 "discarded\n", __func__, 951 class_name[res->fp_class + 2], 952 res->fp_sign ? '-' : '+', res->fp_exp, 953 res->fp_mant[0], res->fp_mant[1], 954 res->fp_mant[2]); 955 } 956 #endif 957 } else { 958 DPRINTF(("%s: received signal %d\n", __func__, sig)); 959 } 960 961 DPRINTF(("%s: FPSR = %08x, FPCR = %08x\n", __func__, 962 fe->fe_fpsr, fe->fe_fpcr)); 963 964 DUMP_INSN(insn); 965 966 return sig; 967 } 968 969 /* 970 * test condition code according to the predicate in the opcode. 971 * returns -1 when the predicate evaluates to true, 0 when false. 972 * signal numbers are returned when an error is detected. 973 */ 974 static int 975 test_cc(struct fpemu *fe, int pred) 976 { 977 int result, sig_bsun; 978 int fpsr; 979 980 fpsr = fe->fe_fpsr; 981 DPRINTF(("%s: fpsr=0x%08x\n", __func__, fpsr)); 982 pred &= 0x3f; /* lowest 6 bits */ 983 984 DPRINTF(("%s: ", __func__)); 985 986 if (pred >= 0x20) { 987 DPRINTF(("Illegal condition code\n")); 988 return SIGILL; 989 } else if (pred & 0x10) { 990 /* IEEE nonaware tests */ 991 sig_bsun = 1; 992 pred &= 0x0f; /* lower 4 bits */ 993 } else { 994 /* IEEE aware tests */ 995 DPRINTF(("IEEE ")); 996 sig_bsun = 0; 997 } 998 999 /* 1000 * condition real 68882 1001 * mnemonic in manual condition 1002 * -------- ---------- ---------- 1003 * 0000 F 0 <- = ~NAN & 0 & ~Z | 0 1004 * 0001 EQ Z <- = ~NAN & 0 | Z | 0 1005 * 0010 OGT ~(NAN|Z|N) <- = ~NAN & ~N & ~Z | 0 1006 * 0011 OGE Z|~(NAN|N) <- = ~NAN & ~N | Z | 0 1007 * 0100 OLT N&~(NAN|Z) <- = ~NAN & N & ~Z | 0 1008 * 0101 OLE Z|(N&~NAN) <- = ~NAN & N | Z | 0 1009 * 0110 OGL ~(NAN|Z) <- = ~NAN & 1 & ~Z | 0 1010 * 0111 OR ~NAN Z|~NAN = ~NAN & 1 | Z | 0 1011 * 1012 * 1000 UN NAN <- = 1 & 0 & ~Z | NAN 1013 * 1001 UEQ NAN|Z <- = 1 & 0 | Z | NAN 1014 * 1010 UGT NAN|~(N|Z) <- = 1 & ~N & ~Z | NAN 1015 * 1011 UGE NAN|(Z|~N) <- = 1 & ~N | Z | NAN 1016 * 1100 ULT NAN|(N&~Z) <- = 1 & N & ~Z | NAN 1017 * 1101 ULE NAN|(Z|N) <- = 1 & N | Z | NAN 1018 * 1110 NE ~Z NAN|(~Z) = 1 & 1 & ~Z | NAN 1019 * 1111 T 1 <- = 1 & 1 | Z | NAN 1020 */ 1021 if ((pred & 0x08) == 0) { 1022 result = ((fpsr & FPSR_NAN) == 0); 1023 } else { 1024 result = 1; 1025 } 1026 switch (pred & 0x06) { 1027 case 0x00: /* AND 0 */ 1028 result &= 0; 1029 break; 1030 case 0x02: /* AND ~N */ 1031 result &= ((fpsr & FPSR_NEG) == 0); 1032 break; 1033 case 0x04: /* AND N */ 1034 result &= ((fpsr & FPSR_NEG) != 0); 1035 break; 1036 case 0x06: /* AND 1 */ 1037 result &= 1; 1038 break; 1039 } 1040 if ((pred & 0x01) == 0) { 1041 result &= ((fpsr & FPSR_ZERO) == 0); 1042 } else { 1043 result |= ((fpsr & FPSR_ZERO) != 0); 1044 } 1045 if ((pred & 0x08) != 0) { 1046 result |= ((fpsr & FPSR_NAN) != 0); 1047 } 1048 1049 DPRINTF(("=> %s (%d)\n", result ? "true" : "false", result)); 1050 /* if it's an IEEE unaware test and NAN is set, BSUN is set */ 1051 if (sig_bsun && (fpsr & FPSR_NAN)) { 1052 fpsr |= FPSR_BSUN; 1053 } 1054 /* if BSUN is set, IOP is set too */ 1055 if ((fpsr & FPSR_BSUN)) { 1056 fpsr |= FPSR_AIOP; 1057 } 1058 1059 /* put fpsr back */ 1060 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr; 1061 1062 return -result; 1063 } 1064 1065 /* 1066 * type 1: fdbcc, fscc, ftrapcc 1067 * In this function, we know: 1068 * (opcode & 0x01C0) == 0x0040 1069 * return SIGILL for an illegal instruction. 1070 * return SIGFPE if FTRAPcc's condition is met. 1071 */ 1072 static int 1073 fpu_emul_type1(struct fpemu *fe, struct instruction *insn) 1074 { 1075 struct frame *frame = fe->fe_frame; 1076 int advance, sig, branch, displ; 1077 unsigned short sval; 1078 1079 branch = test_cc(fe, insn->is_word1); 1080 if (branch > 0) 1081 return branch; 1082 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr; 1083 1084 sig = 0; 1085 switch (insn->is_opcode & 070) { 1086 case 010: /* fdbcc */ 1087 if (branch) { 1088 /* advance */ 1089 insn->is_advance = 6; 1090 } else { 1091 /* decrement Dn and if (Dn != -1) branch */ 1092 uint16_t count = frame->f_regs[insn->is_opcode & 7]; 1093 1094 if (count-- != 0) { 1095 if (ufetch_short((void *)(insn->is_pc + 1096 insn->is_advance), 1097 &sval)) { 1098 DPRINTF(("%s: fault reading " 1099 "displacement\n", __func__)); 1100 return SIGSEGV; 1101 } 1102 displ = sval; 1103 /* sign-extend the displacement */ 1104 displ &= 0xffff; 1105 if (displ & 0x8000) { 1106 displ |= 0xffff0000; 1107 } 1108 insn->is_advance += displ; 1109 #if 0 /* XXX */ 1110 insn->is_nextpc = insn->is_pc + 1111 insn->is_advance; 1112 #endif 1113 } else { 1114 insn->is_advance = 6; 1115 } 1116 /* write it back */ 1117 frame->f_regs[insn->is_opcode & 7] &= 0xffff0000; 1118 frame->f_regs[insn->is_opcode & 7] |= (uint32_t)count; 1119 } 1120 break; 1121 1122 case 070: /* ftrapcc or fscc */ 1123 advance = 4; 1124 if ((insn->is_opcode & 07) >= 2) { 1125 switch (insn->is_opcode & 07) { 1126 case 3: /* long opr */ 1127 advance += 2; 1128 case 2: /* word opr */ 1129 advance += 2; 1130 case 4: /* no opr */ 1131 break; 1132 default: 1133 return SIGILL; 1134 break; 1135 } 1136 insn->is_advance = advance; 1137 1138 if (branch) { 1139 /* trap */ 1140 sig = SIGFPE; 1141 } 1142 break; 1143 } 1144 1145 /* FALLTHROUGH */ 1146 default: /* fscc */ 1147 insn->is_datasize = 1; /* always byte */ 1148 sig = fpu_decode_ea(frame, insn, &insn->is_ea, insn->is_opcode); 1149 if (sig) { 1150 break; 1151 } 1152 /* set result */ 1153 sig = fpu_store_ea(frame, insn, &insn->is_ea, (char *)&branch); 1154 break; 1155 } 1156 return sig; 1157 } 1158 1159 /* 1160 * Type 2 or 3: fbcc (also fnop) 1161 * In this function, we know: 1162 * (opcode & 0x0180) == 0x0080 1163 */ 1164 static int 1165 fpu_emul_brcc(struct fpemu *fe, struct instruction *insn) 1166 { 1167 int displ, word2; 1168 int sig; 1169 unsigned short sval; 1170 1171 /* 1172 * Get branch displacement. 1173 */ 1174 displ = insn->is_word1; 1175 1176 if (insn->is_opcode & 0x40) { 1177 if (ufetch_short((void *)(insn->is_pc + insn->is_advance), 1178 &sval)) { 1179 DPRINTF(("%s: fault reading word2\n", __func__)); 1180 return SIGSEGV; 1181 } 1182 word2 = sval; 1183 displ <<= 16; 1184 displ |= word2; 1185 insn->is_advance += 2; 1186 } else { 1187 /* displacement is word sized */ 1188 if (displ & 0x8000) 1189 displ |= 0xFFFF0000; 1190 } 1191 1192 /* XXX: If CC, insn->is_pc += displ */ 1193 sig = test_cc(fe, insn->is_opcode); 1194 fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr; 1195 1196 if (fe->fe_fpsr & fe->fe_fpcr & FPSR_EXCP) { 1197 return SIGFPE; /* caught an exception */ 1198 } 1199 if (sig == -1) { 1200 /* 1201 * branch does take place; 2 is the offset to the 1st disp word 1202 */ 1203 insn->is_advance = displ + 2; 1204 #if 0 /* XXX */ 1205 insn->is_nextpc = insn->is_pc + insn->is_advance; 1206 #endif 1207 } else if (sig) 1208 return SIGILL; /* got a signal */ 1209 DPRINTF(("%s: %s insn @ %x (%x+%x) (disp=%x)\n", __func__, 1210 (sig == -1) ? "BRANCH to" : "NEXT", 1211 insn->is_pc + insn->is_advance, insn->is_pc, insn->is_advance, 1212 displ)); 1213 return 0; 1214 } 1215
Indexes created Sun Nov 01 00:25:34 UTC 2026