1 /* $NetBSD: i80312_mainbus.c,v 1.16 2012/10/14 18:37:55 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * IQ80310 front-end for the i80312 Companion I/O chip. We take care 40 * of setting up the i80312 memory map, PCI interrupt routing, etc., 41 * which are all specific to the board the i80312 is wired up to. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: i80312_mainbus.c,v 1.16 2012/10/14 18:37:55 msaitoh Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 51 #include <machine/autoconf.h> 52 #include <sys/bus.h> 53 54 #include <evbarm/iq80310/iq80310reg.h> 55 #include <evbarm/iq80310/iq80310var.h> 56 57 #include <arm/xscale/i80312reg.h> 58 #include <arm/xscale/i80312var.h> 59 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 int i80312_mainbus_match(device_t, cfdata_t, void *); 64 void i80312_mainbus_attach(device_t, device_t, void *); 65 66 CFATTACH_DECL_NEW(iopxs_mainbus, sizeof(struct i80312_softc), 67 i80312_mainbus_match, i80312_mainbus_attach, NULL, NULL); 68 69 /* There can be only one. */ 70 int i80312_mainbus_found; 71 72 int 73 i80312_mainbus_match(device_t parent, cfdata_t cf, void *aux) 74 { 75 #if 0 76 struct mainbus_attach_args *ma = aux; 77 #endif 78 79 if (i80312_mainbus_found) 80 return (0); 81 82 #if 1 83 /* XXX Shoot arch/arm/mainbus in the head. */ 84 return (1); 85 #else 86 if (strcmp(cf->cf_name, ma->ma_name) == 0) 87 return (1); 88 89 return (0); 90 #endif 91 } 92 93 void 94 i80312_mainbus_attach(device_t parent, device_t self, void *aux) 95 { 96 struct i80312_softc *sc = device_private(self); 97 paddr_t memstart; 98 psize_t memsize; 99 100 i80312_mainbus_found = 1; 101 sc->sc_dev = self; 102 iq80310_intr_evcnt_attach(); 103 104 /* 105 * Fill in the space tag for the i80312's own devices, 106 * and hand-craft the space handle for it (the device 107 * was mapped during early bootstrap). 108 */ 109 i80312_bs_init(&i80312_bs_tag, sc); 110 sc->sc_st = &i80312_bs_tag; 111 sc->sc_sh = IQ80310_80312_VBASE; 112 113 /* 114 * Slice off a subregion for the Memory Controller -- we need it 115 * here in order read the memory size. 116 */ 117 if (bus_space_subregion(sc->sc_st, sc->sc_sh, I80312_MEM_BASE, 118 I80312_MEM_SIZE, &sc->sc_mem_sh)) 119 panic("%s: unable to subregion MEM registers", 120 device_xname(self)); 121 122 /* 123 * We have mapped the PCI I/O windows in the early bootstrap phase. 124 */ 125 sc->sc_piow_vaddr = IQ80310_PIOW_VBASE; 126 sc->sc_siow_vaddr = IQ80310_SIOW_VBASE; 127 128 /* Some boards are always considered "host". */ 129 #if defined(IOP310_TEAMASA_NPWR) 130 sc->sc_is_host = 1; 131 #else /* Default to stock IQ80310 */ 132 sc->sc_is_host = CPLD_READ(IQ80310_BACKPLANE_DET) & 1; 133 134 /* 135 * Set the subsystem vendor/device IDs to "Cyclone" "PCI-700", 136 * which is the board-specific identification. 137 */ 138 bus_space_write_4(sc->sc_st, sc->sc_sh, 139 I80312_ATU_BASE + PCI_SUBSYS_ID_REG, 140 PCI_ID_CODE(PCI_VENDOR_CYCLONE, PCI_PRODUCT_CYCLONE_PCI_700)); 141 #endif 142 143 printf(": i80312 Companion I/O, acting as PCI %s\n", 144 sc->sc_is_host ? "host" : "slave"); 145 146 i80312_sdram_bounds(sc->sc_st, sc->sc_mem_sh, &memstart, &memsize); 147 148 /* 149 * Set the Primary Inbound window xlate base to the start 150 * of RAM. Set the size to 4K, for now. Just for testing 151 * in a host. This obviously has to be customized for each 152 * IQ310 application. 153 * 154 * Note the first 4K of the window is reserved for the 155 * messaging unit, so no RAM is going to be accessed here. 156 * 157 * ..unless we're a host -- in which case, make it work like 158 * the Secondary Inbound window (below). 159 */ 160 if (sc->sc_is_host) { 161 sc->sc_pin_base = memstart; 162 sc->sc_pin_xlate = memstart; 163 sc->sc_pin_size = memsize; 164 } else { 165 sc->sc_pin_xlate = memstart; 166 sc->sc_pin_size = 4096; 167 } 168 169 /* 170 * Map the Secondary Inbound window 1:1 with local RAM. 171 */ 172 sc->sc_sin_base = memstart; 173 sc->sc_sin_xlate = memstart; 174 sc->sc_sin_size = memsize; 175 176 /* 177 * XXX Don't use the Primary Outbound windows, for now. 178 */ 179 sc->sc_pmemout_size = 0; 180 sc->sc_pioout_size = 0; 181 182 /* 183 * Set the Secondary Outbound Memory window to map 1:1 184 * PCI:Local. 185 */ 186 sc->sc_smemout_base = I80312_PCI_XLATE_SMW_BASE; 187 sc->sc_smemout_size = I80312_PCI_XLATE_MSIZE; 188 189 /* 190 * Set the Secondary Outbound I/O window to map 191 * to PCI address 0 for all 64K of the I/O space. 192 */ 193 sc->sc_sioout_base = 0; 194 sc->sc_sioout_size = I80312_PCI_XLATE_IOSIZE; 195 196 /* 197 * XXX For now, suppress all secondary IDSELs (thus making all 198 * devices from S_AD[11]..S_AD[25] private). 199 */ 200 sc->sc_sisr = 0x3ff; 201 202 /* 203 * XXX For now, make the entire Secondary Outbound address 204 * spaces private. 205 */ 206 sc->sc_privio_base = sc->sc_sioout_base; 207 sc->sc_privio_size = sc->sc_sioout_size; 208 sc->sc_privmem_base = sc->sc_smemout_base; 209 sc->sc_privmem_size = sc->sc_smemout_size; 210 211 /* 212 * Initialize the interrupt part of our PCI chipset tag. 213 */ 214 iq80310_pci_init(&sc->sc_pci_chipset, sc); 215 216 i80312_attach(sc); 217 } 218
Indexes created Thu Oct 30 03:10:01 GMT 2025