| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni_dma.c | 195 u32 rb_cntl, dma_cntl, ib_cntl; local in function:cayman_dma_resume
238 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
240 ib_cntl |= DMA_IB_SWAP_ENABLE;
242 WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);
|
| radeon_r600_dma.c | 128 u32 rb_cntl, dma_cntl, ib_cntl; local in function:r600_dma_resume
159 ib_cntl = DMA_IB_ENABLE;
161 ib_cntl |= DMA_IB_SWAP_ENABLE;
163 WREG32(DMA_IB_CNTL, ib_cntl);
|
| radeon_cik_sdma.c | 373 u32 rb_cntl, ib_cntl; local in function:cik_sdma_gfx_resume
422 ib_cntl = SDMA_IB_ENABLE;
424 ib_cntl |= SDMA_IB_SWAP_ENABLE;
427 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dma.c | 139 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; local in function:si_dma_start
171 ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE;
173 ib_cntl |= DMA_IB_SWAP_ENABLE;
175 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl);
|
| amdgpu_cik_sdma.c | 440 u32 rb_cntl, ib_cntl; local in function:cik_sdma_gfx_resume
499 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
501 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
504 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
|
| amdgpu_sdma_v2_4.c | 349 u32 rb_cntl, ib_cntl; local in function:sdma_v2_4_gfx_stop
360 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
361 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
362 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
419 u32 rb_cntl, ib_cntl; local in function:sdma_v2_4_gfx_resume
478 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
479 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
481 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)
[all...] |
| amdgpu_sdma_v3_0.c | 523 u32 rb_cntl, ib_cntl; local in function:sdma_v3_0_gfx_stop
534 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
535 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
536 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
654 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v3_0_gfx_resume
746 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
747 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
749 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)
[all...] |
| amdgpu_sdma_v4_0.c | 916 u32 rb_cntl, ib_cntl; local in function:sdma_v4_0_gfx_stop
930 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
931 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
932 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
960 u32 rb_cntl, ib_cntl; local in function:sdma_v4_0_page_stop
977 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
978 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
980 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1093 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v4_0_gfx_resume
1183 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v4_0_page_resume
[all...] |
| amdgpu_sdma_v5_0.c | 497 u32 rb_cntl, ib_cntl; local in function:sdma_v5_0_gfx_stop
508 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
509 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
510 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
619 u32 rb_cntl, ib_cntl; local in function:sdma_v5_0_gfx_resume
741 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
742 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
744 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)
[all...] |
