1 /* $NetBSD: amdgpu_cik_sdma.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_cik_sdma.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 29 30 #include <linux/firmware.h> 31 #include <linux/module.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ucode.h" 35 #include "amdgpu_trace.h" 36 #include "cikd.h" 37 #include "cik.h" 38 39 #include "bif/bif_4_1_d.h" 40 #include "bif/bif_4_1_sh_mask.h" 41 42 #include "gca/gfx_7_2_d.h" 43 #include "gca/gfx_7_2_enum.h" 44 #include "gca/gfx_7_2_sh_mask.h" 45 46 #include "gmc/gmc_7_1_d.h" 47 #include "gmc/gmc_7_1_sh_mask.h" 48 49 #include "oss/oss_2_0_d.h" 50 #include "oss/oss_2_0_sh_mask.h" 51 52 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 53 { 54 SDMA0_REGISTER_OFFSET, 55 SDMA1_REGISTER_OFFSET 56 }; 57 58 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 59 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 60 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 61 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static int cik_sdma_soft_reset(void *handle); 63 64 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); 65 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); 66 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin"); 67 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin"); 68 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin"); 69 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin"); 70 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin"); 71 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin"); 72 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin"); 73 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin"); 74 75 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); 76 77 78 static void cik_sdma_free_microcode(struct amdgpu_device *adev) 79 { 80 int i; 81 for (i = 0; i < adev->sdma.num_instances; i++) { 82 release_firmware(adev->sdma.instance[i].fw); 83 adev->sdma.instance[i].fw = NULL; 84 } 85 } 86 87 /* 88 * sDMA - System DMA 89 * Starting with CIK, the GPU has new asynchronous 90 * DMA engines. These engines are used for compute 91 * and gfx. There are two DMA engines (SDMA0, SDMA1) 92 * and each one supports 1 ring buffer used for gfx 93 * and 2 queues used for compute. 94 * 95 * The programming model is very similar to the CP 96 * (ring buffer, IBs, etc.), but sDMA has it's own 97 * packet format that is different from the PM4 format 98 * used by the CP. sDMA supports copying data, writing 99 * embedded data, solid fills, and a number of other 100 * things. It also has support for tiling/detiling of 101 * buffers. 102 */ 103 104 /** 105 * cik_sdma_init_microcode - load ucode images from disk 106 * 107 * @adev: amdgpu_device pointer 108 * 109 * Use the firmware interface to load the ucode images into 110 * the driver (not loaded into hw). 111 * Returns 0 on success, error on failure. 112 */ 113 static int cik_sdma_init_microcode(struct amdgpu_device *adev) 114 { 115 const char *chip_name; 116 char fw_name[30]; 117 int err = 0, i; 118 119 DRM_DEBUG("\n"); 120 121 switch (adev->asic_type) { 122 case CHIP_BONAIRE: 123 chip_name = "bonaire"; 124 break; 125 case CHIP_HAWAII: 126 chip_name = "hawaii"; 127 break; 128 case CHIP_KAVERI: 129 chip_name = "kaveri"; 130 break; 131 case CHIP_KABINI: 132 chip_name = "kabini"; 133 break; 134 case CHIP_MULLINS: 135 chip_name = "mullins"; 136 break; 137 default: BUG(); 138 } 139 140 for (i = 0; i < adev->sdma.num_instances; i++) { 141 if (i == 0) 142 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 143 else 144 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 145 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 146 if (err) 147 goto out; 148 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 149 } 150 out: 151 if (err) { 152 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); 153 for (i = 0; i < adev->sdma.num_instances; i++) { 154 release_firmware(adev->sdma.instance[i].fw); 155 adev->sdma.instance[i].fw = NULL; 156 } 157 } 158 return err; 159 } 160 161 /** 162 * cik_sdma_ring_get_rptr - get the current read pointer 163 * 164 * @ring: amdgpu ring pointer 165 * 166 * Get the current rptr from the hardware (CIK+). 167 */ 168 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 169 { 170 u32 rptr; 171 172 rptr = ring->adev->wb.wb[ring->rptr_offs]; 173 174 return (rptr & 0x3fffc) >> 2; 175 } 176 177 /** 178 * cik_sdma_ring_get_wptr - get the current write pointer 179 * 180 * @ring: amdgpu ring pointer 181 * 182 * Get the current wptr from the hardware (CIK+). 183 */ 184 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) 185 { 186 struct amdgpu_device *adev = ring->adev; 187 188 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; 189 } 190 191 /** 192 * cik_sdma_ring_set_wptr - commit the write pointer 193 * 194 * @ring: amdgpu ring pointer 195 * 196 * Write the wptr back to the hardware (CIK+). 197 */ 198 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 199 { 200 struct amdgpu_device *adev = ring->adev; 201 202 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], 203 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); 204 } 205 206 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 207 { 208 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 209 int i; 210 211 for (i = 0; i < count; i++) 212 if (sdma && sdma->burst_nop && (i == 0)) 213 amdgpu_ring_write(ring, ring->funcs->nop | 214 SDMA_NOP_COUNT(count - 1)); 215 else 216 amdgpu_ring_write(ring, ring->funcs->nop); 217 } 218 219 /** 220 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine 221 * 222 * @ring: amdgpu ring pointer 223 * @ib: IB object to schedule 224 * 225 * Schedule an IB in the DMA ring (CIK). 226 */ 227 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 228 struct amdgpu_job *job, 229 struct amdgpu_ib *ib, 230 uint32_t flags) 231 { 232 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 233 u32 extra_bits = vmid & 0xf; 234 235 /* IB packet must end on a 8 DW boundary */ 236 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); 237 238 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 239 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 241 amdgpu_ring_write(ring, ib->length_dw); 242 243 } 244 245 /** 246 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 247 * 248 * @ring: amdgpu ring pointer 249 * 250 * Emit an hdp flush packet on the requested DMA ring. 251 */ 252 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 253 { 254 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 255 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 256 u32 ref_and_mask; 257 258 if (ring->me == 0) 259 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; 260 else 261 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; 262 263 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 264 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 265 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 266 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 267 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 268 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 269 } 270 271 /** 272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring 273 * 274 * @ring: amdgpu ring pointer 275 * @fence: amdgpu fence object 276 * 277 * Add a DMA fence packet to the ring to write 278 * the fence seq number and DMA trap packet to generate 279 * an interrupt if needed (CIK). 280 */ 281 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 282 unsigned flags) 283 { 284 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 285 /* write the fence */ 286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 287 amdgpu_ring_write(ring, lower_32_bits(addr)); 288 amdgpu_ring_write(ring, upper_32_bits(addr)); 289 amdgpu_ring_write(ring, lower_32_bits(seq)); 290 291 /* optionally write high bits as well */ 292 if (write64bit) { 293 addr += 4; 294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 295 amdgpu_ring_write(ring, lower_32_bits(addr)); 296 amdgpu_ring_write(ring, upper_32_bits(addr)); 297 amdgpu_ring_write(ring, upper_32_bits(seq)); 298 } 299 300 /* generate an interrupt */ 301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 302 } 303 304 /** 305 * cik_sdma_gfx_stop - stop the gfx async dma engines 306 * 307 * @adev: amdgpu_device pointer 308 * 309 * Stop the gfx async dma ring buffers (CIK). 310 */ 311 static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 312 { 313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 315 u32 rb_cntl; 316 int i; 317 318 if ((adev->mman.buffer_funcs_ring == sdma0) || 319 (adev->mman.buffer_funcs_ring == sdma1)) 320 amdgpu_ttm_set_buffer_funcs_status(adev, false); 321 322 for (i = 0; i < adev->sdma.num_instances; i++) { 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; 325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); 327 } 328 sdma0->sched.ready = false; 329 sdma1->sched.ready = false; 330 } 331 332 /** 333 * cik_sdma_rlc_stop - stop the compute async dma engines 334 * 335 * @adev: amdgpu_device pointer 336 * 337 * Stop the compute async dma queues (CIK). 338 */ 339 static void cik_sdma_rlc_stop(struct amdgpu_device *adev) 340 { 341 /* XXX todo */ 342 } 343 344 /** 345 * cik_ctx_switch_enable - stop the async dma engines context switch 346 * 347 * @adev: amdgpu_device pointer 348 * @enable: enable/disable the DMA MEs context switch. 349 * 350 * Halt or unhalt the async dma engines context switch (VI). 351 */ 352 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 353 { 354 u32 f32_cntl, phase_quantum = 0; 355 int i; 356 357 if (amdgpu_sdma_phase_quantum) { 358 unsigned value = amdgpu_sdma_phase_quantum; 359 unsigned unit = 0; 360 361 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 363 value = (value + 1) >> 1; 364 unit++; 365 } 366 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 367 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 368 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 369 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 370 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 371 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 372 WARN_ONCE(1, 373 "clamping sdma_phase_quantum to %uK clock cycles\n", 374 value << unit); 375 } 376 phase_quantum = 377 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 378 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 379 } 380 381 for (i = 0; i < adev->sdma.num_instances; i++) { 382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 383 if (enable) { 384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 385 AUTO_CTXSW_ENABLE, 1); 386 if (amdgpu_sdma_phase_quantum) { 387 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 388 phase_quantum); 389 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 390 phase_quantum); 391 } 392 } else { 393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 394 AUTO_CTXSW_ENABLE, 0); 395 } 396 397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 398 } 399 } 400 401 /** 402 * cik_sdma_enable - stop the async dma engines 403 * 404 * @adev: amdgpu_device pointer 405 * @enable: enable/disable the DMA MEs. 406 * 407 * Halt or unhalt the async dma engines (CIK). 408 */ 409 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) 410 { 411 u32 me_cntl; 412 int i; 413 414 if (!enable) { 415 cik_sdma_gfx_stop(adev); 416 cik_sdma_rlc_stop(adev); 417 } 418 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 421 if (enable) 422 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; 423 else 424 me_cntl |= SDMA0_F32_CNTL__HALT_MASK; 425 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); 426 } 427 } 428 429 /** 430 * cik_sdma_gfx_resume - setup and start the async dma engines 431 * 432 * @adev: amdgpu_device pointer 433 * 434 * Set up the gfx DMA ring buffers and enable them (CIK). 435 * Returns 0 for success, error for failure. 436 */ 437 static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 438 { 439 struct amdgpu_ring *ring; 440 u32 rb_cntl, ib_cntl; 441 u32 rb_bufsz; 442 u32 wb_offset; 443 int i, j, r; 444 445 for (i = 0; i < adev->sdma.num_instances; i++) { 446 ring = &adev->sdma.instance[i].ring; 447 wb_offset = (ring->rptr_offs * 4); 448 449 mutex_lock(&adev->srbm_mutex); 450 for (j = 0; j < 16; j++) { 451 cik_srbm_select(adev, 0, 0, 0, j); 452 /* SDMA GFX */ 453 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 454 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 455 /* XXX SDMA RLC - todo */ 456 } 457 cik_srbm_select(adev, 0, 0, 0, 0); 458 mutex_unlock(&adev->srbm_mutex); 459 460 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 461 adev->gfx.config.gb_addr_config & 0x70); 462 463 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 464 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 465 466 /* Set ring buffer size in dwords */ 467 rb_bufsz = order_base_2(ring->ring_size / 4); 468 rb_cntl = rb_bufsz << 1; 469 #ifdef __BIG_ENDIAN 470 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | 471 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; 472 #endif 473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 474 475 /* Initialize the ring buffer's read and write pointers */ 476 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 477 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 478 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 479 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 480 481 /* set the wb address whether it's enabled or not */ 482 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 484 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 485 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 486 487 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; 488 489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 491 492 ring->wptr = 0; 493 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 494 495 /* enable DMA RB */ 496 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], 497 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); 498 499 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; 500 #ifdef __BIG_ENDIAN 501 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; 502 #endif 503 /* enable DMA IBs */ 504 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 505 506 ring->sched.ready = true; 507 } 508 509 cik_sdma_enable(adev, true); 510 511 for (i = 0; i < adev->sdma.num_instances; i++) { 512 ring = &adev->sdma.instance[i].ring; 513 r = amdgpu_ring_test_helper(ring); 514 if (r) 515 return r; 516 517 if (adev->mman.buffer_funcs_ring == ring) 518 amdgpu_ttm_set_buffer_funcs_status(adev, true); 519 } 520 521 return 0; 522 } 523 524 /** 525 * cik_sdma_rlc_resume - setup and start the async dma engines 526 * 527 * @adev: amdgpu_device pointer 528 * 529 * Set up the compute DMA queues and enable them (CIK). 530 * Returns 0 for success, error for failure. 531 */ 532 static int cik_sdma_rlc_resume(struct amdgpu_device *adev) 533 { 534 /* XXX todo */ 535 return 0; 536 } 537 538 /** 539 * cik_sdma_load_microcode - load the sDMA ME ucode 540 * 541 * @adev: amdgpu_device pointer 542 * 543 * Loads the sDMA0/1 ucode. 544 * Returns 0 for success, -EINVAL if the ucode is not available. 545 */ 546 static int cik_sdma_load_microcode(struct amdgpu_device *adev) 547 { 548 const struct sdma_firmware_header_v1_0 *hdr; 549 const __le32 *fw_data; 550 u32 fw_size; 551 int i, j; 552 553 /* halt the MEs */ 554 cik_sdma_enable(adev, false); 555 556 for (i = 0; i < adev->sdma.num_instances; i++) { 557 if (!adev->sdma.instance[i].fw) 558 return -EINVAL; 559 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 560 amdgpu_ucode_print_sdma_hdr(&hdr->header); 561 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 562 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 563 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 564 if (adev->sdma.instance[i].feature_version >= 20) 565 adev->sdma.instance[i].burst_nop = true; 566 fw_data = (const __le32 *) 567 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 568 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 569 for (j = 0; j < fw_size; j++) 570 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 571 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 572 } 573 574 return 0; 575 } 576 577 /** 578 * cik_sdma_start - setup and start the async dma engines 579 * 580 * @adev: amdgpu_device pointer 581 * 582 * Set up the DMA engines and enable them (CIK). 583 * Returns 0 for success, error for failure. 584 */ 585 static int cik_sdma_start(struct amdgpu_device *adev) 586 { 587 int r; 588 589 r = cik_sdma_load_microcode(adev); 590 if (r) 591 return r; 592 593 /* halt the engine before programing */ 594 cik_sdma_enable(adev, false); 595 /* enable sdma ring preemption */ 596 cik_ctx_switch_enable(adev, true); 597 598 /* start the gfx rings and rlc compute queues */ 599 r = cik_sdma_gfx_resume(adev); 600 if (r) 601 return r; 602 r = cik_sdma_rlc_resume(adev); 603 if (r) 604 return r; 605 606 return 0; 607 } 608 609 /** 610 * cik_sdma_ring_test_ring - simple async dma engine test 611 * 612 * @ring: amdgpu_ring structure holding ring information 613 * 614 * Test the DMA engine by writing using it to write an 615 * value to memory. (CIK). 616 * Returns 0 for success, error for failure. 617 */ 618 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) 619 { 620 struct amdgpu_device *adev = ring->adev; 621 unsigned i; 622 unsigned index; 623 int r; 624 u32 tmp; 625 u64 gpu_addr; 626 627 r = amdgpu_device_wb_get(adev, &index); 628 if (r) 629 return r; 630 631 gpu_addr = adev->wb.gpu_addr + (index * 4); 632 tmp = 0xCAFEDEAD; 633 adev->wb.wb[index] = cpu_to_le32(tmp); 634 635 r = amdgpu_ring_alloc(ring, 5); 636 if (r) 637 goto error_free_wb; 638 639 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 640 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 641 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 642 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ 643 amdgpu_ring_write(ring, 0xDEADBEEF); 644 amdgpu_ring_commit(ring); 645 646 for (i = 0; i < adev->usec_timeout; i++) { 647 tmp = le32_to_cpu(adev->wb.wb[index]); 648 if (tmp == 0xDEADBEEF) 649 break; 650 udelay(1); 651 } 652 653 if (i >= adev->usec_timeout) 654 r = -ETIMEDOUT; 655 656 error_free_wb: 657 amdgpu_device_wb_free(adev, index); 658 return r; 659 } 660 661 /** 662 * cik_sdma_ring_test_ib - test an IB on the DMA engine 663 * 664 * @ring: amdgpu_ring structure holding ring information 665 * 666 * Test a simple IB in the DMA ring (CIK). 667 * Returns 0 on success, error on failure. 668 */ 669 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 670 { 671 struct amdgpu_device *adev = ring->adev; 672 struct amdgpu_ib ib; 673 struct dma_fence *f = NULL; 674 unsigned index; 675 u32 tmp = 0; 676 u64 gpu_addr; 677 long r; 678 679 r = amdgpu_device_wb_get(adev, &index); 680 if (r) 681 return r; 682 683 gpu_addr = adev->wb.gpu_addr + (index * 4); 684 tmp = 0xCAFEDEAD; 685 adev->wb.wb[index] = cpu_to_le32(tmp); 686 memset(&ib, 0, sizeof(ib)); 687 r = amdgpu_ib_get(adev, NULL, 256, &ib); 688 if (r) 689 goto err0; 690 691 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, 692 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 693 ib.ptr[1] = lower_32_bits(gpu_addr); 694 ib.ptr[2] = upper_32_bits(gpu_addr); 695 ib.ptr[3] = 1; 696 ib.ptr[4] = 0xDEADBEEF; 697 ib.length_dw = 5; 698 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 699 if (r) 700 goto err1; 701 702 r = dma_fence_wait_timeout(f, false, timeout); 703 if (r == 0) { 704 r = -ETIMEDOUT; 705 goto err1; 706 } else if (r < 0) { 707 goto err1; 708 } 709 tmp = le32_to_cpu(adev->wb.wb[index]); 710 if (tmp == 0xDEADBEEF) 711 r = 0; 712 else 713 r = -EINVAL; 714 715 err1: 716 amdgpu_ib_free(adev, &ib, NULL); 717 dma_fence_put(f); 718 err0: 719 amdgpu_device_wb_free(adev, index); 720 return r; 721 } 722 723 /** 724 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 725 * 726 * @ib: indirect buffer to fill with commands 727 * @pe: addr of the page entry 728 * @src: src addr to copy from 729 * @count: number of page entries to update 730 * 731 * Update PTEs by copying them from the GART using sDMA (CIK). 732 */ 733 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, 734 uint64_t pe, uint64_t src, 735 unsigned count) 736 { 737 unsigned bytes = count * 8; 738 739 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 740 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 741 ib->ptr[ib->length_dw++] = bytes; 742 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 743 ib->ptr[ib->length_dw++] = lower_32_bits(src); 744 ib->ptr[ib->length_dw++] = upper_32_bits(src); 745 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 746 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 747 } 748 749 /** 750 * cik_sdma_vm_write_pages - update PTEs by writing them manually 751 * 752 * @ib: indirect buffer to fill with commands 753 * @pe: addr of the page entry 754 * @value: dst addr to write into pe 755 * @count: number of page entries to update 756 * @incr: increase next addr by incr bytes 757 * 758 * Update PTEs by writing them manually using sDMA (CIK). 759 */ 760 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 761 uint64_t value, unsigned count, 762 uint32_t incr) 763 { 764 unsigned ndw = count * 2; 765 766 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 767 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 768 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 769 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 770 ib->ptr[ib->length_dw++] = ndw; 771 for (; ndw > 0; ndw -= 2) { 772 ib->ptr[ib->length_dw++] = lower_32_bits(value); 773 ib->ptr[ib->length_dw++] = upper_32_bits(value); 774 value += incr; 775 } 776 } 777 778 /** 779 * cik_sdma_vm_set_pages - update the page tables using sDMA 780 * 781 * @ib: indirect buffer to fill with commands 782 * @pe: addr of the page entry 783 * @addr: dst addr to write into pe 784 * @count: number of page entries to update 785 * @incr: increase next addr by incr bytes 786 * @flags: access flags 787 * 788 * Update the page tables using sDMA (CIK). 789 */ 790 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 791 uint64_t addr, unsigned count, 792 uint32_t incr, uint64_t flags) 793 { 794 /* for physically contiguous pages (vram) */ 795 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 796 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 797 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 798 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 799 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 800 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 801 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 802 ib->ptr[ib->length_dw++] = incr; /* increment size */ 803 ib->ptr[ib->length_dw++] = 0; 804 ib->ptr[ib->length_dw++] = count; /* number of entries */ 805 } 806 807 /** 808 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 809 * 810 * @ib: indirect buffer to fill with padding 811 * 812 */ 813 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 814 { 815 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 816 u32 pad_count; 817 int i; 818 819 pad_count = (-ib->length_dw) & 7; 820 for (i = 0; i < pad_count; i++) 821 if (sdma && sdma->burst_nop && (i == 0)) 822 ib->ptr[ib->length_dw++] = 823 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | 824 SDMA_NOP_COUNT(pad_count - 1); 825 else 826 ib->ptr[ib->length_dw++] = 827 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 828 } 829 830 /** 831 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 832 * 833 * @ring: amdgpu_ring pointer 834 * 835 * Make sure all previous operations are completed (CIK). 836 */ 837 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 838 { 839 uint32_t seq = ring->fence_drv.sync_seq; 840 uint64_t addr = ring->fence_drv.gpu_addr; 841 842 /* wait for idle */ 843 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 844 SDMA_POLL_REG_MEM_EXTRA_OP(0) | 845 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ 846 SDMA_POLL_REG_MEM_EXTRA_M)); 847 amdgpu_ring_write(ring, addr & 0xfffffffc); 848 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 849 amdgpu_ring_write(ring, seq); /* reference */ 850 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 851 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ 852 } 853 854 /** 855 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA 856 * 857 * @ring: amdgpu_ring pointer 858 * @vm: amdgpu_vm pointer 859 * 860 * Update the page table base and flush the VM TLB 861 * using sDMA (CIK). 862 */ 863 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 864 unsigned vmid, uint64_t pd_addr) 865 { 866 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 867 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 868 869 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 870 871 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 872 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 873 amdgpu_ring_write(ring, 0); 874 amdgpu_ring_write(ring, 0); /* reference */ 875 amdgpu_ring_write(ring, 0); /* mask */ 876 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 877 } 878 879 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring, 880 uint32_t reg, uint32_t val) 881 { 882 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 883 amdgpu_ring_write(ring, reg); 884 amdgpu_ring_write(ring, val); 885 } 886 887 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 888 bool enable) 889 { 890 u32 orig, data; 891 892 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 893 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 894 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 895 } else { 896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); 897 data |= 0xff000000; 898 if (data != orig) 899 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); 900 901 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); 902 data |= 0xff000000; 903 if (data != orig) 904 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); 905 } 906 } 907 908 static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 909 bool enable) 910 { 911 u32 orig, data; 912 913 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 915 data |= 0x100; 916 if (orig != data) 917 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 918 919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 920 data |= 0x100; 921 if (orig != data) 922 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 923 } else { 924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 925 data &= ~0x100; 926 if (orig != data) 927 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 928 929 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 930 data &= ~0x100; 931 if (orig != data) 932 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 933 } 934 } 935 936 static int cik_sdma_early_init(void *handle) 937 { 938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 939 940 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 941 942 cik_sdma_set_ring_funcs(adev); 943 cik_sdma_set_irq_funcs(adev); 944 cik_sdma_set_buffer_funcs(adev); 945 cik_sdma_set_vm_pte_funcs(adev); 946 947 return 0; 948 } 949 950 static int cik_sdma_sw_init(void *handle) 951 { 952 struct amdgpu_ring *ring; 953 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 954 int r, i; 955 956 r = cik_sdma_init_microcode(adev); 957 if (r) { 958 DRM_ERROR("Failed to load sdma firmware!\n"); 959 return r; 960 } 961 962 /* SDMA trap event */ 963 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, 964 &adev->sdma.trap_irq); 965 if (r) 966 return r; 967 968 /* SDMA Privileged inst */ 969 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 970 &adev->sdma.illegal_inst_irq); 971 if (r) 972 return r; 973 974 /* SDMA Privileged inst */ 975 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247, 976 &adev->sdma.illegal_inst_irq); 977 if (r) 978 return r; 979 980 for (i = 0; i < adev->sdma.num_instances; i++) { 981 ring = &adev->sdma.instance[i].ring; 982 ring->ring_obj = NULL; 983 snprintf(ring->name, sizeof ring->name, "sdma%d", i); 984 r = amdgpu_ring_init(adev, ring, 1024, 985 &adev->sdma.trap_irq, 986 (i == 0) ? 987 AMDGPU_SDMA_IRQ_INSTANCE0 : 988 AMDGPU_SDMA_IRQ_INSTANCE1); 989 if (r) 990 return r; 991 } 992 993 return r; 994 } 995 996 static int cik_sdma_sw_fini(void *handle) 997 { 998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 999 int i; 1000 1001 for (i = 0; i < adev->sdma.num_instances; i++) 1002 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1003 1004 cik_sdma_free_microcode(adev); 1005 return 0; 1006 } 1007 1008 static int cik_sdma_hw_init(void *handle) 1009 { 1010 int r; 1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1012 1013 r = cik_sdma_start(adev); 1014 if (r) 1015 return r; 1016 1017 return r; 1018 } 1019 1020 static int cik_sdma_hw_fini(void *handle) 1021 { 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 1024 cik_ctx_switch_enable(adev, false); 1025 cik_sdma_enable(adev, false); 1026 1027 return 0; 1028 } 1029 1030 static int cik_sdma_suspend(void *handle) 1031 { 1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1033 1034 return cik_sdma_hw_fini(adev); 1035 } 1036 1037 static int cik_sdma_resume(void *handle) 1038 { 1039 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1040 1041 cik_sdma_soft_reset(handle); 1042 1043 return cik_sdma_hw_init(adev); 1044 } 1045 1046 static bool cik_sdma_is_idle(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 u32 tmp = RREG32(mmSRBM_STATUS2); 1050 1051 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1052 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1053 return false; 1054 1055 return true; 1056 } 1057 1058 static int cik_sdma_wait_for_idle(void *handle) 1059 { 1060 unsigned i; 1061 u32 tmp; 1062 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1063 1064 for (i = 0; i < adev->usec_timeout; i++) { 1065 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1066 SRBM_STATUS2__SDMA1_BUSY_MASK); 1067 1068 if (!tmp) 1069 return 0; 1070 udelay(1); 1071 } 1072 return -ETIMEDOUT; 1073 } 1074 1075 static int cik_sdma_soft_reset(void *handle) 1076 { 1077 u32 srbm_soft_reset = 0; 1078 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1079 u32 tmp = RREG32(mmSRBM_STATUS2); 1080 1081 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1082 /* sdma0 */ 1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1084 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1085 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1087 } 1088 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1089 /* sdma1 */ 1090 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1091 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1092 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1093 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1094 } 1095 1096 if (srbm_soft_reset) { 1097 tmp = RREG32(mmSRBM_SOFT_RESET); 1098 tmp |= srbm_soft_reset; 1099 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1100 WREG32(mmSRBM_SOFT_RESET, tmp); 1101 tmp = RREG32(mmSRBM_SOFT_RESET); 1102 1103 udelay(50); 1104 1105 tmp &= ~srbm_soft_reset; 1106 WREG32(mmSRBM_SOFT_RESET, tmp); 1107 tmp = RREG32(mmSRBM_SOFT_RESET); 1108 1109 /* Wait a little for things to settle down */ 1110 udelay(50); 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, 1117 struct amdgpu_irq_src *src, 1118 unsigned type, 1119 enum amdgpu_interrupt_state state) 1120 { 1121 u32 sdma_cntl; 1122 1123 switch (type) { 1124 case AMDGPU_SDMA_IRQ_INSTANCE0: 1125 switch (state) { 1126 case AMDGPU_IRQ_STATE_DISABLE: 1127 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1128 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1129 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1130 break; 1131 case AMDGPU_IRQ_STATE_ENABLE: 1132 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1133 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1134 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1135 break; 1136 default: 1137 break; 1138 } 1139 break; 1140 case AMDGPU_SDMA_IRQ_INSTANCE1: 1141 switch (state) { 1142 case AMDGPU_IRQ_STATE_DISABLE: 1143 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1144 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1145 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1146 break; 1147 case AMDGPU_IRQ_STATE_ENABLE: 1148 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1149 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1150 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1151 break; 1152 default: 1153 break; 1154 } 1155 break; 1156 default: 1157 break; 1158 } 1159 return 0; 1160 } 1161 1162 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, 1163 struct amdgpu_irq_src *source, 1164 struct amdgpu_iv_entry *entry) 1165 { 1166 u8 instance_id, queue_id; 1167 1168 instance_id = (entry->ring_id & 0x3) >> 0; 1169 queue_id = (entry->ring_id & 0xc) >> 2; 1170 DRM_DEBUG("IH: SDMA trap\n"); 1171 switch (instance_id) { 1172 case 0: 1173 switch (queue_id) { 1174 case 0: 1175 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1176 break; 1177 case 1: 1178 /* XXX compute */ 1179 break; 1180 case 2: 1181 /* XXX compute */ 1182 break; 1183 } 1184 break; 1185 case 1: 1186 switch (queue_id) { 1187 case 0: 1188 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1189 break; 1190 case 1: 1191 /* XXX compute */ 1192 break; 1193 case 2: 1194 /* XXX compute */ 1195 break; 1196 } 1197 break; 1198 } 1199 1200 return 0; 1201 } 1202 1203 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, 1204 struct amdgpu_irq_src *source, 1205 struct amdgpu_iv_entry *entry) 1206 { 1207 u8 instance_id; 1208 1209 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1210 instance_id = (entry->ring_id & 0x3) >> 0; 1211 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1212 return 0; 1213 } 1214 1215 static int cik_sdma_set_clockgating_state(void *handle, 1216 enum amd_clockgating_state state) 1217 { 1218 bool gate = false; 1219 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1220 1221 if (state == AMD_CG_STATE_GATE) 1222 gate = true; 1223 1224 cik_enable_sdma_mgcg(adev, gate); 1225 cik_enable_sdma_mgls(adev, gate); 1226 1227 return 0; 1228 } 1229 1230 static int cik_sdma_set_powergating_state(void *handle, 1231 enum amd_powergating_state state) 1232 { 1233 return 0; 1234 } 1235 1236 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1237 .name = "cik_sdma", 1238 .early_init = cik_sdma_early_init, 1239 .late_init = NULL, 1240 .sw_init = cik_sdma_sw_init, 1241 .sw_fini = cik_sdma_sw_fini, 1242 .hw_init = cik_sdma_hw_init, 1243 .hw_fini = cik_sdma_hw_fini, 1244 .suspend = cik_sdma_suspend, 1245 .resume = cik_sdma_resume, 1246 .is_idle = cik_sdma_is_idle, 1247 .wait_for_idle = cik_sdma_wait_for_idle, 1248 .soft_reset = cik_sdma_soft_reset, 1249 .set_clockgating_state = cik_sdma_set_clockgating_state, 1250 .set_powergating_state = cik_sdma_set_powergating_state, 1251 }; 1252 1253 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1254 .type = AMDGPU_RING_TYPE_SDMA, 1255 .align_mask = 0xf, 1256 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 1257 .support_64bit_ptrs = false, 1258 .get_rptr = cik_sdma_ring_get_rptr, 1259 .get_wptr = cik_sdma_ring_get_wptr, 1260 .set_wptr = cik_sdma_ring_set_wptr, 1261 .emit_frame_size = 1262 6 + /* cik_sdma_ring_emit_hdp_flush */ 1263 3 + /* hdp invalidate */ 1264 6 + /* cik_sdma_ring_emit_pipeline_sync */ 1265 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ 1266 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ 1267 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ 1268 .emit_ib = cik_sdma_ring_emit_ib, 1269 .emit_fence = cik_sdma_ring_emit_fence, 1270 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, 1271 .emit_vm_flush = cik_sdma_ring_emit_vm_flush, 1272 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1273 .test_ring = cik_sdma_ring_test_ring, 1274 .test_ib = cik_sdma_ring_test_ib, 1275 .insert_nop = cik_sdma_ring_insert_nop, 1276 .pad_ib = cik_sdma_ring_pad_ib, 1277 .emit_wreg = cik_sdma_ring_emit_wreg, 1278 }; 1279 1280 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) 1281 { 1282 int i; 1283 1284 for (i = 0; i < adev->sdma.num_instances; i++) { 1285 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; 1286 adev->sdma.instance[i].ring.me = i; 1287 } 1288 } 1289 1290 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { 1291 .set = cik_sdma_set_trap_irq_state, 1292 .process = cik_sdma_process_trap_irq, 1293 }; 1294 1295 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { 1296 .process = cik_sdma_process_illegal_inst_irq, 1297 }; 1298 1299 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) 1300 { 1301 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1302 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; 1303 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; 1304 } 1305 1306 /** 1307 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine 1308 * 1309 * @ring: amdgpu_ring structure holding ring information 1310 * @src_offset: src GPU address 1311 * @dst_offset: dst GPU address 1312 * @byte_count: number of bytes to xfer 1313 * 1314 * Copy GPU buffers using the DMA engine (CIK). 1315 * Used by the amdgpu ttm implementation to move pages if 1316 * registered as the asic copy callback. 1317 */ 1318 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, 1319 uint64_t src_offset, 1320 uint64_t dst_offset, 1321 uint32_t byte_count) 1322 { 1323 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1324 ib->ptr[ib->length_dw++] = byte_count; 1325 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1326 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1327 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1328 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1329 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1330 } 1331 1332 /** 1333 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine 1334 * 1335 * @ring: amdgpu_ring structure holding ring information 1336 * @src_data: value to write to buffer 1337 * @dst_offset: dst GPU address 1338 * @byte_count: number of bytes to xfer 1339 * 1340 * Fill GPU buffers using the DMA engine (CIK). 1341 */ 1342 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, 1343 uint32_t src_data, 1344 uint64_t dst_offset, 1345 uint32_t byte_count) 1346 { 1347 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); 1348 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1349 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1350 ib->ptr[ib->length_dw++] = src_data; 1351 ib->ptr[ib->length_dw++] = byte_count; 1352 } 1353 1354 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { 1355 .copy_max_bytes = 0x1fffff, 1356 .copy_num_dw = 7, 1357 .emit_copy_buffer = cik_sdma_emit_copy_buffer, 1358 1359 .fill_max_bytes = 0x1fffff, 1360 .fill_num_dw = 5, 1361 .emit_fill_buffer = cik_sdma_emit_fill_buffer, 1362 }; 1363 1364 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) 1365 { 1366 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; 1367 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1368 } 1369 1370 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1371 .copy_pte_num_dw = 7, 1372 .copy_pte = cik_sdma_vm_copy_pte, 1373 1374 .write_pte = cik_sdma_vm_write_pte, 1375 .set_pte_pde = cik_sdma_vm_set_pte_pde, 1376 }; 1377 1378 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) 1379 { 1380 unsigned i; 1381 1382 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; 1383 for (i = 0; i < adev->sdma.num_instances; i++) { 1384 adev->vm_manager.vm_pte_scheds[i] = 1385 &adev->sdma.instance[i].ring.sched; 1386 } 1387 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1388 } 1389 1390 const struct amdgpu_ip_block_version cik_sdma_ip_block = 1391 { 1392 .type = AMD_IP_BLOCK_TYPE_SDMA, 1393 .major = 2, 1394 .minor = 0, 1395 .rev = 0, 1396 .funcs = &cik_sdma_ip_funcs, 1397 }; 1398
Indexes created Sat Sep 20 22:09:52 GMT 2025