1 /* $NetBSD: pci_machdep.c,v 1.13 2022/10/15 04:47:37 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Machine-specific functions for PCI autoconfiguration. 35 * 36 * On PCs, there are two methods of generating PCI configuration cycles. 37 * We try to detect the appropriate mechanism for this machine and set 38 * up a few function pointers to access the correct method directly. 39 * 40 * The configuration method can be hard-coded in the config file by 41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 42 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.13 2022/10/15 04:47:37 rin Exp $"); 47 48 #ifdef _KERNEL_OPT 49 #include "opt_pci.h" 50 #endif 51 52 #include <sys/types.h> 53 #include <sys/param.h> 54 #include <sys/time.h> 55 #include <sys/systm.h> 56 #include <sys/errno.h> 57 #include <sys/device.h> 58 #include <sys/extent.h> 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcidevs.h> 67 #include <dev/pci/pciconf.h> 68 69 #include <powerpc/ibm4xx/ibm405gp.h> 70 #include <powerpc/ibm4xx/pci_machdep.h> 71 #include <powerpc/ibm4xx/dev/pcicreg.h> 72 73 #ifdef DHT_FIXUP_PDCIDE 74 #include <dev/pci/pciidereg.h> 75 #endif 76 77 static struct powerpc_bus_space pci_iot = { 78 _BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE, 79 0x00000000, 80 IBM405GP_PCIC0_BASE, /* extent base */ 81 IBM405GP_PCIC0_BASE + 8, /* extent limit */ 82 }; 83 84 static bus_space_handle_t pci_ioh; 85 86 void 87 ibm4xx_pci_machdep_init(void) 88 { 89 90 if (pci_ioh == 0 && 91 (bus_space_init(&pci_iot, "pcicfg", NULL, 0) || 92 bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh))) 93 panic("Cannot map PCI registers"); 94 } 95 96 void 97 ibm4xx_pci_attach_hook(device_t parent, device_t self, 98 struct pcibus_attach_args *pba) 99 { 100 101 #ifdef PCI_CONFIGURE_VERBOSE 102 printf("pci_attach_hook\n"); 103 ibm4xx_show_pci_map(); 104 #endif 105 ibm4xx_setup_pci(); 106 #ifdef PCI_CONFIGURE_VERBOSE 107 ibm4xx_show_pci_map(); 108 #endif 109 } 110 111 pcitag_t 112 ibm4xx_pci_make_tag(void *v, int bus, int device, int function) 113 { 114 pcitag_t tag; 115 116 if (bus >= 256 || device >= 32 || function >= 8) 117 panic("pci_make_tag: bad request"); 118 119 /* XXX magic number */ 120 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 121 122 return tag; 123 } 124 125 void 126 ibm4xx_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 127 { 128 129 if (bp != NULL) 130 *bp = (tag >> 16) & 0xff; 131 if (dp != NULL) 132 *dp = (tag >> 11) & 0x1f; 133 if (fp != NULL) 134 *fp = (tag >> 8) & 0x07; 135 } 136 137 pcireg_t 138 ibm4xx_pci_conf_read(void *v, pcitag_t tag, int reg) 139 { 140 pcireg_t data; 141 142 if ((unsigned int)reg >= PCI_CONF_SIZE) 143 return (pcireg_t) -1; 144 145 /* 405GT BIOS disables interrupts here. Should we? --Art */ 146 bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg); 147 data = bus_space_read_4(&pci_iot, pci_ioh, PCIC_CFGDATA); 148 /* 405GP pass2 errata #6 */ 149 bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0); 150 return data; 151 } 152 153 void 154 ibm4xx_pci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 155 { 156 157 if ((unsigned int)reg >= PCI_CONF_SIZE) 158 return; 159 160 bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg); 161 bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGDATA, data); 162 /* 405GP pass2 errata #6 */ 163 bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0); 164 } 165 166 int 167 ibm4xx_pci_intr_setattr(void *v, pci_intr_handle_t *ihp, int attr, 168 uint64_t data) 169 { 170 171 switch (attr) { 172 case PCI_INTR_MPSAFE: 173 return 0; 174 default: 175 return ENODEV; 176 } 177 } 178 179 /* Avoid overconfiguration */ 180 int 181 ibm4xx_pci_conf_hook(void *v, int bus, int dev, int func, pcireg_t id) 182 { 183 184 if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) || 185 (PCI_VENDOR(id) == PCI_VENDOR_INTEL && PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) { 186 /* Don't configure the bridge and PCI probe. */ 187 return 0; 188 } 189 190 #ifdef DHT_FIXUP_PDCIDE 191 /* 192 * Initialize PDC20265 to native-PCI mode. This should be done 193 * *before* pci_do_device_query(). Otherwise, we will fail to 194 * configure native-PCI IO registers. 195 */ 196 if (PCI_VENDOR(id) == PCI_VENDOR_PROMISE && 197 PCI_PRODUCT(id) == PCI_PRODUCT_PROMISE_PDC20265) { 198 pcitag_t tag; 199 pcireg_t csr; 200 201 tag = ibm4xx_pci_make_tag(v, bus, dev, func); 202 csr = ibm4xx_pci_conf_read(v, tag, PCI_CLASS_REG); 203 csr |= (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1)) 204 << PCI_INTERFACE_SHIFT; 205 ibm4xx_pci_conf_write(v, tag, PCI_CLASS_REG, csr); 206 } 207 #endif 208 209 return PCI_CONF_DEFAULT; 210 } 211
Indexes created Sun Sep 21 16:09:51 GMT 2025