| /src/sys/arch/arm/at91/ |
| at91spi.c | 332 DPRINTFN(3, ("%s: dmaoffs=%d len=%d wchunk=%p (%p:%d) rchunk=%p (%p:%d) mr=%"PRIX32" sr=%"PRIX32" imr=%"PRIX32" csr0=%"PRIX32"\n",
422 uint32_t imr, sr; local
425 if ((imr = GETREG(sc, SPI_IMR)) == 0) {
432 if (!(sr & imr)) {
434 DPRINTFN(3, ("%s: interrupts are not enabled, sr=%08"PRIX32" imr=%08"PRIX32"\n",
435 __FUNCTION__, sr, imr));
439 DPRINTFN(3, ("%s: sr=%08"PRIX32" imr=%08"PRIX32"\n",
440 __FUNCTION__, sr, imr));
442 if (sr & imr & SPI_SR_MODF) {
447 if (sr & imr & SPI_SR_OVRES)
[all...] |
| at91twi.c | 146 u_int sr, isr, imr; local
149 imr = at91twi_readreg(sc, TWI_IMR);
150 isr = sr & imr;
154 // printf("%s(%s): interrupts are disabled (sr=%08X imr=%08X)\n", __FUNCTION__, device_xname(sc->sc_dev), sr, imr);
|
| at91emac.c | 211 uint32_t imr, isr, ctl; local
214 imr = ~EMAC_READ(ETH_IMR);
215 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE
221 isr = EMAC_READ(ETH_ISR) & imr;
227 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
228 isr, rsr, imr));
|
| at91dbgu.c | 1042 uint32_t imr, sr; local
1044 imr = DBGUREG(DBGU_IMR);
1046 if (!imr)
1050 if (!(sr & imr)) {
1052 // printf("sr=0x%08x imr=0x%08x\n", sr, imr);
1130 rnd_add_uint32(&sc->rnd_source, imr ^ sr ^ c);
|
| at91usart.c | 1096 u_int csr, imr; local
1099 imr = at91usart_readreg(sc, US_IMR);
1100 if (!imr)
1104 DPRINTFN(6,("%s: csr=%08X imr=%08X\n", device_xname(sc->sc_dev), csr, imr));
1105 if (!ISSET(csr, imr))
|
| /src/sys/arch/evbmips/loongson/ |
| loongson_intr.c | 143 uint32_t isr0, isr, imr; local
151 imr = REGVAL(BONITO_INTEN);
154 isr = isr0 & imr & LOONGSON_INTRMASK_LVL4;
|
| yeeloong_machdep.c | 373 uint imr; local
380 imr = lemote_get_isa_imr();
381 imr |= (1 << irq);
382 DPRINTF(("lemote_isa_intr_establish: enable irq %d 0x%x\n", irq, imr));
383 loongson_set_isa_imr(imr);
430 uint32_t isr, imr, mask; local
434 imr = lemote_get_isa_imr();
435 isr = lemote_get_isa_isr() & imr;
474 loongson_set_isa_imr(imr);
|
| generic2e_machdep.c | 249 uint imr; local
255 imr = loongson_isaimr;
256 imr |= (1 << irq);
257 loongson_set_isa_imr(imr);
|
| /src/sys/arch/evbmips/sbmips/ |
| sb1250_icu.c | 77 /* imr values corresponding to each pin */
275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); local
276 for (u_int i = 1; imr += IMR_REGISTER_SPACING, i < cpus; i++) {
277 WRITE_REG(imr, imr_all);
|
| /src/sys/arch/sbmips/sbmips/ |
| sb1250_icu.c | 77 /* imr values corresponding to each pin */
275 vaddr_t imr = MIPS_PHYS_TO_KSEG1(A_IMR_CPU0_BASE + R_IMR_INTERRUPT_MASK); local
276 for (u_int i = 1; imr += IMR_REGISTER_SPACING, i < cpus; i++) {
277 WRITE_REG(imr, imr_all);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| interrupt.c | 167 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
173 * This function is used to emulate the generic IMR register bit change
185 u32 imr = *(u32 *)p_data; local
187 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
188 (vgpu_vreg(vgpu, reg) ^ imr));
190 vgpu_vreg(vgpu, reg) = imr;
369 u32 imr = regbase_to_imr( local
372 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
|
| /src/sys/net80211/ |
| ieee80211.c | 383 struct ifmediareq imr; local
477 ieee80211_media_status(ifp, &imr);
478 ifmedia_set(&ic->ic_media, imr.ifm_active);
743 ieee80211_media_status(struct ifnet *ifp, struct ifmediareq *imr)
753 imr->ifm_status = IFM_AVALID;
754 imr->ifm_active = IFM_IEEE80211;
756 imr->ifm_status |= IFM_ACTIVE;
765 imr->ifm_active |= ieee80211_rate2media(ic,
772 imr->ifm_active |= ieee80211_rate2media(ic,
775 imr->ifm_active |= IFM_AUTO
[all...] |
| /src/external/gpl3/gdb/dist/sim/mips/ |
| dv-tx3904irc.c | 55 4: IMR: interrupt mask register
182 unsigned_4 imr; member in struct:tx3904irc
183 #define IMR_GET(c) ((c)->imr)
246 controller->imr = 0;
306 controller->imr = 0;
349 case IMR_REG: register_value = controller->imr; break;
390 case IMR_REG: register_ptr = & controller->imr; break;
|
| /src/external/gpl3/gdb.old/dist/sim/mips/ |
| dv-tx3904irc.c | 55 4: IMR: interrupt mask register
182 unsigned_4 imr; member in struct:tx3904irc
183 #define IMR_GET(c) ((c)->imr)
246 controller->imr = 0;
306 controller->imr = 0;
349 case IMR_REG: register_value = controller->imr; break;
390 case IMR_REG: register_ptr = & controller->imr; break;
|
| /src/sys/dev/cadence/ |
| if_cemac.c | 250 uint32_t imr, isr, ctl; local
262 imr = ~CEMAC_READ(ETH_IMR);
263 if (!(imr & (ETH_ISR_RCOM | ETH_ISR_TBRE | ETH_ISR_TIDLE |
272 isr &= imr;
282 DPRINTFN(2, ("%s: isr=0x%08X rsr=0x%08X imr=0x%08X\n", __FUNCTION__,
283 isr, rsr, imr));
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| convex.h | 34 #define imr 13 macro
561 {91,0,imr,A,0,0}, /* halt */
563 {18,6,imr,A,0,0}, /* ld.h */
564 {18,7,imr,A,0,0}, /* ld.w */
565 {5,0,imr,A,0,0}, /* and */
566 {6,0,imr,A,0,0}, /* or */
567 {7,0,imr,A,0,0}, /* xor */
568 {8,0,imr,A,0,0}, /* shf */
569 {9,6,imr,A,0,0}, /* add.h */
570 {9,7,imr,A,0,0}, /* add.w *
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| convex.h | 34 #define imr 13 macro
561 {91,0,imr,A,0,0}, /* halt */
563 {18,6,imr,A,0,0}, /* ld.h */
564 {18,7,imr,A,0,0}, /* ld.w */
565 {5,0,imr,A,0,0}, /* and */
566 {6,0,imr,A,0,0}, /* or */
567 {7,0,imr,A,0,0}, /* xor */
568 {8,0,imr,A,0,0}, /* shf */
569 {9,6,imr,A,0,0}, /* add.h */
570 {9,7,imr,A,0,0}, /* add.w *
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| convex.h | 34 #define imr 13 macro
561 {91,0,imr,A,0,0}, /* halt */
563 {18,6,imr,A,0,0}, /* ld.h */
564 {18,7,imr,A,0,0}, /* ld.w */
565 {5,0,imr,A,0,0}, /* and */
566 {6,0,imr,A,0,0}, /* or */
567 {7,0,imr,A,0,0}, /* xor */
568 {8,0,imr,A,0,0}, /* shf */
569 {9,6,imr,A,0,0}, /* add.h */
570 {9,7,imr,A,0,0}, /* add.w *
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| convex.h | 34 #define imr 13 macro
561 {91,0,imr,A,0,0}, /* halt */
563 {18,6,imr,A,0,0}, /* ld.h */
564 {18,7,imr,A,0,0}, /* ld.w */
565 {5,0,imr,A,0,0}, /* and */
566 {6,0,imr,A,0,0}, /* or */
567 {7,0,imr,A,0,0}, /* xor */
568 {8,0,imr,A,0,0}, /* shf */
569 {9,6,imr,A,0,0}, /* add.h */
570 {9,7,imr,A,0,0}, /* add.w *
[all...] |
| /src/sys/arch/sgimips/dev/ |
| scnvar.h | 104 u_char imr; /* IMR bits */ member in struct:duart
|
| /src/sys/arch/zaurus/zaurus/ |
| machdep.c | 577 uint16_t mcr, cdr, csr, cpr, ccr, irr, irm, imr, isr; local
587 imr = ioreg16_read(baseaddr + SCOOP_IMR);
594 irr == 0 && irm == 0 && imr == 0 && isr == 0 &&
|
| /src/sys/arch/arm/rockchip/ |
| rk_spi.c | 407 uint32_t imr = SPI_IMR_RFOIM | SPI_IMR_RFUIM | SPI_IMR_TFOIM; local
418 imr |= SPI_IMR_RFFIM;
429 imr |= SPI_IMR_TFEIM;
433 if (!ISSET(imr, (SPI_IMR_RFFIM | SPI_IMR_TFEIM))) {
435 imr |= SPI_IMR_TFEIM;
438 SPIREG_WRITE(sc, SPI_IMR, imr);
|
| /src/sys/arch/hppa/dev/ |
| mongoose.c | 283 volatile uint8_t *imr, *pic; local
307 imr = &sc->sc_ctrl->imr0;
310 imr = &sc->sc_ctrl->imr1;
315 *imr |= 1 << irq;
329 volatile uint8_t *imr; local
337 imr = &sc->sc_ctrl->imr0;
339 imr = &sc->sc_ctrl->imr1;
340 *imr &= ~(1 << irq);
|
| /src/sys/dev/pci/ |
| if_msk.c | 2540 uint32_t imr, imtimer_ticks; local
2636 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2637 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
|
| if_sk.c | 2723 uint32_t imr, imtimer_ticks; local
2840 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2841 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
|
