| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dp_link_training.c | 48 int lane; local
52 for (lane = 0; lane < intel_dp->lane_count; lane++) {
53 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
54 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
70 for (lane = 0; lane < 4; lane++)
71 intel_dp->train_set[lane] = v | p
124 int lane; local
[all...] |
| intel_dpio_phy.c | 47 * houses a common lane part which contains the PLL and other common
48 * logic. CH0 common lane also contains the IOSF-SB logic for the
63 * Additionally the PHY also contains an AUX lane with AUX blocks
69 * Generally on VLV/CHV the common lane corresponds to the pipe and
284 * can read only lane registers and we pick lanes 0/1 for that.
602 int lane; local
606 for (lane = 0; lane < 4; lane++) {
607 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
628 int lane; local
[all...] |
| icl_dsi.c | 213 int lane; local
258 for (lane = 0; lane <= 3; lane++) {
260 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
266 I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
398 int lane; local
405 for (lane = 0; lane <= 3; lane++)
[all...] |
| /src/external/apache2/argon2/dist/phc-winner-argon2/src/ |
| core.h | 91 uint32_t lane; member in struct:Argon2_position_t
141 * Computes absolute position of reference block in the lane following a skewed
146 * @param same_lane Indicates if the block will be taken from the current lane.
177 * Function creates first 2 blocks per lane
186 * two blocks. Returns the pointer to the main memory with 2 blocks per lane
197 * XORing the last block of each lane, hashing it, making the tag. Deallocates
222 * blocks in each lane
|
| /src/sys/arch/arm/rockchip/ |
| rk3399_pcie_phy.c | 120 uint8_t * const lane = priv; local
122 // device_printf(dev, "%s %u %u\n", __func__, *lane, enable);
125 rkpcie_phy_poweron(sc, *lane);
126 sc->sc_phys_on |= 1U << *lane;
129 sc->sc_phys_on &= ~(1U << *lane);
202 rkpcie_phy_poweron(struct rkpciephy_softc *sc, u_int lane)
219 RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0);
|
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_pwhash/argon2/ |
| argon2-core.h | 115 uint32_t lane; member in struct:Argon2_position_t
130 * Computes absolute position of reference block in the lane following a skewed
135 * @param same_lane Indicates if the block will be taken from the current lane.
145 * This lane : all already finished segments plus already constructed
149 * This lane : (SYNC_POINTS - 1) last segments plus already constructed
165 /* The same lane => add current segment */
233 * Function creates first 2 blocks per lane
242 * two blocks. Returns the pointer to the main memory with 2 blocks per lane
258 * XORing the last block of each lane, hashing it, making the tag. Deallocates
291 * blocks in each lane
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 93 u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local
95 u8 lpre = (lane & 0x0c) >> 2;
96 u8 lvsw = (lane & 0x03) >> 0;
114 OUTP_TRACE(&dp->outp, "config lane %d %02x %02x",
180 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
181 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
183 if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) ||
184 !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED))
208 u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
209 if (!(lane & DPCD_LS02_LANE0_CR_DONE))
494 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; local
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_atombios_dp.c | 217 int lane; local
219 for (lane = 0; lane < lane_count; lane++) {
220 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
221 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
223 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
224 lane,
244 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_link_encoder.c | 1089 * by checking lane count that has been set
1119 int32_t lane = 0; local
1135 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1136 /* translate lane settings */
1139 link_settings->lane_settings[lane].VOLTAGE_SWING;
1141 link_settings->lane_settings[lane].PRE_EMPHASIS;
1149 link_settings->lane_settings[lane].POST_CURSOR2;
1152 cntl.lane_select = lane;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_link_encoder.c | 1054 * by checking lane count that has been set
1085 int32_t lane = 0; local
1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
1102 /* translate lane settings */
1105 link_settings->lane_settings[lane].VOLTAGE_SWING;
1107 link_settings->lane_settings[lane].PRE_EMPHASIS;
1115 link_settings->lane_settings[lane].POST_CURSOR2;
1118 cntl.lane_select = lane;
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_atombios_dp.c | 275 int lane; local
277 for (lane = 0; lane < lane_count; lane++) {
278 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
279 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
281 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
282 lane,
302 for (lane = 0; lane < 4; lane++
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/ |
| drm_dp_helper.c | 62 int lane)
64 int i = DP_LANE0_1_STATUS + (lane >> 1);
65 int s = (lane & 1) * 4;
75 int lane; local
81 for (lane = 0; lane < lane_count; lane++) {
82 lane_status = dp_get_lane_status(link_status, lane);
93 int lane; local
96 for (lane = 0; lane < lane_count; lane++)
[all...] |
| /src/sys/arch/arm/nvidia/ |
| tegra210_xusbpad.c | 663 tegra210_xusbpad_find_func(const struct tegra210_xusbpad_lane *lane,
666 for (int n = 0; n < lane->nfuncs; n++)
667 if (strcmp(lane->funcs[n], func) == 0)
685 const struct tegra210_xusbpad_lane *lane; local
700 lane = tegra210_xusbpad_find_lane(name);
701 if (lane == NULL) {
702 aprint_error_dev(sc->sc_dev, "unsupported lane '%s'\n", name);
705 func = tegra210_xusbpad_find_func(lane, function);
711 aprint_normal_dev(sc->sc_dev, "lane %s: set func %s\n", name, function);
712 SETCLR4(sc, lane->reg, __SHIFTIN(func, lane->mask), lane->mask)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_link_dp.c | 175 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
185 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
245 uint32_t lane; local
278 for (lane = 0; lane <
279 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
281 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
282 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
283 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
284 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS)
354 uint32_t lane; local
369 uint32_t lane; local
387 uint32_t lane; local
437 uint32_t lane; local
541 uint32_t lane; local
648 uint32_t lane; local
728 uint32_t lane; local
750 uint32_t lane; local
1107 uint32_t lane; local
1796 uint32_t lane; local
2507 unsigned int lane; local
3797 unsigned int lane; local
[all...] |
| /src/crypto/external/apache2/openssl/dist/providers/implementations/kdfs/ |
| argon2.c | 150 uint32_t lane; member in struct:__anon545
246 static void fill_segment(const KDF_ARGON2 *ctx, uint32_t pass, uint32_t lane,
350 * Make the first and second block in each lane as G(H0||0||i)
416 * This lane: all already finished segments plus already constructed blocks
421 * This lane: (SYNC_POINTS - 1) last segments plus already constructed
461 static void fill_segment(const KDF_ARGON2 *ctx, uint32_t pass, uint32_t lane,
482 input_block.v[1] = lane;
498 curr_offset = lane * ctx->lane_length + slice * ctx->segment_length
519 /* Computing the lane of the reference block */
523 ref_lane = lane;
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| rs6000-p8swap.cc | 84 which we should adjust the selected lane of the input. We should
714 processing to see if we can change the lane for the splat. */
720 /* A vec_extract operation is ok if we change the lane. */
1000 /* Otherwise check the operands for vector lane violations. */
1249 of the extracted lane to account for the doubleword swap. */
1262 int lane = INTVAL (XVECEXP (par, 0, 0)); local
1263 lane = lane >= half_elts ? lane - half_elts : lane + half_elts
1280 int lane = INTVAL (XVECEXP (unspec, 0, 1)); local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| rs6000-p8swap.cc | 84 which we should adjust the selected lane of the input. We should
712 processing to see if we can change the lane for the splat. */
718 /* A vec_extract operation is ok if we change the lane. */
998 /* Otherwise check the operands for vector lane violations. */
1247 of the extracted lane to account for the doubleword swap. */
1260 int lane = INTVAL (XVECEXP (par, 0, 0)); local
1261 lane = lane >= half_elts ? lane - half_elts : lane + half_elts
1278 int lane = INTVAL (XVECEXP (unspec, 0, 1)); local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/gcn/ |
| gcn.cc | 1732 /* Load vector constant where n-th lane contains BASE+n*VAL. */
2719 int lane = saved_scalars % 64; local
2723 emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane)));
2727 emit_insn (gen_vec_extractv64sisi (reg, vreg, GEN_INT (lane)));
4090 /* Return an RTX that references a vector with the i-th lane containing
4101 /* Permutation addresses use byte addressing. With each vector lane being
4227 /* Masking a lane masks both the destination and source lanes for
4281 All GCN vectors are 64-lane, so this is simpler than other architectures.
4354 SHIFT must be a power of 2. If SHIFT is 16, the 15th lane of each row is
4356 each row). If SHIFT is 32, lane 31 is broadcast to all th
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/gcn/ |
| gcn.cc | 2162 /* Load vector constant where n-th lane contains BASE+n*VAL. */
3137 int lane = saved_scalars % 64; local
3141 emit_insn (gen_vec_setv64si (vreg, reg, GEN_INT (lane)));
3145 emit_insn (gen_vec_extractv64sisi (reg, vreg, GEN_INT (lane)));
5066 /* Return an RTX that references a vector with the i-th lane containing
5078 /* Permutation addresses use byte addressing. With each vector lane being
5184 /* Masking a lane masks both the destination and source lanes for
5246 /* RDNA devices have 32-lane vectors with limited support for 64-bit vectors
5248 span the 32-lane boundary).
5350 All GCN vectors are 64-lane, so this is simpler than other architectures
[all...] |
| /src/external/gpl3/gcc/dist/gcc/ |
| omp-low.cc | 4553 tree lane;
4617 sctx->lane = create_tmp_var (unsigned_type_node);
4691 lvar = build4 (ARRAY_REF, TREE_TYPE (new_var), avar, sctx->lane,
6808 normal lastprivate, as there will be just one simd lane
6818 if (sctx.lane == NULL_TREE)
6821 sctx.lane = create_tmp_var (unsigned_type_node);
6827 if (sctx.lane || sctx.is_simt)
6854 if (sctx.lane)
6860 gimple_call_set_lhs (g, sctx.lane);
6863 g = gimple_build_assign (sctx.lane, INTEGER_CST
4552 tree lane; member in class:omplow_simd_context
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| aarch64-builtins.cc | 159 /* Lane indices - must be in range, and flipped for bigendian. */
161 /* Lane indices for single lane structure loads and stores. */
163 /* Lane indices selected in pairs. - must be in range, and flipped for
166 /* Lane indices selected in quadtuplets. - must be in range, and flipped for
541 bool lane; member in struct:__anon15266
589 /* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */
1117 /* Due to the architecture not providing lane variant of the lane instructions
1890 /* Keep to GCC-vector-extension lane indices in the RTL. *
1922 int lane = INTVAL (op[opc]); local
1939 int lane = INTVAL (op[opc]); local
2194 int lane = INTVAL (lane_idx); local
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/ |
| omp-low.cc | 4595 tree lane;
4659 sctx->lane = create_tmp_var (unsigned_type_node);
4733 lvar = build4 (ARRAY_REF, TREE_TYPE (new_var), avar, sctx->lane,
6850 normal lastprivate, as there will be just one simd lane
6860 if (sctx.lane == NULL_TREE)
6863 sctx.lane = create_tmp_var (unsigned_type_node);
6869 if (sctx.lane || sctx.is_simt)
6896 if (sctx.lane)
6902 gimple_call_set_lhs (g, sctx.lane);
6905 g = gimple_build_assign (sctx.lane, INTEGER_CST
4594 tree lane; member in class:omplow_simd_context
[all...] |
| tree-vect-slp.cc | 1428 /* For each lane linearize the addition/subtraction (or other
1788 HOST_WIDE_INT lane; local
1792 bit_field_size (bfref), &lane))
1798 lperm.safe_push (std::make_pair (0, (unsigned)lane));
1851 for (unsigned lane = 0; lane < group_size; ++lane)
1853 /* For each lane linearize the addition/subtraction (or other
1857 stmts[lane]->stmt, op_stmt, other_op_stmt,
1872 matches[lane] = false
1925 unsigned lane; local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| aarch64-builtins.cc | 676 bool lane; member in struct:__anon12645
741 /* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */
1279 /* Due to the architecture not providing lane variant of the lane instructions
2311 /* Keep to GCC-vector-extension lane indices in the RTL. */
2326 /* Keep to GCC-vector-extension lane indices in the RTL. */
2329 /* If the lane index isn't a constant then error out. */
2342 /* Keep to GCC-vector-extension lane indices in the RTL. */
2343 int lane = INTVAL (op[opc]); local
2344 op[opc] = gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane),
2360 int lane = INTVAL (op[opc]); local
2615 int lane = INTVAL (lane_idx); local
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/i386/ |
| i386-expand.cc | 5483 if it requests element from the same 128-bit lane
5484 and MSB set if it requests element from the other 128-bit lane.
5491 /* The bit whether element is from the same lane or the other
5492 lane is bit 4, so shift it up by 3 to the MSB position. */
5498 /* After this t1 will have MSB set for elements from other lane. */
5505 lane. */
5517 element from the other 128-bit lane is needed, otherwise
19956 /* We can only permute within the 128-bit lane. */
19971 /* Within each 128-bit lane, the elements of op0 are numbered
21080 The lack of cross-lane shuffling in some instruction
21722 unsigned i, nelt = d->nelt, nelt2 = nelt \/ 2, lane = nelt; local
[all...] |
