1 /* $NetBSD: radeon_atombios_dp.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: radeon_atombios_dp.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $"); 32 33 #include <drm/radeon_drm.h> 34 #include "radeon.h" 35 36 #include "atom.h" 37 #include "atom-bits.h" 38 #include <drm/drm_dp_helper.h> 39 40 #include <linux/nbsd-namespace.h> 41 42 /* move these to drm_dp_helper.c/h */ 43 #define DP_LINK_CONFIGURATION_SIZE 9 44 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 45 46 static const char *voltage_names[] = { 47 "0.4V", "0.6V", "0.8V", "1.2V" 48 }; 49 static const char *pre_emph_names[] = { 50 "0dB", "3.5dB", "6dB", "9.5dB" 51 }; 52 53 /***** radeon AUX functions *****/ 54 55 /* Atom needs data in little endian format so swap as appropriate when copying 56 * data to or from atom. Note that atom operates on dw units. 57 * 58 * Use to_le=true when sending data to atom and provide at least 59 * ALIGN(num_bytes,4) bytes in the dst buffer. 60 * 61 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4) 62 * byes in the src buffer. 63 */ 64 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 65 { 66 #ifdef __BIG_ENDIAN 67 u32 src_tmp[5], dst_tmp[5]; 68 int i; 69 u8 align_num_bytes = ALIGN(num_bytes, 4); 70 71 if (to_le) { 72 memcpy(src_tmp, src, num_bytes); 73 for (i = 0; i < align_num_bytes / 4; i++) 74 dst_tmp[i] = cpu_to_le32(src_tmp[i]); 75 memcpy(dst, dst_tmp, align_num_bytes); 76 } else { 77 memcpy(src_tmp, src, align_num_bytes); 78 for (i = 0; i < align_num_bytes / 4; i++) 79 dst_tmp[i] = le32_to_cpu(src_tmp[i]); 80 memcpy(dst, dst_tmp, num_bytes); 81 } 82 #else 83 memcpy(dst, src, num_bytes); 84 #endif 85 } 86 87 union aux_channel_transaction { 88 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 89 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 90 }; 91 92 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, 93 u8 *send, int send_bytes, 94 u8 *recv, int recv_size, 95 u8 delay, u8 *ack) 96 { 97 struct drm_device *dev = chan->dev; 98 struct radeon_device *rdev = dev->dev_private; 99 union aux_channel_transaction args; 100 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 101 unsigned char *base; 102 int recv_bytes; 103 int r = 0; 104 105 memset(&args, 0, sizeof(args)); 106 107 mutex_lock(&chan->mutex); 108 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); 109 110 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); 111 112 radeon_atom_copy_swap(base, send, send_bytes, true); 113 114 args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 115 args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); 116 args.v1.ucDataOutLen = 0; 117 args.v1.ucChannelID = chan->rec.i2c_id; 118 args.v1.ucDelay = delay / 10; 119 if (ASIC_IS_DCE4(rdev)) 120 args.v2.ucHPD_ID = chan->rec.hpd; 121 122 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args); 123 124 *ack = args.v1.ucReplyStatus; 125 126 /* timeout */ 127 if (args.v1.ucReplyStatus == 1) { 128 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 129 r = -ETIMEDOUT; 130 goto done; 131 } 132 133 /* flags not zero */ 134 if (args.v1.ucReplyStatus == 2) { 135 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 136 r = -EIO; 137 goto done; 138 } 139 140 /* error */ 141 if (args.v1.ucReplyStatus == 3) { 142 DRM_DEBUG_KMS("dp_aux_ch error\n"); 143 r = -EIO; 144 goto done; 145 } 146 147 recv_bytes = args.v1.ucDataOutLen; 148 if (recv_bytes > recv_size) 149 recv_bytes = recv_size; 150 151 if (recv && recv_size) 152 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); 153 154 r = recv_bytes; 155 done: 156 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex); 157 mutex_unlock(&chan->mutex); 158 159 return r; 160 } 161 162 #define BARE_ADDRESS_SIZE 3 163 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 164 165 static ssize_t 166 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 167 { 168 struct radeon_i2c_chan *chan = 169 container_of(aux, struct radeon_i2c_chan, aux); 170 int ret; 171 u8 tx_buf[20]; 172 size_t tx_size; 173 u8 ack, delay = 0; 174 175 if (WARN_ON(msg->size > 16)) 176 return -E2BIG; 177 178 tx_buf[0] = msg->address & 0xff; 179 tx_buf[1] = (msg->address >> 8) & 0xff; 180 tx_buf[2] = (msg->request << 4) | 181 ((msg->address >> 16) & 0xf); 182 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 183 184 switch (msg->request & ~DP_AUX_I2C_MOT) { 185 case DP_AUX_NATIVE_WRITE: 186 case DP_AUX_I2C_WRITE: 187 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 188 /* The atom implementation only supports writes with a max payload of 189 * 12 bytes since it uses 4 bits for the total count (header + payload) 190 * in the parameter space. The atom interface supports 16 byte 191 * payloads for reads. The hw itself supports up to 16 bytes of payload. 192 */ 193 if (WARN_ON_ONCE(msg->size > 12)) 194 return -E2BIG; 195 /* tx_size needs to be 4 even for bare address packets since the atom 196 * table needs the info in tx_buf[3]. 197 */ 198 tx_size = HEADER_SIZE + msg->size; 199 if (msg->size == 0) 200 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 201 else { 202 tx_buf[3] |= tx_size << 4; 203 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 204 } 205 ret = radeon_process_aux_ch(chan, 206 tx_buf, tx_size, NULL, 0, delay, &ack); 207 if (ret >= 0) 208 /* Return payload size. */ 209 ret = msg->size; 210 break; 211 case DP_AUX_NATIVE_READ: 212 case DP_AUX_I2C_READ: 213 /* tx_size needs to be 4 even for bare address packets since the atom 214 * table needs the info in tx_buf[3]. 215 */ 216 tx_size = HEADER_SIZE; 217 if (msg->size == 0) 218 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 219 else 220 tx_buf[3] |= tx_size << 4; 221 ret = radeon_process_aux_ch(chan, 222 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 223 break; 224 default: 225 ret = -EINVAL; 226 break; 227 } 228 229 if (ret >= 0) 230 msg->reply = ack >> 4; 231 232 return ret; 233 } 234 235 void radeon_dp_aux_init(struct radeon_connector *radeon_connector) 236 { 237 struct drm_device *dev = radeon_connector->base.dev; 238 struct radeon_device *rdev = dev->dev_private; 239 int ret; 240 241 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd; 242 radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev; 243 if (ASIC_IS_DCE5(rdev)) { 244 if (radeon_auxch) 245 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native; 246 else 247 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 248 } else { 249 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom; 250 } 251 252 #ifdef __NetBSD__ 253 /* XXX dervied from sysfs/i2c on linux. */ 254 radeon_connector->ddc_bus->aux.name = "radeon_dp_aux"; 255 #endif 256 257 ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux); 258 if (!ret) 259 radeon_connector->ddc_bus->has_aux = true; 260 261 WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret); 262 } 263 264 /***** general DP utility functions *****/ 265 266 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 267 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 268 269 static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 270 int lane_count, 271 u8 train_set[4]) 272 { 273 u8 v = 0; 274 u8 p = 0; 275 int lane; 276 277 for (lane = 0; lane < lane_count; lane++) { 278 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 279 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 280 281 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 282 lane, 283 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 284 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 285 286 if (this_v > v) 287 v = this_v; 288 if (this_p > p) 289 p = this_p; 290 } 291 292 if (v >= DP_VOLTAGE_MAX) 293 v |= DP_TRAIN_MAX_SWING_REACHED; 294 295 if (p >= DP_PRE_EMPHASIS_MAX) 296 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 297 298 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 299 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 300 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 301 302 for (lane = 0; lane < 4; lane++) 303 train_set[lane] = v | p; 304 } 305 306 /* convert bits per color to bits per pixel */ 307 /* get bpc from the EDID */ 308 static int convert_bpc_to_bpp(int bpc) 309 { 310 if (bpc == 0) 311 return 24; 312 else 313 return bpc * 3; 314 } 315 316 /***** radeon specific DP functions *****/ 317 318 static int radeon_dp_get_dp_link_config(struct drm_connector *connector, 319 const u8 dpcd[DP_DPCD_SIZE], 320 unsigned pix_clock, 321 unsigned *dp_lanes, unsigned *dp_rate) 322 { 323 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); 324 static const unsigned link_rates[3] = { 162000, 270000, 540000 }; 325 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); 326 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 327 unsigned lane_num, i, max_pix_clock; 328 329 if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 330 ENCODER_OBJECT_ID_NUTMEG) { 331 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 332 max_pix_clock = (lane_num * 270000 * 8) / bpp; 333 if (max_pix_clock >= pix_clock) { 334 *dp_lanes = lane_num; 335 *dp_rate = 270000; 336 return 0; 337 } 338 } 339 } else { 340 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { 341 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 342 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; 343 if (max_pix_clock >= pix_clock) { 344 *dp_lanes = lane_num; 345 *dp_rate = link_rates[i]; 346 return 0; 347 } 348 } 349 } 350 } 351 352 return -EINVAL; 353 } 354 355 static u8 radeon_dp_encoder_service(struct radeon_device *rdev, 356 int action, int dp_clock, 357 u8 ucconfig, u8 lane_num) 358 { 359 DP_ENCODER_SERVICE_PARAMETERS args; 360 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 361 362 memset(&args, 0, sizeof(args)); 363 args.ucLinkClock = dp_clock / 10; 364 args.ucConfig = ucconfig; 365 args.ucAction = action; 366 args.ucLaneNum = lane_num; 367 args.ucStatus = 0; 368 369 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 370 return args.ucStatus; 371 } 372 373 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) 374 { 375 struct drm_device *dev = radeon_connector->base.dev; 376 struct radeon_device *rdev = dev->dev_private; 377 378 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 379 radeon_connector->ddc_bus->rec.i2c_id, 0); 380 } 381 382 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 383 { 384 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 385 u8 buf[3]; 386 387 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 388 return; 389 390 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 391 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n", 392 buf[0], buf[1], buf[2]); 393 394 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 395 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n", 396 buf[0], buf[1], buf[2]); 397 } 398 399 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 400 { 401 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; 402 u8 msg[DP_DPCD_SIZE]; 403 int ret; 404 405 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg, 406 DP_DPCD_SIZE); 407 if (ret == DP_DPCD_SIZE) { 408 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 409 410 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 411 dig_connector->dpcd); 412 413 radeon_dp_probe_oui(radeon_connector); 414 415 return true; 416 } 417 418 dig_connector->dpcd[0] = 0; 419 return false; 420 } 421 422 int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 423 struct drm_connector *connector) 424 { 425 struct drm_device *dev = encoder->dev; 426 struct radeon_device *rdev = dev->dev_private; 427 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 428 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 429 u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); 430 u8 tmp; 431 432 if (!ASIC_IS_DCE4(rdev)) 433 return panel_mode; 434 435 if (!radeon_connector->con_priv) 436 return panel_mode; 437 438 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 439 /* DP bridge chips */ 440 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 441 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 442 if (tmp & 1) 443 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 444 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 445 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 446 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 447 else 448 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 449 } 450 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 451 /* eDP */ 452 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, 453 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 454 if (tmp & 1) 455 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 456 } 457 } 458 459 return panel_mode; 460 } 461 462 void radeon_dp_set_link_config(struct drm_connector *connector, 463 const struct drm_display_mode *mode) 464 { 465 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 466 struct radeon_connector_atom_dig *dig_connector; 467 int ret; 468 469 if (!radeon_connector->con_priv) 470 return; 471 dig_connector = radeon_connector->con_priv; 472 473 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 474 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 475 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, 476 mode->clock, 477 &dig_connector->dp_lane_count, 478 &dig_connector->dp_clock); 479 if (ret) { 480 dig_connector->dp_clock = 0; 481 dig_connector->dp_lane_count = 0; 482 } 483 } 484 } 485 486 int radeon_dp_mode_valid_helper(struct drm_connector *connector, 487 struct drm_display_mode *mode) 488 { 489 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 490 struct radeon_connector_atom_dig *dig_connector; 491 unsigned dp_clock, dp_lanes; 492 int ret; 493 494 if ((mode->clock > 340000) && 495 (!radeon_connector_is_dp12_capable(connector))) 496 return MODE_CLOCK_HIGH; 497 498 if (!radeon_connector->con_priv) 499 return MODE_CLOCK_HIGH; 500 dig_connector = radeon_connector->con_priv; 501 502 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, 503 mode->clock, 504 &dp_lanes, 505 &dp_clock); 506 if (ret) 507 return MODE_CLOCK_HIGH; 508 509 if ((dp_clock == 540000) && 510 (!radeon_connector_is_dp12_capable(connector))) 511 return MODE_CLOCK_HIGH; 512 513 return MODE_OK; 514 } 515 516 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) 517 { 518 u8 link_status[DP_LINK_STATUS_SIZE]; 519 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 520 521 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status) 522 <= 0) 523 return false; 524 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 525 return false; 526 return true; 527 } 528 529 void radeon_dp_set_rx_power_state(struct drm_connector *connector, 530 u8 power_state) 531 { 532 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 533 struct radeon_connector_atom_dig *dig_connector; 534 535 if (!radeon_connector->con_priv) 536 return; 537 538 dig_connector = radeon_connector->con_priv; 539 540 /* power up/down the sink */ 541 if (dig_connector->dpcd[0] >= 0x11) { 542 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux, 543 DP_SET_POWER, power_state); 544 usleep_range(1000, 2000); 545 } 546 } 547 548 549 struct radeon_dp_link_train_info { 550 struct radeon_device *rdev; 551 struct drm_encoder *encoder; 552 struct drm_connector *connector; 553 int enc_id; 554 int dp_clock; 555 int dp_lane_count; 556 bool tp3_supported; 557 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 558 u8 train_set[4]; 559 u8 link_status[DP_LINK_STATUS_SIZE]; 560 u8 tries; 561 bool use_dpencoder; 562 struct drm_dp_aux *aux; 563 }; 564 565 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) 566 { 567 /* set the initial vs/emph on the source */ 568 atombios_dig_transmitter_setup(dp_info->encoder, 569 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 570 0, dp_info->train_set[0]); /* sets all lanes at once */ 571 572 /* set the vs/emph on the sink */ 573 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 574 dp_info->train_set, dp_info->dp_lane_count); 575 } 576 577 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) 578 { 579 int rtp = 0; 580 581 /* set training pattern on the source */ 582 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { 583 switch (tp) { 584 case DP_TRAINING_PATTERN_1: 585 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 586 break; 587 case DP_TRAINING_PATTERN_2: 588 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 589 break; 590 case DP_TRAINING_PATTERN_3: 591 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 592 break; 593 } 594 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); 595 } else { 596 switch (tp) { 597 case DP_TRAINING_PATTERN_1: 598 rtp = 0; 599 break; 600 case DP_TRAINING_PATTERN_2: 601 rtp = 1; 602 break; 603 } 604 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, 605 dp_info->dp_clock, dp_info->enc_id, rtp); 606 } 607 608 /* enable training pattern on the sink */ 609 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 610 } 611 612 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) 613 { 614 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); 615 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 616 u8 tmp; 617 618 /* power up the sink */ 619 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 620 621 /* possibly enable downspread on the sink */ 622 if (dp_info->dpcd[3] & 0x1) 623 drm_dp_dpcd_writeb(dp_info->aux, 624 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 625 else 626 drm_dp_dpcd_writeb(dp_info->aux, 627 DP_DOWNSPREAD_CTRL, 0); 628 629 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 630 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 631 632 /* set the lane count on the sink */ 633 tmp = dp_info->dp_lane_count; 634 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 635 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 636 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 637 638 /* set the link rate on the sink */ 639 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 640 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 641 642 /* start training on the source */ 643 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 644 atombios_dig_encoder_setup(dp_info->encoder, 645 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 646 else 647 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, 648 dp_info->dp_clock, dp_info->enc_id, 0); 649 650 /* disable the training pattern on the sink */ 651 drm_dp_dpcd_writeb(dp_info->aux, 652 DP_TRAINING_PATTERN_SET, 653 DP_TRAINING_PATTERN_DISABLE); 654 655 return 0; 656 } 657 658 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) 659 { 660 udelay(400); 661 662 /* disable the training pattern on the sink */ 663 drm_dp_dpcd_writeb(dp_info->aux, 664 DP_TRAINING_PATTERN_SET, 665 DP_TRAINING_PATTERN_DISABLE); 666 667 /* disable the training pattern on the source */ 668 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) 669 atombios_dig_encoder_setup(dp_info->encoder, 670 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 671 else 672 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, 673 dp_info->dp_clock, dp_info->enc_id, 0); 674 675 return 0; 676 } 677 678 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) 679 { 680 bool clock_recovery; 681 u8 voltage; 682 int i; 683 684 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 685 memset(dp_info->train_set, 0, 4); 686 radeon_dp_update_vs_emph(dp_info); 687 688 udelay(400); 689 690 /* clock recovery loop */ 691 clock_recovery = false; 692 dp_info->tries = 0; 693 voltage = 0xff; 694 while (1) { 695 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 696 697 if (drm_dp_dpcd_read_link_status(dp_info->aux, 698 dp_info->link_status) <= 0) { 699 DRM_ERROR("displayport link status failed\n"); 700 break; 701 } 702 703 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 704 clock_recovery = true; 705 break; 706 } 707 708 for (i = 0; i < dp_info->dp_lane_count; i++) { 709 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 710 break; 711 } 712 if (i == dp_info->dp_lane_count) { 713 DRM_ERROR("clock recovery reached max voltage\n"); 714 break; 715 } 716 717 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 718 ++dp_info->tries; 719 if (dp_info->tries == 5) { 720 DRM_ERROR("clock recovery tried 5 times\n"); 721 break; 722 } 723 } else 724 dp_info->tries = 0; 725 726 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 727 728 /* Compute new train_set as requested by sink */ 729 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 730 731 radeon_dp_update_vs_emph(dp_info); 732 } 733 if (!clock_recovery) { 734 DRM_ERROR("clock recovery failed\n"); 735 return -1; 736 } else { 737 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 738 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 739 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 740 DP_TRAIN_PRE_EMPHASIS_SHIFT); 741 return 0; 742 } 743 } 744 745 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) 746 { 747 bool channel_eq; 748 749 if (dp_info->tp3_supported) 750 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 751 else 752 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 753 754 /* channel equalization loop */ 755 dp_info->tries = 0; 756 channel_eq = false; 757 while (1) { 758 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 759 760 if (drm_dp_dpcd_read_link_status(dp_info->aux, 761 dp_info->link_status) <= 0) { 762 DRM_ERROR("displayport link status failed\n"); 763 break; 764 } 765 766 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 767 channel_eq = true; 768 break; 769 } 770 771 /* Try 5 times */ 772 if (dp_info->tries > 5) { 773 DRM_ERROR("channel eq failed: 5 tries\n"); 774 break; 775 } 776 777 /* Compute new train_set as requested by sink */ 778 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); 779 780 radeon_dp_update_vs_emph(dp_info); 781 dp_info->tries++; 782 } 783 784 if (!channel_eq) { 785 DRM_ERROR("channel eq failed\n"); 786 return -1; 787 } else { 788 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 789 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 790 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 791 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 792 return 0; 793 } 794 } 795 796 void radeon_dp_link_train(struct drm_encoder *encoder, 797 struct drm_connector *connector) 798 { 799 struct drm_device *dev = encoder->dev; 800 struct radeon_device *rdev = dev->dev_private; 801 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 802 struct radeon_encoder_atom_dig *dig; 803 struct radeon_connector *radeon_connector; 804 struct radeon_connector_atom_dig *dig_connector; 805 struct radeon_dp_link_train_info dp_info; 806 int index; 807 u8 tmp, frev, crev; 808 809 if (!radeon_encoder->enc_priv) 810 return; 811 dig = radeon_encoder->enc_priv; 812 813 radeon_connector = to_radeon_connector(connector); 814 if (!radeon_connector->con_priv) 815 return; 816 dig_connector = radeon_connector->con_priv; 817 818 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 819 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 820 return; 821 822 /* DPEncoderService newer than 1.1 can't program properly the 823 * training pattern. When facing such version use the 824 * DIGXEncoderControl (X== 1 | 2) 825 */ 826 dp_info.use_dpencoder = true; 827 index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 828 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { 829 if (crev > 1) 830 dp_info.use_dpencoder = false; 831 } 832 833 dp_info.enc_id = 0; 834 if (dig->dig_encoder) 835 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 836 else 837 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 838 if (dig->linkb) 839 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; 840 else 841 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; 842 843 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 844 == 1) { 845 if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) 846 dp_info.tp3_supported = true; 847 else 848 dp_info.tp3_supported = false; 849 } else { 850 dp_info.tp3_supported = false; 851 } 852 853 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 854 dp_info.rdev = rdev; 855 dp_info.encoder = encoder; 856 dp_info.connector = connector; 857 dp_info.dp_lane_count = dig_connector->dp_lane_count; 858 dp_info.dp_clock = dig_connector->dp_clock; 859 dp_info.aux = &radeon_connector->ddc_bus->aux; 860 861 if (radeon_dp_link_train_init(&dp_info)) 862 goto done; 863 if (radeon_dp_link_train_cr(&dp_info)) 864 goto done; 865 if (radeon_dp_link_train_ce(&dp_info)) 866 goto done; 867 done: 868 if (radeon_dp_link_train_finish(&dp_info)) 869 return; 870 } 871
Indexes created Sat Sep 20 22:09:52 GMT 2025