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    Searched defs:min_sclk (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
trinity_dpm.h 81 u32 min_sclk; member in struct:trinity_sys_info
sumo_dpm.h 85 u32 min_sclk; member in struct:sumo_sys_info
radeon_kv_dpm.c 2151 u32 min_sclk = 10000; /* ??? */ local in function:kv_apply_state_adjust_rules
2170 sclk = min_sclk;
radeon_sumo_dpm.c 1052 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1099 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ local in function:sumo_apply_state_adjust_rules
1100 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1120 if (ps->levels[i].sclk < min_sclk)
1122 sumo_get_valid_engine_clock(rdev, min_sclk);
1680 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
radeon_trinity_dpm.c 1408 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1547 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ local in function:trinity_apply_state_adjust_rules
1548 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1571 if (ps->levels[i].sclk < min_sclk)
1573 trinity_get_valid_engine_clock(rdev, min_sclk);
1871 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);
radeon_ni_dpm.c 2464 u32 min_sclk; local in function:ni_populate_power_containment_values
2515 min_sclk = max_sclk;
2517 min_sclk = prev_sclk;
2519 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2521 if (min_sclk < state->performance_levels[0].sclk)
2522 min_sclk = state->performance_levels[0].sclk;
2524 if (min_sclk == 0)
2528 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
radeon_si_dpm.c 2302 u32 min_sclk; local in function:si_populate_power_containment_values
2342 min_sclk = max_sclk;
2344 min_sclk = prev_sclk;
2346 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2349 if (min_sclk < state->performance_levels[0].sclk)
2350 min_sclk = state->performance_levels[0].sclk;
2352 if (min_sclk == 0)
2376 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu10_hwmgr.c 578 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; local in function:smu10_dpm_force_dpm_level
586 if (min_sclk < data->gfx_min_freq_limit)
587 min_sclk = data->gfx_min_freq_limit;
589 min_sclk /= 100; /* transfer 10KHz to MHz */
625 min_sclk);
628 min_sclk);
668 min_sclk);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_kv_dpm.c 2216 u32 min_sclk = 10000; /* ??? */ local in function:kv_apply_state_adjust_rules
2235 sclk = min_sclk;
amdgpu_si_dpm.c 2400 u32 min_sclk; local in function:si_populate_power_containment_values
2440 min_sclk = max_sclk;
2442 min_sclk = prev_sclk;
2444 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2446 if (min_sclk < state->performance_levels[0].sclk)
2447 min_sclk = state->performance_levels[0].sclk;
2449 if (min_sclk == 0)
2473 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

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