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Searched defs:num_tile_mode_states (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v6_0.c	`404 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); local in function:gfx_v6_0_tiling_mode_table_init 645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 851 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1075 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1299 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)`
amdgpu_gfx_v7_0.c	`1033 const u32 num_tile_mode_states = local in function:gfx_v7_0_tiling_mode_table_init 1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1223 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1406 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1576 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)`
amdgpu_gfx_v8_0.c	2102 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); local in function:gfx_v8_0_tiling_mode_table_init 2109 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2277 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2469 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2658 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2861 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3063 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3232 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3409 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c	`2503 const u32 num_tile_mode_states = local in function:si_tiling_mode_table_init 2520 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2734 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2949 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)`
radeon_cik.c	`2350 const u32 num_tile_mode_states = local in function:cik_tiling_mode_table_init 2376 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2519 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2662 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 2887 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 3030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)`

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