1 /* $NetBSD: amdgpu_gfx_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gfx_v6_0.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $"); 27 28 #include <linux/firmware.h> 29 #include <linux/module.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_gfx.h" 34 #include "amdgpu_ucode.h" 35 #include "clearstate_si.h" 36 #include "bif/bif_3_0_d.h" 37 #include "bif/bif_3_0_sh_mask.h" 38 #include "oss/oss_1_0_d.h" 39 #include "oss/oss_1_0_sh_mask.h" 40 #include "gca/gfx_6_0_d.h" 41 #include "gca/gfx_6_0_sh_mask.h" 42 #include "gmc/gmc_6_0_d.h" 43 #include "gmc/gmc_6_0_sh_mask.h" 44 #include "dce/dce_6_0_d.h" 45 #include "dce/dce_6_0_sh_mask.h" 46 #include "gca/gfx_7_2_enum.h" 47 #include "si_enums.h" 48 #include "si.h" 49 50 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev); 51 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev); 52 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev); 53 54 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin"); 55 MODULE_FIRMWARE("amdgpu/tahiti_me.bin"); 56 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin"); 57 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin"); 58 59 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin"); 60 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin"); 61 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin"); 62 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin"); 63 64 MODULE_FIRMWARE("amdgpu/verde_pfp.bin"); 65 MODULE_FIRMWARE("amdgpu/verde_me.bin"); 66 MODULE_FIRMWARE("amdgpu/verde_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/verde_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/oland_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/oland_me.bin"); 71 MODULE_FIRMWARE("amdgpu/oland_ce.bin"); 72 MODULE_FIRMWARE("amdgpu/oland_rlc.bin"); 73 74 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/hainan_me.bin"); 76 MODULE_FIRMWARE("amdgpu/hainan_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin"); 78 79 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev); 80 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer); 81 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev); 82 static void gfx_v6_0_init_pg(struct amdgpu_device *adev); 83 84 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) 85 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) 86 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) 87 #define MICRO_TILE_MODE(x) ((x) << 0) 88 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) 89 #define BANK_WIDTH(x) ((x) << 14) 90 #define BANK_HEIGHT(x) ((x) << 16) 91 #define MACRO_TILE_ASPECT(x) ((x) << 18) 92 #define NUM_BANKS(x) ((x) << 20) 93 94 static const u32 verde_rlc_save_restore_register_list[] = 95 { 96 (0x8000 << 16) | (0x98f4 >> 2), 97 0x00000000, 98 (0x8040 << 16) | (0x98f4 >> 2), 99 0x00000000, 100 (0x8000 << 16) | (0xe80 >> 2), 101 0x00000000, 102 (0x8040 << 16) | (0xe80 >> 2), 103 0x00000000, 104 (0x8000 << 16) | (0x89bc >> 2), 105 0x00000000, 106 (0x8040 << 16) | (0x89bc >> 2), 107 0x00000000, 108 (0x8000 << 16) | (0x8c1c >> 2), 109 0x00000000, 110 (0x8040 << 16) | (0x8c1c >> 2), 111 0x00000000, 112 (0x9c00 << 16) | (0x98f0 >> 2), 113 0x00000000, 114 (0x9c00 << 16) | (0xe7c >> 2), 115 0x00000000, 116 (0x8000 << 16) | (0x9148 >> 2), 117 0x00000000, 118 (0x8040 << 16) | (0x9148 >> 2), 119 0x00000000, 120 (0x9c00 << 16) | (0x9150 >> 2), 121 0x00000000, 122 (0x9c00 << 16) | (0x897c >> 2), 123 0x00000000, 124 (0x9c00 << 16) | (0x8d8c >> 2), 125 0x00000000, 126 (0x9c00 << 16) | (0xac54 >> 2), 127 0X00000000, 128 0x3, 129 (0x9c00 << 16) | (0x98f8 >> 2), 130 0x00000000, 131 (0x9c00 << 16) | (0x9910 >> 2), 132 0x00000000, 133 (0x9c00 << 16) | (0x9914 >> 2), 134 0x00000000, 135 (0x9c00 << 16) | (0x9918 >> 2), 136 0x00000000, 137 (0x9c00 << 16) | (0x991c >> 2), 138 0x00000000, 139 (0x9c00 << 16) | (0x9920 >> 2), 140 0x00000000, 141 (0x9c00 << 16) | (0x9924 >> 2), 142 0x00000000, 143 (0x9c00 << 16) | (0x9928 >> 2), 144 0x00000000, 145 (0x9c00 << 16) | (0x992c >> 2), 146 0x00000000, 147 (0x9c00 << 16) | (0x9930 >> 2), 148 0x00000000, 149 (0x9c00 << 16) | (0x9934 >> 2), 150 0x00000000, 151 (0x9c00 << 16) | (0x9938 >> 2), 152 0x00000000, 153 (0x9c00 << 16) | (0x993c >> 2), 154 0x00000000, 155 (0x9c00 << 16) | (0x9940 >> 2), 156 0x00000000, 157 (0x9c00 << 16) | (0x9944 >> 2), 158 0x00000000, 159 (0x9c00 << 16) | (0x9948 >> 2), 160 0x00000000, 161 (0x9c00 << 16) | (0x994c >> 2), 162 0x00000000, 163 (0x9c00 << 16) | (0x9950 >> 2), 164 0x00000000, 165 (0x9c00 << 16) | (0x9954 >> 2), 166 0x00000000, 167 (0x9c00 << 16) | (0x9958 >> 2), 168 0x00000000, 169 (0x9c00 << 16) | (0x995c >> 2), 170 0x00000000, 171 (0x9c00 << 16) | (0x9960 >> 2), 172 0x00000000, 173 (0x9c00 << 16) | (0x9964 >> 2), 174 0x00000000, 175 (0x9c00 << 16) | (0x9968 >> 2), 176 0x00000000, 177 (0x9c00 << 16) | (0x996c >> 2), 178 0x00000000, 179 (0x9c00 << 16) | (0x9970 >> 2), 180 0x00000000, 181 (0x9c00 << 16) | (0x9974 >> 2), 182 0x00000000, 183 (0x9c00 << 16) | (0x9978 >> 2), 184 0x00000000, 185 (0x9c00 << 16) | (0x997c >> 2), 186 0x00000000, 187 (0x9c00 << 16) | (0x9980 >> 2), 188 0x00000000, 189 (0x9c00 << 16) | (0x9984 >> 2), 190 0x00000000, 191 (0x9c00 << 16) | (0x9988 >> 2), 192 0x00000000, 193 (0x9c00 << 16) | (0x998c >> 2), 194 0x00000000, 195 (0x9c00 << 16) | (0x8c00 >> 2), 196 0x00000000, 197 (0x9c00 << 16) | (0x8c14 >> 2), 198 0x00000000, 199 (0x9c00 << 16) | (0x8c04 >> 2), 200 0x00000000, 201 (0x9c00 << 16) | (0x8c08 >> 2), 202 0x00000000, 203 (0x8000 << 16) | (0x9b7c >> 2), 204 0x00000000, 205 (0x8040 << 16) | (0x9b7c >> 2), 206 0x00000000, 207 (0x8000 << 16) | (0xe84 >> 2), 208 0x00000000, 209 (0x8040 << 16) | (0xe84 >> 2), 210 0x00000000, 211 (0x8000 << 16) | (0x89c0 >> 2), 212 0x00000000, 213 (0x8040 << 16) | (0x89c0 >> 2), 214 0x00000000, 215 (0x8000 << 16) | (0x914c >> 2), 216 0x00000000, 217 (0x8040 << 16) | (0x914c >> 2), 218 0x00000000, 219 (0x8000 << 16) | (0x8c20 >> 2), 220 0x00000000, 221 (0x8040 << 16) | (0x8c20 >> 2), 222 0x00000000, 223 (0x8000 << 16) | (0x9354 >> 2), 224 0x00000000, 225 (0x8040 << 16) | (0x9354 >> 2), 226 0x00000000, 227 (0x9c00 << 16) | (0x9060 >> 2), 228 0x00000000, 229 (0x9c00 << 16) | (0x9364 >> 2), 230 0x00000000, 231 (0x9c00 << 16) | (0x9100 >> 2), 232 0x00000000, 233 (0x9c00 << 16) | (0x913c >> 2), 234 0x00000000, 235 (0x8000 << 16) | (0x90e0 >> 2), 236 0x00000000, 237 (0x8000 << 16) | (0x90e4 >> 2), 238 0x00000000, 239 (0x8000 << 16) | (0x90e8 >> 2), 240 0x00000000, 241 (0x8040 << 16) | (0x90e0 >> 2), 242 0x00000000, 243 (0x8040 << 16) | (0x90e4 >> 2), 244 0x00000000, 245 (0x8040 << 16) | (0x90e8 >> 2), 246 0x00000000, 247 (0x9c00 << 16) | (0x8bcc >> 2), 248 0x00000000, 249 (0x9c00 << 16) | (0x8b24 >> 2), 250 0x00000000, 251 (0x9c00 << 16) | (0x88c4 >> 2), 252 0x00000000, 253 (0x9c00 << 16) | (0x8e50 >> 2), 254 0x00000000, 255 (0x9c00 << 16) | (0x8c0c >> 2), 256 0x00000000, 257 (0x9c00 << 16) | (0x8e58 >> 2), 258 0x00000000, 259 (0x9c00 << 16) | (0x8e5c >> 2), 260 0x00000000, 261 (0x9c00 << 16) | (0x9508 >> 2), 262 0x00000000, 263 (0x9c00 << 16) | (0x950c >> 2), 264 0x00000000, 265 (0x9c00 << 16) | (0x9494 >> 2), 266 0x00000000, 267 (0x9c00 << 16) | (0xac0c >> 2), 268 0x00000000, 269 (0x9c00 << 16) | (0xac10 >> 2), 270 0x00000000, 271 (0x9c00 << 16) | (0xac14 >> 2), 272 0x00000000, 273 (0x9c00 << 16) | (0xae00 >> 2), 274 0x00000000, 275 (0x9c00 << 16) | (0xac08 >> 2), 276 0x00000000, 277 (0x9c00 << 16) | (0x88d4 >> 2), 278 0x00000000, 279 (0x9c00 << 16) | (0x88c8 >> 2), 280 0x00000000, 281 (0x9c00 << 16) | (0x88cc >> 2), 282 0x00000000, 283 (0x9c00 << 16) | (0x89b0 >> 2), 284 0x00000000, 285 (0x9c00 << 16) | (0x8b10 >> 2), 286 0x00000000, 287 (0x9c00 << 16) | (0x8a14 >> 2), 288 0x00000000, 289 (0x9c00 << 16) | (0x9830 >> 2), 290 0x00000000, 291 (0x9c00 << 16) | (0x9834 >> 2), 292 0x00000000, 293 (0x9c00 << 16) | (0x9838 >> 2), 294 0x00000000, 295 (0x9c00 << 16) | (0x9a10 >> 2), 296 0x00000000, 297 (0x8000 << 16) | (0x9870 >> 2), 298 0x00000000, 299 (0x8000 << 16) | (0x9874 >> 2), 300 0x00000000, 301 (0x8001 << 16) | (0x9870 >> 2), 302 0x00000000, 303 (0x8001 << 16) | (0x9874 >> 2), 304 0x00000000, 305 (0x8040 << 16) | (0x9870 >> 2), 306 0x00000000, 307 (0x8040 << 16) | (0x9874 >> 2), 308 0x00000000, 309 (0x8041 << 16) | (0x9870 >> 2), 310 0x00000000, 311 (0x8041 << 16) | (0x9874 >> 2), 312 0x00000000, 313 0x00000000 314 }; 315 316 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev) 317 { 318 const char *chip_name; 319 char fw_name[30]; 320 int err; 321 const struct gfx_firmware_header_v1_0 *cp_hdr; 322 const struct rlc_firmware_header_v1_0 *rlc_hdr; 323 324 DRM_DEBUG("\n"); 325 326 switch (adev->asic_type) { 327 case CHIP_TAHITI: 328 chip_name = "tahiti"; 329 break; 330 case CHIP_PITCAIRN: 331 chip_name = "pitcairn"; 332 break; 333 case CHIP_VERDE: 334 chip_name = "verde"; 335 break; 336 case CHIP_OLAND: 337 chip_name = "oland"; 338 break; 339 case CHIP_HAINAN: 340 chip_name = "hainan"; 341 break; 342 default: BUG(); 343 } 344 345 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 346 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 347 if (err) 348 goto out; 349 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 350 if (err) 351 goto out; 352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 353 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 354 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 355 356 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 357 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 358 if (err) 359 goto out; 360 err = amdgpu_ucode_validate(adev->gfx.me_fw); 361 if (err) 362 goto out; 363 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 364 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 365 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 366 367 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 368 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 369 if (err) 370 goto out; 371 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 372 if (err) 373 goto out; 374 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 375 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 376 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 377 378 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 379 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 380 if (err) 381 goto out; 382 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 383 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 384 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 385 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 386 387 out: 388 if (err) { 389 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name); 390 release_firmware(adev->gfx.pfp_fw); 391 adev->gfx.pfp_fw = NULL; 392 release_firmware(adev->gfx.me_fw); 393 adev->gfx.me_fw = NULL; 394 release_firmware(adev->gfx.ce_fw); 395 adev->gfx.ce_fw = NULL; 396 release_firmware(adev->gfx.rlc_fw); 397 adev->gfx.rlc_fw = NULL; 398 } 399 return err; 400 } 401 402 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev) 403 { 404 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array); 405 u32 reg_offset, split_equal_to_row_size, *tilemode; 406 407 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array)); 408 tilemode = adev->gfx.config.tile_mode_array; 409 410 switch (adev->gfx.config.mem_row_size_in_kb) { 411 case 1: 412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 413 break; 414 case 2: 415 default: 416 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 417 break; 418 case 4: 419 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 420 break; 421 } 422 423 if (adev->asic_type == CHIP_VERDE) { 424 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 425 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 426 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 427 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 428 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 429 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 430 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 431 NUM_BANKS(ADDR_SURF_16_BANK); 432 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 433 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 434 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 435 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 436 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 437 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 438 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 439 NUM_BANKS(ADDR_SURF_16_BANK); 440 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 442 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 447 NUM_BANKS(ADDR_SURF_16_BANK); 448 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 450 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 454 NUM_BANKS(ADDR_SURF_8_BANK) | 455 TILE_SPLIT(split_equal_to_row_size); 456 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 457 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 458 PIPE_CONFIG(ADDR_SURF_P4_8x16); 459 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 460 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 461 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 462 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 463 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 464 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 465 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 466 NUM_BANKS(ADDR_SURF_4_BANK); 467 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 469 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 474 NUM_BANKS(ADDR_SURF_4_BANK); 475 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 477 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 481 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 482 NUM_BANKS(ADDR_SURF_2_BANK); 483 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 484 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 485 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 486 PIPE_CONFIG(ADDR_SURF_P4_8x16); 487 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 488 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 489 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 490 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 491 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 492 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 493 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 494 NUM_BANKS(ADDR_SURF_16_BANK); 495 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 497 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 502 NUM_BANKS(ADDR_SURF_16_BANK); 503 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 504 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 505 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 506 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 507 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 508 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 509 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 510 NUM_BANKS(ADDR_SURF_16_BANK); 511 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 512 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 513 PIPE_CONFIG(ADDR_SURF_P4_8x16); 514 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 515 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 516 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 517 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 519 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 520 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 521 NUM_BANKS(ADDR_SURF_16_BANK); 522 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 523 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 524 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 525 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 526 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 527 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 528 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 529 NUM_BANKS(ADDR_SURF_16_BANK); 530 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 531 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 532 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 533 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 537 NUM_BANKS(ADDR_SURF_16_BANK); 538 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 539 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 540 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 544 NUM_BANKS(ADDR_SURF_16_BANK) | 545 TILE_SPLIT(split_equal_to_row_size); 546 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 547 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 548 PIPE_CONFIG(ADDR_SURF_P4_8x16); 549 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 550 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 551 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 552 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 553 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 554 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 555 NUM_BANKS(ADDR_SURF_16_BANK) | 556 TILE_SPLIT(split_equal_to_row_size); 557 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 558 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 559 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 560 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 561 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 562 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 563 NUM_BANKS(ADDR_SURF_16_BANK) | 564 TILE_SPLIT(split_equal_to_row_size); 565 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 566 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 567 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 568 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 569 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 570 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 571 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 572 NUM_BANKS(ADDR_SURF_8_BANK); 573 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 574 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 575 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 576 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 577 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 580 NUM_BANKS(ADDR_SURF_8_BANK); 581 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 582 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 583 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 584 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 585 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 586 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 587 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 588 NUM_BANKS(ADDR_SURF_4_BANK); 589 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 590 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 591 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 592 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 594 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 595 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 596 NUM_BANKS(ADDR_SURF_4_BANK); 597 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 598 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 599 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 600 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 601 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 602 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 603 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 604 NUM_BANKS(ADDR_SURF_2_BANK); 605 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 606 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 607 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 608 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 609 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 610 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 611 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 612 NUM_BANKS(ADDR_SURF_2_BANK); 613 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 614 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 615 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 616 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 617 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 618 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 619 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 620 NUM_BANKS(ADDR_SURF_2_BANK); 621 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 622 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 623 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 624 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 625 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 626 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 627 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 628 NUM_BANKS(ADDR_SURF_2_BANK); 629 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 631 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 636 NUM_BANKS(ADDR_SURF_2_BANK); 637 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 638 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 639 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 640 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 642 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 644 NUM_BANKS(ADDR_SURF_2_BANK); 645 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 646 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 647 } else if (adev->asic_type == CHIP_OLAND) { 648 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 649 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 650 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 651 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 652 NUM_BANKS(ADDR_SURF_16_BANK) | 653 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 654 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 655 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 656 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 657 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 658 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 660 NUM_BANKS(ADDR_SURF_16_BANK) | 661 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 662 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 663 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 664 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 665 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 666 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 667 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 668 NUM_BANKS(ADDR_SURF_16_BANK) | 669 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 670 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 671 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 672 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 673 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 674 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 675 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 676 NUM_BANKS(ADDR_SURF_16_BANK) | 677 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 678 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 679 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 680 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 681 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 682 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 683 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 684 NUM_BANKS(ADDR_SURF_16_BANK) | 685 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 686 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 687 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 688 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 689 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 690 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 691 TILE_SPLIT(split_equal_to_row_size) | 692 NUM_BANKS(ADDR_SURF_16_BANK) | 693 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 694 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 695 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 696 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 697 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 698 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 699 TILE_SPLIT(split_equal_to_row_size) | 700 NUM_BANKS(ADDR_SURF_16_BANK) | 701 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 702 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 703 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 704 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 705 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 706 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 707 TILE_SPLIT(split_equal_to_row_size) | 708 NUM_BANKS(ADDR_SURF_16_BANK) | 709 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 710 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 711 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 712 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 713 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 714 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 715 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 716 NUM_BANKS(ADDR_SURF_16_BANK) | 717 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 718 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 719 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 720 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 721 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 722 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 723 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 724 NUM_BANKS(ADDR_SURF_16_BANK) | 725 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 726 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 727 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 728 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 729 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 730 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 731 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 732 NUM_BANKS(ADDR_SURF_16_BANK) | 733 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 734 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 735 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 736 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 737 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 738 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 739 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 740 NUM_BANKS(ADDR_SURF_16_BANK) | 741 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 742 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 743 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 744 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 745 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 746 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 747 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 748 NUM_BANKS(ADDR_SURF_16_BANK) | 749 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 750 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 751 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 752 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 753 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 754 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 755 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 756 NUM_BANKS(ADDR_SURF_16_BANK) | 757 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 758 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 759 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 760 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 761 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 762 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 763 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 764 NUM_BANKS(ADDR_SURF_16_BANK) | 765 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 766 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 767 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 768 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 769 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 770 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 771 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 772 NUM_BANKS(ADDR_SURF_16_BANK) | 773 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 774 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 775 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 776 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 777 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 778 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 779 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 780 NUM_BANKS(ADDR_SURF_16_BANK) | 781 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 782 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 783 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 784 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 785 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 786 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 787 TILE_SPLIT(split_equal_to_row_size) | 788 NUM_BANKS(ADDR_SURF_16_BANK) | 789 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 790 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 791 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 792 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 793 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 794 PIPE_CONFIG(ADDR_SURF_P4_8x16); 795 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 796 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 797 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 801 NUM_BANKS(ADDR_SURF_16_BANK) | 802 TILE_SPLIT(split_equal_to_row_size); 803 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 804 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 805 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 809 NUM_BANKS(ADDR_SURF_16_BANK) | 810 TILE_SPLIT(split_equal_to_row_size); 811 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 812 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 813 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 814 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 815 NUM_BANKS(ADDR_SURF_16_BANK) | 816 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 817 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 818 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 819 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 820 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 821 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 822 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 823 NUM_BANKS(ADDR_SURF_16_BANK) | 824 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 825 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 826 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); 827 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 828 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 829 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 830 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 831 NUM_BANKS(ADDR_SURF_16_BANK) | 832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 835 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 836 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 837 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 839 NUM_BANKS(ADDR_SURF_16_BANK) | 840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); 843 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 844 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 845 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 846 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 847 NUM_BANKS(ADDR_SURF_8_BANK) | 848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); 851 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 852 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 853 } else if (adev->asic_type == CHIP_HAINAN) { 854 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 855 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 856 PIPE_CONFIG(ADDR_SURF_P2) | 857 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 858 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 859 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 860 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 861 NUM_BANKS(ADDR_SURF_16_BANK); 862 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 863 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 864 PIPE_CONFIG(ADDR_SURF_P2) | 865 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 866 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 867 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 868 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 869 NUM_BANKS(ADDR_SURF_16_BANK); 870 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 871 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 872 PIPE_CONFIG(ADDR_SURF_P2) | 873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 877 NUM_BANKS(ADDR_SURF_16_BANK); 878 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 879 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 880 PIPE_CONFIG(ADDR_SURF_P2) | 881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 884 NUM_BANKS(ADDR_SURF_8_BANK) | 885 TILE_SPLIT(split_equal_to_row_size); 886 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 887 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 888 PIPE_CONFIG(ADDR_SURF_P2); 889 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 890 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 891 PIPE_CONFIG(ADDR_SURF_P2) | 892 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 893 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 894 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 895 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 896 NUM_BANKS(ADDR_SURF_8_BANK); 897 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 898 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 899 PIPE_CONFIG(ADDR_SURF_P2) | 900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 904 NUM_BANKS(ADDR_SURF_8_BANK); 905 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 906 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 907 PIPE_CONFIG(ADDR_SURF_P2) | 908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 909 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 910 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 911 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 912 NUM_BANKS(ADDR_SURF_4_BANK); 913 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 914 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 915 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 916 PIPE_CONFIG(ADDR_SURF_P2); 917 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 918 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 919 PIPE_CONFIG(ADDR_SURF_P2) | 920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 921 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 922 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 923 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | 924 NUM_BANKS(ADDR_SURF_16_BANK); 925 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 926 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 927 PIPE_CONFIG(ADDR_SURF_P2) | 928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 932 NUM_BANKS(ADDR_SURF_16_BANK); 933 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 934 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 935 PIPE_CONFIG(ADDR_SURF_P2) | 936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 937 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 938 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 939 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 940 NUM_BANKS(ADDR_SURF_16_BANK); 941 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 942 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 943 PIPE_CONFIG(ADDR_SURF_P2); 944 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 945 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 946 PIPE_CONFIG(ADDR_SURF_P2) | 947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 948 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 949 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 950 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 951 NUM_BANKS(ADDR_SURF_16_BANK); 952 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 953 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 954 PIPE_CONFIG(ADDR_SURF_P2) | 955 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 959 NUM_BANKS(ADDR_SURF_16_BANK); 960 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 961 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 962 PIPE_CONFIG(ADDR_SURF_P2) | 963 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 967 NUM_BANKS(ADDR_SURF_16_BANK); 968 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 969 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 970 PIPE_CONFIG(ADDR_SURF_P2) | 971 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 974 NUM_BANKS(ADDR_SURF_16_BANK) | 975 TILE_SPLIT(split_equal_to_row_size); 976 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 977 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 978 PIPE_CONFIG(ADDR_SURF_P2); 979 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 980 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 981 PIPE_CONFIG(ADDR_SURF_P2) | 982 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 983 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 984 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 985 NUM_BANKS(ADDR_SURF_16_BANK) | 986 TILE_SPLIT(split_equal_to_row_size); 987 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 988 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 989 PIPE_CONFIG(ADDR_SURF_P2) | 990 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 991 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 992 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 993 NUM_BANKS(ADDR_SURF_16_BANK) | 994 TILE_SPLIT(split_equal_to_row_size); 995 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 996 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 997 PIPE_CONFIG(ADDR_SURF_P2) | 998 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 999 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1002 NUM_BANKS(ADDR_SURF_8_BANK); 1003 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1004 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1005 PIPE_CONFIG(ADDR_SURF_P2) | 1006 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1007 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1008 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1009 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1010 NUM_BANKS(ADDR_SURF_8_BANK); 1011 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1012 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1013 PIPE_CONFIG(ADDR_SURF_P2) | 1014 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1015 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1016 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1017 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1018 NUM_BANKS(ADDR_SURF_8_BANK); 1019 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1020 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1021 PIPE_CONFIG(ADDR_SURF_P2) | 1022 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1023 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1024 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1025 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1026 NUM_BANKS(ADDR_SURF_8_BANK); 1027 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1028 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1029 PIPE_CONFIG(ADDR_SURF_P2) | 1030 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1031 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1032 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1033 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1034 NUM_BANKS(ADDR_SURF_4_BANK); 1035 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1036 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1037 PIPE_CONFIG(ADDR_SURF_P2) | 1038 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1039 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1042 NUM_BANKS(ADDR_SURF_4_BANK); 1043 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1044 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1045 PIPE_CONFIG(ADDR_SURF_P2) | 1046 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1047 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1048 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1049 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1050 NUM_BANKS(ADDR_SURF_4_BANK); 1051 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1052 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1053 PIPE_CONFIG(ADDR_SURF_P2) | 1054 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1055 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1056 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1057 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1058 NUM_BANKS(ADDR_SURF_4_BANK); 1059 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1060 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1061 PIPE_CONFIG(ADDR_SURF_P2) | 1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1063 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1066 NUM_BANKS(ADDR_SURF_4_BANK); 1067 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1068 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1069 PIPE_CONFIG(ADDR_SURF_P2) | 1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1071 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1074 NUM_BANKS(ADDR_SURF_4_BANK); 1075 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1076 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1077 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) { 1078 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1079 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1080 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1081 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1082 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1083 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1084 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1085 NUM_BANKS(ADDR_SURF_16_BANK); 1086 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1087 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1088 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1089 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1090 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1091 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1092 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1093 NUM_BANKS(ADDR_SURF_16_BANK); 1094 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1101 NUM_BANKS(ADDR_SURF_16_BANK); 1102 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1103 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1104 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1108 NUM_BANKS(ADDR_SURF_4_BANK) | 1109 TILE_SPLIT(split_equal_to_row_size); 1110 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1111 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1112 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1113 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1114 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1115 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1117 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1120 NUM_BANKS(ADDR_SURF_2_BANK); 1121 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1128 NUM_BANKS(ADDR_SURF_2_BANK); 1129 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1130 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1131 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1136 NUM_BANKS(ADDR_SURF_2_BANK); 1137 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); 1138 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1139 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1140 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1141 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1142 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1143 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1144 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1145 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1146 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1147 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1148 NUM_BANKS(ADDR_SURF_16_BANK); 1149 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1153 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | 1156 NUM_BANKS(ADDR_SURF_16_BANK); 1157 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1158 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1164 NUM_BANKS(ADDR_SURF_16_BANK); 1165 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1166 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1168 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1169 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1170 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1171 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1172 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1175 NUM_BANKS(ADDR_SURF_16_BANK); 1176 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1177 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1178 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1179 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1183 NUM_BANKS(ADDR_SURF_16_BANK); 1184 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1185 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1187 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1191 NUM_BANKS(ADDR_SURF_16_BANK); 1192 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1193 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1195 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1198 NUM_BANKS(ADDR_SURF_16_BANK) | 1199 TILE_SPLIT(split_equal_to_row_size); 1200 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1201 ARRAY_MODE(ARRAY_1D_TILED_THICK) | 1202 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16); 1203 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1204 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | 1205 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1206 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1207 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1208 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1209 NUM_BANKS(ADDR_SURF_16_BANK) | 1210 TILE_SPLIT(split_equal_to_row_size); 1211 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1212 ARRAY_MODE(ARRAY_2D_TILED_THICK) | 1213 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1214 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1215 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1216 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1217 NUM_BANKS(ADDR_SURF_16_BANK) | 1218 TILE_SPLIT(split_equal_to_row_size); 1219 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1220 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1221 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1222 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1223 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1224 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1225 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1226 NUM_BANKS(ADDR_SURF_4_BANK); 1227 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1228 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1229 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1230 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1231 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1234 NUM_BANKS(ADDR_SURF_4_BANK); 1235 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1236 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1237 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1238 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1239 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1240 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | 1241 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1242 NUM_BANKS(ADDR_SURF_2_BANK); 1243 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1244 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1245 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1247 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1248 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1249 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1250 NUM_BANKS(ADDR_SURF_2_BANK); 1251 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1252 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1253 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1254 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1255 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1256 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1257 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1258 NUM_BANKS(ADDR_SURF_2_BANK); 1259 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1260 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1261 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1262 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1263 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1264 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1265 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1266 NUM_BANKS(ADDR_SURF_2_BANK); 1267 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1268 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1269 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1270 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1271 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1274 NUM_BANKS(ADDR_SURF_2_BANK); 1275 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1276 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1277 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1278 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1279 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1280 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1281 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1282 NUM_BANKS(ADDR_SURF_2_BANK); 1283 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1284 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1285 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1287 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1288 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1289 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1290 NUM_BANKS(ADDR_SURF_2_BANK); 1291 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1292 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1293 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1294 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | 1295 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1296 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1297 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) | 1298 NUM_BANKS(ADDR_SURF_2_BANK); 1299 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) 1300 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); 1301 } else { 1302 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1303 } 1304 } 1305 1306 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1307 u32 sh_num, u32 instance) 1308 { 1309 u32 data; 1310 1311 if (instance == 0xffffffff) 1312 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1313 else 1314 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1315 1316 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1317 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1318 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 1319 else if (se_num == 0xffffffff) 1320 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK | 1321 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); 1322 else if (sh_num == 0xffffffff) 1323 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 1324 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1325 else 1326 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | 1327 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1328 WREG32(mmGRBM_GFX_INDEX, data); 1329 } 1330 1331 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1332 { 1333 u32 data, mask; 1334 1335 data = RREG32(mmCC_RB_BACKEND_DISABLE) | 1336 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1337 1338 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE); 1339 1340 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/ 1341 adev->gfx.config.max_sh_per_se); 1342 1343 return ~data & mask; 1344 } 1345 1346 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf) 1347 { 1348 switch (adev->asic_type) { 1349 case CHIP_TAHITI: 1350 case CHIP_PITCAIRN: 1351 *rconf |= 1352 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) | 1353 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1354 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1355 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) | 1356 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) | 1357 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) | 1358 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT); 1359 break; 1360 case CHIP_VERDE: 1361 *rconf |= 1362 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) | 1363 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) | 1364 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT); 1365 break; 1366 case CHIP_OLAND: 1367 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT); 1368 break; 1369 case CHIP_HAINAN: 1370 *rconf |= 0x0; 1371 break; 1372 default: 1373 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type); 1374 break; 1375 } 1376 } 1377 1378 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev, 1379 u32 raster_config, unsigned rb_mask, 1380 unsigned num_rb) 1381 { 1382 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); 1383 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1); 1384 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2); 1385 unsigned rb_per_se = num_rb / num_se; 1386 unsigned se_mask[4]; 1387 unsigned se; 1388 1389 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 1390 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 1391 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 1392 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 1393 1394 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4)); 1395 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2)); 1396 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2)); 1397 1398 for (se = 0; se < num_se; se++) { 1399 unsigned raster_config_se = raster_config; 1400 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 1401 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 1402 int idx = (se / 2) * 2; 1403 1404 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK; 1406 1407 if (!se_mask[idx]) 1408 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1409 else 1410 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT; 1411 } 1412 1413 pkr0_mask &= rb_mask; 1414 pkr1_mask &= rb_mask; 1415 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 1416 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK; 1417 1418 if (!pkr0_mask) 1419 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1420 else 1421 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT; 1422 } 1423 1424 if (rb_per_se >= 2) { 1425 unsigned rb0_mask = 1 << (se * rb_per_se); 1426 unsigned rb1_mask = rb0_mask << 1; 1427 1428 rb0_mask &= rb_mask; 1429 rb1_mask &= rb_mask; 1430 if (!rb0_mask || !rb1_mask) { 1431 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK; 1432 1433 if (!rb0_mask) 1434 raster_config_se |= 1435 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1436 else 1437 raster_config_se |= 1438 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT; 1439 } 1440 1441 if (rb_per_se > 2) { 1442 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 1443 rb1_mask = rb0_mask << 1; 1444 rb0_mask &= rb_mask; 1445 rb1_mask &= rb_mask; 1446 if (!rb0_mask || !rb1_mask) { 1447 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK; 1448 1449 if (!rb0_mask) 1450 raster_config_se |= 1451 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1452 else 1453 raster_config_se |= 1454 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT; 1455 } 1456 } 1457 } 1458 1459 /* GRBM_GFX_INDEX has a different offset on SI */ 1460 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1461 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1462 } 1463 1464 /* GRBM_GFX_INDEX has a different offset on SI */ 1465 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1466 } 1467 1468 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) 1469 { 1470 int i, j; 1471 u32 data; 1472 u32 raster_config = 0; 1473 u32 active_rbs = 0; 1474 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1475 adev->gfx.config.max_sh_per_se; 1476 unsigned num_rb_pipes; 1477 1478 mutex_lock(&adev->grbm_idx_mutex); 1479 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1480 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1481 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1482 data = gfx_v6_0_get_rb_active_bitmap(adev); 1483 active_rbs |= data << 1484 ((i * adev->gfx.config.max_sh_per_se + j) * 1485 rb_bitmap_width_per_sh); 1486 } 1487 } 1488 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1489 1490 adev->gfx.config.backend_enable_mask = active_rbs; 1491 adev->gfx.config.num_rbs = hweight32(active_rbs); 1492 1493 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se * 1494 adev->gfx.config.max_shader_engines, 16); 1495 1496 gfx_v6_0_raster_config(adev, &raster_config); 1497 1498 if (!adev->gfx.config.backend_enable_mask || 1499 adev->gfx.config.num_rbs >= num_rb_pipes) 1500 WREG32(mmPA_SC_RASTER_CONFIG, raster_config); 1501 else 1502 gfx_v6_0_write_harvested_raster_configs(adev, raster_config, 1503 adev->gfx.config.backend_enable_mask, 1504 num_rb_pipes); 1505 1506 /* cache the values for userspace */ 1507 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1508 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1509 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1510 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1511 RREG32(mmCC_RB_BACKEND_DISABLE); 1512 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = 1513 RREG32(mmGC_USER_RB_BACKEND_DISABLE); 1514 adev->gfx.config.rb_config[i][j].raster_config = 1515 RREG32(mmPA_SC_RASTER_CONFIG); 1516 } 1517 } 1518 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1519 mutex_unlock(&adev->grbm_idx_mutex); 1520 } 1521 1522 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 1523 u32 bitmap) 1524 { 1525 u32 data; 1526 1527 if (!bitmap) 1528 return; 1529 1530 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 1531 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 1532 1533 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data); 1534 } 1535 1536 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 1537 { 1538 u32 data, mask; 1539 1540 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) | 1541 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG); 1542 1543 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 1544 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask; 1545 } 1546 1547 1548 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev) 1549 { 1550 int i, j, k; 1551 u32 data, mask; 1552 u32 active_cu = 0; 1553 1554 mutex_lock(&adev->grbm_idx_mutex); 1555 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1556 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1557 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1558 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1559 active_cu = gfx_v6_0_get_cu_enabled(adev); 1560 1561 mask = 1; 1562 for (k = 0; k < 16; k++) { 1563 mask <<= k; 1564 if (active_cu & mask) { 1565 data &= ~mask; 1566 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data); 1567 break; 1568 } 1569 } 1570 } 1571 } 1572 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1573 mutex_unlock(&adev->grbm_idx_mutex); 1574 } 1575 1576 static void gfx_v6_0_config_init(struct amdgpu_device *adev) 1577 { 1578 adev->gfx.config.double_offchip_lds_buf = 0; 1579 } 1580 1581 static void gfx_v6_0_constants_init(struct amdgpu_device *adev) 1582 { 1583 u32 gb_addr_config = 0; 1584 u32 mc_arb_ramcfg; 1585 u32 sx_debug_1; 1586 u32 hdp_host_path_cntl; 1587 u32 tmp; 1588 1589 switch (adev->asic_type) { 1590 case CHIP_TAHITI: 1591 adev->gfx.config.max_shader_engines = 2; 1592 adev->gfx.config.max_tile_pipes = 12; 1593 adev->gfx.config.max_cu_per_sh = 8; 1594 adev->gfx.config.max_sh_per_se = 2; 1595 adev->gfx.config.max_backends_per_se = 4; 1596 adev->gfx.config.max_texture_channel_caches = 12; 1597 adev->gfx.config.max_gprs = 256; 1598 adev->gfx.config.max_gs_threads = 32; 1599 adev->gfx.config.max_hw_contexts = 8; 1600 1601 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1602 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1603 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1604 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1605 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1606 break; 1607 case CHIP_PITCAIRN: 1608 adev->gfx.config.max_shader_engines = 2; 1609 adev->gfx.config.max_tile_pipes = 8; 1610 adev->gfx.config.max_cu_per_sh = 5; 1611 adev->gfx.config.max_sh_per_se = 2; 1612 adev->gfx.config.max_backends_per_se = 4; 1613 adev->gfx.config.max_texture_channel_caches = 8; 1614 adev->gfx.config.max_gprs = 256; 1615 adev->gfx.config.max_gs_threads = 32; 1616 adev->gfx.config.max_hw_contexts = 8; 1617 1618 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1619 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1620 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1621 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1622 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1623 break; 1624 case CHIP_VERDE: 1625 adev->gfx.config.max_shader_engines = 1; 1626 adev->gfx.config.max_tile_pipes = 4; 1627 adev->gfx.config.max_cu_per_sh = 5; 1628 adev->gfx.config.max_sh_per_se = 2; 1629 adev->gfx.config.max_backends_per_se = 4; 1630 adev->gfx.config.max_texture_channel_caches = 4; 1631 adev->gfx.config.max_gprs = 256; 1632 adev->gfx.config.max_gs_threads = 32; 1633 adev->gfx.config.max_hw_contexts = 8; 1634 1635 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1636 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1637 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1638 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1639 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1640 break; 1641 case CHIP_OLAND: 1642 adev->gfx.config.max_shader_engines = 1; 1643 adev->gfx.config.max_tile_pipes = 4; 1644 adev->gfx.config.max_cu_per_sh = 6; 1645 adev->gfx.config.max_sh_per_se = 1; 1646 adev->gfx.config.max_backends_per_se = 2; 1647 adev->gfx.config.max_texture_channel_caches = 4; 1648 adev->gfx.config.max_gprs = 256; 1649 adev->gfx.config.max_gs_threads = 16; 1650 adev->gfx.config.max_hw_contexts = 8; 1651 1652 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1653 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1654 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1655 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1656 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1657 break; 1658 case CHIP_HAINAN: 1659 adev->gfx.config.max_shader_engines = 1; 1660 adev->gfx.config.max_tile_pipes = 4; 1661 adev->gfx.config.max_cu_per_sh = 5; 1662 adev->gfx.config.max_sh_per_se = 1; 1663 adev->gfx.config.max_backends_per_se = 1; 1664 adev->gfx.config.max_texture_channel_caches = 2; 1665 adev->gfx.config.max_gprs = 256; 1666 adev->gfx.config.max_gs_threads = 16; 1667 adev->gfx.config.max_hw_contexts = 8; 1668 1669 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1670 adev->gfx.config.sc_prim_fifo_size_backend = 0x40; 1671 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1672 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; 1673 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; 1674 break; 1675 default: 1676 BUG(); 1677 break; 1678 } 1679 1680 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT)); 1681 WREG32(mmSRBM_INT_CNTL, 1); 1682 WREG32(mmSRBM_INT_ACK, 1); 1683 1684 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 1685 1686 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); 1687 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; 1688 1689 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 1690 adev->gfx.config.mem_max_burst_length_bytes = 256; 1691 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT; 1692 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1693 if (adev->gfx.config.mem_row_size_in_kb > 4) 1694 adev->gfx.config.mem_row_size_in_kb = 4; 1695 adev->gfx.config.shader_engine_tile_size = 32; 1696 adev->gfx.config.num_gpus = 1; 1697 adev->gfx.config.multi_gpu_tile_size = 64; 1698 1699 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; 1700 switch (adev->gfx.config.mem_row_size_in_kb) { 1701 case 1: 1702 default: 1703 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1704 break; 1705 case 2: 1706 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1707 break; 1708 case 4: 1709 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; 1710 break; 1711 } 1712 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK; 1713 if (adev->gfx.config.max_shader_engines == 2) 1714 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT; 1715 adev->gfx.config.gb_addr_config = gb_addr_config; 1716 1717 WREG32(mmGB_ADDR_CONFIG, gb_addr_config); 1718 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config); 1719 WREG32(mmDMIF_ADDR_CALC, gb_addr_config); 1720 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); 1721 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1722 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1723 1724 #if 0 1725 if (adev->has_uvd) { 1726 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); 1727 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); 1728 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); 1729 } 1730 #endif 1731 gfx_v6_0_tiling_mode_table_init(adev); 1732 1733 gfx_v6_0_setup_rb(adev); 1734 1735 gfx_v6_0_setup_spi(adev); 1736 1737 gfx_v6_0_get_cu_info(adev); 1738 gfx_v6_0_config_init(adev); 1739 1740 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | 1741 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); 1742 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) | 1743 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT)); 1744 1745 sx_debug_1 = RREG32(mmSX_DEBUG_1); 1746 WREG32(mmSX_DEBUG_1, sx_debug_1); 1747 1748 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); 1749 1750 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | 1751 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | 1752 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | 1753 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); 1754 1755 WREG32(mmVGT_NUM_INSTANCES, 1); 1756 WREG32(mmCP_PERFMON_CNTL, 0); 1757 WREG32(mmSQ_CONFIG, 0); 1758 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) | 1759 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT))); 1760 1761 WREG32(mmVGT_CACHE_INVALIDATION, 1762 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) | 1763 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT)); 1764 1765 WREG32(mmVGT_GS_VERTEX_REUSE, 16); 1766 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0); 1767 1768 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0); 1769 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0); 1770 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0); 1771 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0); 1772 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0); 1773 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0); 1774 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0); 1775 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0); 1776 1777 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL); 1778 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1779 1780 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK | 1781 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT)); 1782 1783 udelay(50); 1784 } 1785 1786 1787 static void gfx_v6_0_scratch_init(struct amdgpu_device *adev) 1788 { 1789 adev->gfx.scratch.num_reg = 8; 1790 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; 1791 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1792 } 1793 1794 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) 1795 { 1796 struct amdgpu_device *adev = ring->adev; 1797 uint32_t scratch; 1798 uint32_t tmp = 0; 1799 unsigned i; 1800 int r; 1801 1802 r = amdgpu_gfx_scratch_get(adev, &scratch); 1803 if (r) 1804 return r; 1805 1806 WREG32(scratch, 0xCAFEDEAD); 1807 1808 r = amdgpu_ring_alloc(ring, 3); 1809 if (r) 1810 goto error_free_scratch; 1811 1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1813 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START)); 1814 amdgpu_ring_write(ring, 0xDEADBEEF); 1815 amdgpu_ring_commit(ring); 1816 1817 for (i = 0; i < adev->usec_timeout; i++) { 1818 tmp = RREG32(scratch); 1819 if (tmp == 0xDEADBEEF) 1820 break; 1821 udelay(1); 1822 } 1823 1824 if (i >= adev->usec_timeout) 1825 r = -ETIMEDOUT; 1826 1827 error_free_scratch: 1828 amdgpu_gfx_scratch_free(adev, scratch); 1829 return r; 1830 } 1831 1832 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) 1833 { 1834 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 1835 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | 1836 EVENT_INDEX(0)); 1837 } 1838 1839 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1840 u64 seq, unsigned flags) 1841 { 1842 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 1843 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 1844 /* flush read cache over gart */ 1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1846 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)); 1847 amdgpu_ring_write(ring, 0); 1848 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1849 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1850 PACKET3_TC_ACTION_ENA | 1851 PACKET3_SH_KCACHE_ACTION_ENA | 1852 PACKET3_SH_ICACHE_ACTION_ENA); 1853 amdgpu_ring_write(ring, 0xFFFFFFFF); 1854 amdgpu_ring_write(ring, 0); 1855 amdgpu_ring_write(ring, 10); /* poll interval */ 1856 /* EVENT_WRITE_EOP - flush caches, send int */ 1857 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1858 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1859 amdgpu_ring_write(ring, addr & 0xfffffffc); 1860 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | 1861 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) | 1862 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT)); 1863 amdgpu_ring_write(ring, lower_32_bits(seq)); 1864 amdgpu_ring_write(ring, upper_32_bits(seq)); 1865 } 1866 1867 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring, 1868 struct amdgpu_job *job, 1869 struct amdgpu_ib *ib, 1870 uint32_t flags) 1871 { 1872 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1873 u32 header, control = 0; 1874 1875 /* insert SWITCH_BUFFER packet before first IB in the ring frame */ 1876 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 1877 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1878 amdgpu_ring_write(ring, 0); 1879 } 1880 1881 if (ib->flags & AMDGPU_IB_FLAG_CE) 1882 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1883 else 1884 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1885 1886 control |= ib->length_dw | (vmid << 24); 1887 1888 amdgpu_ring_write(ring, header); 1889 amdgpu_ring_write(ring, 1890 #ifdef __BIG_ENDIAN 1891 (2 << 0) | 1892 #endif 1893 (ib->gpu_addr & 0xFFFFFFFC)); 1894 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1895 amdgpu_ring_write(ring, control); 1896 } 1897 1898 /** 1899 * gfx_v6_0_ring_test_ib - basic ring IB test 1900 * 1901 * @ring: amdgpu_ring structure holding ring information 1902 * 1903 * Allocate an IB and execute it on the gfx ring (SI). 1904 * Provides a basic gfx ring test to verify that IBs are working. 1905 * Returns 0 on success, error on failure. 1906 */ 1907 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1908 { 1909 struct amdgpu_device *adev = ring->adev; 1910 struct amdgpu_ib ib; 1911 struct dma_fence *f = NULL; 1912 uint32_t scratch; 1913 uint32_t tmp = 0; 1914 long r; 1915 1916 r = amdgpu_gfx_scratch_get(adev, &scratch); 1917 if (r) 1918 return r; 1919 1920 WREG32(scratch, 0xCAFEDEAD); 1921 memset(&ib, 0, sizeof(ib)); 1922 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1923 if (r) 1924 goto err1; 1925 1926 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 1927 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START)); 1928 ib.ptr[2] = 0xDEADBEEF; 1929 ib.length_dw = 3; 1930 1931 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1932 if (r) 1933 goto err2; 1934 1935 r = dma_fence_wait_timeout(f, false, timeout); 1936 if (r == 0) { 1937 r = -ETIMEDOUT; 1938 goto err2; 1939 } else if (r < 0) { 1940 goto err2; 1941 } 1942 tmp = RREG32(scratch); 1943 if (tmp == 0xDEADBEEF) 1944 r = 0; 1945 else 1946 r = -EINVAL; 1947 1948 err2: 1949 amdgpu_ib_free(adev, &ib, NULL); 1950 dma_fence_put(f); 1951 err1: 1952 amdgpu_gfx_scratch_free(adev, scratch); 1953 return r; 1954 } 1955 1956 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 1957 { 1958 int i; 1959 if (enable) { 1960 WREG32(mmCP_ME_CNTL, 0); 1961 } else { 1962 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | 1963 CP_ME_CNTL__PFP_HALT_MASK | 1964 CP_ME_CNTL__CE_HALT_MASK)); 1965 WREG32(mmSCRATCH_UMSK, 0); 1966 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1967 adev->gfx.gfx_ring[i].sched.ready = false; 1968 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1969 adev->gfx.compute_ring[i].sched.ready = false; 1970 } 1971 udelay(50); 1972 } 1973 1974 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 1975 { 1976 unsigned i; 1977 const struct gfx_firmware_header_v1_0 *pfp_hdr; 1978 const struct gfx_firmware_header_v1_0 *ce_hdr; 1979 const struct gfx_firmware_header_v1_0 *me_hdr; 1980 const __le32 *fw_data; 1981 u32 fw_size; 1982 1983 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 1984 return -EINVAL; 1985 1986 gfx_v6_0_cp_gfx_enable(adev, false); 1987 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1988 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1989 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1990 1991 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 1992 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 1993 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 1994 1995 /* PFP */ 1996 fw_data = (const __le32 *) 1997 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 1998 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 1999 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2000 for (i = 0; i < fw_size; i++) 2001 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2002 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2003 2004 /* CE */ 2005 fw_data = (const __le32 *) 2006 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2007 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2008 WREG32(mmCP_CE_UCODE_ADDR, 0); 2009 for (i = 0; i < fw_size; i++) 2010 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2011 WREG32(mmCP_CE_UCODE_ADDR, 0); 2012 2013 /* ME */ 2014 fw_data = (const __be32 *) 2015 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2016 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2017 WREG32(mmCP_ME_RAM_WADDR, 0); 2018 for (i = 0; i < fw_size; i++) 2019 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2020 WREG32(mmCP_ME_RAM_WADDR, 0); 2021 2022 WREG32(mmCP_PFP_UCODE_ADDR, 0); 2023 WREG32(mmCP_CE_UCODE_ADDR, 0); 2024 WREG32(mmCP_ME_RAM_WADDR, 0); 2025 WREG32(mmCP_ME_RAM_RADDR, 0); 2026 return 0; 2027 } 2028 2029 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) 2030 { 2031 const struct cs_section_def *sect = NULL; 2032 const struct cs_extent_def *ext = NULL; 2033 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2034 int r, i; 2035 2036 r = amdgpu_ring_alloc(ring, 7 + 4); 2037 if (r) { 2038 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2039 return r; 2040 } 2041 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2042 amdgpu_ring_write(ring, 0x1); 2043 amdgpu_ring_write(ring, 0x0); 2044 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1); 2045 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2046 amdgpu_ring_write(ring, 0); 2047 amdgpu_ring_write(ring, 0); 2048 2049 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2050 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2051 amdgpu_ring_write(ring, 0xc000); 2052 amdgpu_ring_write(ring, 0xe000); 2053 amdgpu_ring_commit(ring); 2054 2055 gfx_v6_0_cp_gfx_enable(adev, true); 2056 2057 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); 2058 if (r) { 2059 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2060 return r; 2061 } 2062 2063 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2064 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2065 2066 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2067 for (ext = sect->section; ext->extent != NULL; ++ext) { 2068 if (sect->id == SECT_CONTEXT) { 2069 amdgpu_ring_write(ring, 2070 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2071 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2072 for (i = 0; i < ext->reg_count; i++) 2073 amdgpu_ring_write(ring, ext->extent[i]); 2074 } 2075 } 2076 } 2077 2078 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2079 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2080 2081 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2082 amdgpu_ring_write(ring, 0); 2083 2084 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 2085 amdgpu_ring_write(ring, 0x00000316); 2086 amdgpu_ring_write(ring, 0x0000000e); 2087 amdgpu_ring_write(ring, 0x00000010); 2088 2089 amdgpu_ring_commit(ring); 2090 2091 return 0; 2092 } 2093 2094 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) 2095 { 2096 struct amdgpu_ring *ring; 2097 u32 tmp; 2098 u32 rb_bufsz; 2099 int r; 2100 u64 rptr_addr; 2101 2102 WREG32(mmCP_SEM_WAIT_TIMER, 0x0); 2103 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2104 2105 /* Set the write pointer delay */ 2106 WREG32(mmCP_RB_WPTR_DELAY, 0); 2107 2108 WREG32(mmCP_DEBUG, 0); 2109 WREG32(mmSCRATCH_ADDR, 0); 2110 2111 /* ring 0 - compute and gfx */ 2112 /* Set ring buffer size */ 2113 ring = &adev->gfx.gfx_ring[0]; 2114 rb_bufsz = order_base_2(ring->ring_size / 8); 2115 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2116 2117 #ifdef __BIG_ENDIAN 2118 tmp |= BUF_SWAP_32BIT; 2119 #endif 2120 WREG32(mmCP_RB0_CNTL, tmp); 2121 2122 /* Initialize the ring buffer's read and write pointers */ 2123 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); 2124 ring->wptr = 0; 2125 WREG32(mmCP_RB0_WPTR, ring->wptr); 2126 2127 /* set the wb address whether it's enabled or not */ 2128 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2129 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2130 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2131 2132 WREG32(mmSCRATCH_UMSK, 0); 2133 2134 mdelay(1); 2135 WREG32(mmCP_RB0_CNTL, tmp); 2136 2137 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8); 2138 2139 /* start the rings */ 2140 gfx_v6_0_cp_gfx_start(adev); 2141 r = amdgpu_ring_test_helper(ring); 2142 if (r) 2143 return r; 2144 2145 return 0; 2146 } 2147 2148 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring) 2149 { 2150 return ring->adev->wb.wb[ring->rptr_offs]; 2151 } 2152 2153 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring) 2154 { 2155 struct amdgpu_device *adev = ring->adev; 2156 2157 if (ring == &adev->gfx.gfx_ring[0]) 2158 return RREG32(mmCP_RB0_WPTR); 2159 else if (ring == &adev->gfx.compute_ring[0]) 2160 return RREG32(mmCP_RB1_WPTR); 2161 else if (ring == &adev->gfx.compute_ring[1]) 2162 return RREG32(mmCP_RB2_WPTR); 2163 else 2164 BUG(); 2165 } 2166 2167 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 2168 { 2169 struct amdgpu_device *adev = ring->adev; 2170 2171 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2172 (void)RREG32(mmCP_RB0_WPTR); 2173 } 2174 2175 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 2176 { 2177 struct amdgpu_device *adev = ring->adev; 2178 2179 if (ring == &adev->gfx.compute_ring[0]) { 2180 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2181 (void)RREG32(mmCP_RB1_WPTR); 2182 } else if (ring == &adev->gfx.compute_ring[1]) { 2183 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); 2184 (void)RREG32(mmCP_RB2_WPTR); 2185 } else { 2186 BUG(); 2187 } 2188 2189 } 2190 2191 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev) 2192 { 2193 struct amdgpu_ring *ring; 2194 u32 tmp; 2195 u32 rb_bufsz; 2196 int i, r; 2197 u64 rptr_addr; 2198 2199 /* ring1 - compute only */ 2200 /* Set ring buffer size */ 2201 2202 ring = &adev->gfx.compute_ring[0]; 2203 rb_bufsz = order_base_2(ring->ring_size / 8); 2204 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2205 #ifdef __BIG_ENDIAN 2206 tmp |= BUF_SWAP_32BIT; 2207 #endif 2208 WREG32(mmCP_RB1_CNTL, tmp); 2209 2210 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); 2211 ring->wptr = 0; 2212 WREG32(mmCP_RB1_WPTR, ring->wptr); 2213 2214 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2215 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2216 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2217 2218 mdelay(1); 2219 WREG32(mmCP_RB1_CNTL, tmp); 2220 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8); 2221 2222 ring = &adev->gfx.compute_ring[1]; 2223 rb_bufsz = order_base_2(ring->ring_size / 8); 2224 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2225 #ifdef __BIG_ENDIAN 2226 tmp |= BUF_SWAP_32BIT; 2227 #endif 2228 WREG32(mmCP_RB2_CNTL, tmp); 2229 2230 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); 2231 ring->wptr = 0; 2232 WREG32(mmCP_RB2_WPTR, ring->wptr); 2233 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2234 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); 2235 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); 2236 2237 mdelay(1); 2238 WREG32(mmCP_RB2_CNTL, tmp); 2239 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8); 2240 2241 2242 for (i = 0; i < 2; i++) { 2243 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]); 2244 if (r) 2245 return r; 2246 } 2247 2248 return 0; 2249 } 2250 2251 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable) 2252 { 2253 gfx_v6_0_cp_gfx_enable(adev, enable); 2254 } 2255 2256 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev) 2257 { 2258 return gfx_v6_0_cp_gfx_load_microcode(adev); 2259 } 2260 2261 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2262 bool enable) 2263 { 2264 u32 tmp = RREG32(mmCP_INT_CNTL_RING0); 2265 u32 mask; 2266 int i; 2267 2268 if (enable) 2269 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2270 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2271 else 2272 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK | 2273 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK); 2274 WREG32(mmCP_INT_CNTL_RING0, tmp); 2275 2276 if (!enable) { 2277 /* read a gfx register */ 2278 tmp = RREG32(mmDB_DEPTH_INFO); 2279 2280 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS; 2281 for (i = 0; i < adev->usec_timeout; i++) { 2282 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS)) 2283 break; 2284 udelay(1); 2285 } 2286 } 2287 } 2288 2289 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) 2290 { 2291 int r; 2292 2293 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2294 2295 r = gfx_v6_0_cp_load_microcode(adev); 2296 if (r) 2297 return r; 2298 2299 r = gfx_v6_0_cp_gfx_resume(adev); 2300 if (r) 2301 return r; 2302 r = gfx_v6_0_cp_compute_resume(adev); 2303 if (r) 2304 return r; 2305 2306 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2307 2308 return 0; 2309 } 2310 2311 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2312 { 2313 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2314 uint32_t seq = ring->fence_drv.sync_seq; 2315 uint64_t addr = ring->fence_drv.gpu_addr; 2316 2317 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2318 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 2319 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 2320 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */ 2321 amdgpu_ring_write(ring, addr & 0xfffffffc); 2322 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 2323 amdgpu_ring_write(ring, seq); 2324 amdgpu_ring_write(ring, 0xffffffff); 2325 amdgpu_ring_write(ring, 4); /* poll interval */ 2326 2327 if (usepfp) { 2328 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2329 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2330 amdgpu_ring_write(ring, 0); 2331 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2332 amdgpu_ring_write(ring, 0); 2333 } 2334 } 2335 2336 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 2337 unsigned vmid, uint64_t pd_addr) 2338 { 2339 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2340 2341 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2342 2343 /* wait for the invalidate to complete */ 2344 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 2345 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ 2346 WAIT_REG_MEM_ENGINE(0))); /* me */ 2347 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 2348 amdgpu_ring_write(ring, 0); 2349 amdgpu_ring_write(ring, 0); /* ref */ 2350 amdgpu_ring_write(ring, 0); /* mask */ 2351 amdgpu_ring_write(ring, 0x20); /* poll interval */ 2352 2353 if (usepfp) { 2354 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 2355 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 2356 amdgpu_ring_write(ring, 0x0); 2357 2358 /* synce CE with ME to prevent CE fetch CEIB before context switch done */ 2359 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2360 amdgpu_ring_write(ring, 0); 2361 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 2362 amdgpu_ring_write(ring, 0); 2363 } 2364 } 2365 2366 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, 2367 uint32_t reg, uint32_t val) 2368 { 2369 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2370 2371 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2372 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | 2373 WRITE_DATA_DST_SEL(0))); 2374 amdgpu_ring_write(ring, reg); 2375 amdgpu_ring_write(ring, 0); 2376 amdgpu_ring_write(ring, val); 2377 } 2378 2379 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev) 2380 { 2381 const u32 *src_ptr; 2382 volatile u32 *dst_ptr; 2383 u32 dws; 2384 u64 reg_list_mc_addr; 2385 const struct cs_section_def *cs_data; 2386 int r; 2387 2388 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; 2389 adev->gfx.rlc.reg_list_size = 2390 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list); 2391 2392 adev->gfx.rlc.cs_data = si_cs_data; 2393 src_ptr = adev->gfx.rlc.reg_list; 2394 dws = adev->gfx.rlc.reg_list_size; 2395 cs_data = adev->gfx.rlc.cs_data; 2396 2397 if (src_ptr) { 2398 /* init save restore block */ 2399 r = amdgpu_gfx_rlc_init_sr(adev, dws); 2400 if (r) 2401 return r; 2402 } 2403 2404 if (cs_data) { 2405 /* clear state block */ 2406 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); 2407 dws = adev->gfx.rlc.clear_state_size + (256 / 4); 2408 2409 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 2410 AMDGPU_GEM_DOMAIN_VRAM, 2411 &adev->gfx.rlc.clear_state_obj, 2412 &adev->gfx.rlc.clear_state_gpu_addr, 2413 (void **)__UNVOLATILE(&adev->gfx.rlc.cs_ptr)); 2414 if (r) { 2415 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r); 2416 amdgpu_gfx_rlc_fini(adev); 2417 return r; 2418 } 2419 2420 /* set up the cs buffer */ 2421 dst_ptr = adev->gfx.rlc.cs_ptr; 2422 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256; 2423 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); 2424 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); 2425 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size); 2426 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]); 2427 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 2428 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 2429 } 2430 2431 return 0; 2432 } 2433 2434 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 2435 { 2436 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2437 2438 if (!enable) { 2439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2440 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2441 } 2442 } 2443 2444 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2445 { 2446 int i; 2447 2448 for (i = 0; i < adev->usec_timeout; i++) { 2449 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0) 2450 break; 2451 udelay(1); 2452 } 2453 2454 for (i = 0; i < adev->usec_timeout; i++) { 2455 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0) 2456 break; 2457 udelay(1); 2458 } 2459 } 2460 2461 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) 2462 { 2463 u32 tmp; 2464 2465 tmp = RREG32(mmRLC_CNTL); 2466 if (tmp != rlc) 2467 WREG32(mmRLC_CNTL, rlc); 2468 } 2469 2470 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev) 2471 { 2472 u32 data, orig; 2473 2474 orig = data = RREG32(mmRLC_CNTL); 2475 2476 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2477 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK; 2478 WREG32(mmRLC_CNTL, data); 2479 2480 gfx_v6_0_wait_for_rlc_serdes(adev); 2481 } 2482 2483 return orig; 2484 } 2485 2486 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev) 2487 { 2488 WREG32(mmRLC_CNTL, 0); 2489 2490 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2491 gfx_v6_0_wait_for_rlc_serdes(adev); 2492 } 2493 2494 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev) 2495 { 2496 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 2497 2498 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2499 2500 udelay(50); 2501 } 2502 2503 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev) 2504 { 2505 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2506 udelay(50); 2507 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2508 udelay(50); 2509 } 2510 2511 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev) 2512 { 2513 u32 tmp; 2514 2515 /* Enable LBPW only for DDR3 */ 2516 tmp = RREG32(mmMC_SEQ_MISC0); 2517 if ((tmp & 0xF0000000) == 0xB0000000) 2518 return true; 2519 return false; 2520 } 2521 2522 static void gfx_v6_0_init_cg(struct amdgpu_device *adev) 2523 { 2524 } 2525 2526 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev) 2527 { 2528 u32 i; 2529 const struct rlc_firmware_header_v1_0 *hdr; 2530 const __le32 *fw_data; 2531 u32 fw_size; 2532 2533 2534 if (!adev->gfx.rlc_fw) 2535 return -EINVAL; 2536 2537 adev->gfx.rlc.funcs->stop(adev); 2538 adev->gfx.rlc.funcs->reset(adev); 2539 gfx_v6_0_init_pg(adev); 2540 gfx_v6_0_init_cg(adev); 2541 2542 WREG32(mmRLC_RL_BASE, 0); 2543 WREG32(mmRLC_RL_SIZE, 0); 2544 WREG32(mmRLC_LB_CNTL, 0); 2545 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff); 2546 WREG32(mmRLC_LB_CNTR_INIT, 0); 2547 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 2548 2549 WREG32(mmRLC_MC_CNTL, 0); 2550 WREG32(mmRLC_UCODE_CNTL, 0); 2551 2552 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; 2553 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2554 fw_data = (const __le32 *) 2555 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2556 2557 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2558 2559 for (i = 0; i < fw_size; i++) { 2560 WREG32(mmRLC_UCODE_ADDR, i); 2561 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++)); 2562 } 2563 WREG32(mmRLC_UCODE_ADDR, 0); 2564 2565 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev)); 2566 adev->gfx.rlc.funcs->start(adev); 2567 2568 return 0; 2569 } 2570 2571 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable) 2572 { 2573 u32 data, orig, tmp; 2574 2575 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); 2576 2577 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2578 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2579 2580 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080); 2581 2582 tmp = gfx_v6_0_halt_rlc(adev); 2583 2584 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2585 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2586 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff); 2587 2588 gfx_v6_0_wait_for_rlc_serdes(adev); 2589 gfx_v6_0_update_rlc(adev, tmp); 2590 2591 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff); 2592 2593 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2594 } else { 2595 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2596 2597 RREG32(mmCB_CGTT_SCLK_CTRL); 2598 RREG32(mmCB_CGTT_SCLK_CTRL); 2599 RREG32(mmCB_CGTT_SCLK_CTRL); 2600 RREG32(mmCB_CGTT_SCLK_CTRL); 2601 2602 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2603 } 2604 2605 if (orig != data) 2606 WREG32(mmRLC_CGCG_CGLS_CTRL, data); 2607 2608 } 2609 2610 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable) 2611 { 2612 2613 u32 data, orig, tmp = 0; 2614 2615 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2616 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2617 data = 0x96940200; 2618 if (orig != data) 2619 WREG32(mmCGTS_SM_CTRL_REG, data); 2620 2621 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2622 orig = data = RREG32(mmCP_MEM_SLP_CNTL); 2623 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2624 if (orig != data) 2625 WREG32(mmCP_MEM_SLP_CNTL, data); 2626 } 2627 2628 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2629 data &= 0xffffffc0; 2630 if (orig != data) 2631 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2632 2633 tmp = gfx_v6_0_halt_rlc(adev); 2634 2635 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2636 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2637 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff); 2638 2639 gfx_v6_0_update_rlc(adev, tmp); 2640 } else { 2641 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE); 2642 data |= 0x00000003; 2643 if (orig != data) 2644 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data); 2645 2646 data = RREG32(mmCP_MEM_SLP_CNTL); 2647 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2648 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2649 WREG32(mmCP_MEM_SLP_CNTL, data); 2650 } 2651 orig = data = RREG32(mmCGTS_SM_CTRL_REG); 2652 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK; 2653 if (orig != data) 2654 WREG32(mmCGTS_SM_CTRL_REG, data); 2655 2656 tmp = gfx_v6_0_halt_rlc(adev); 2657 2658 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); 2659 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); 2660 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff); 2661 2662 gfx_v6_0_update_rlc(adev, tmp); 2663 } 2664 } 2665 /* 2666 static void gfx_v6_0_update_cg(struct amdgpu_device *adev, 2667 bool enable) 2668 { 2669 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 2670 if (enable) { 2671 gfx_v6_0_enable_mgcg(adev, true); 2672 gfx_v6_0_enable_cgcg(adev, true); 2673 } else { 2674 gfx_v6_0_enable_cgcg(adev, false); 2675 gfx_v6_0_enable_mgcg(adev, false); 2676 } 2677 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 2678 } 2679 */ 2680 2681 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev, 2682 bool enable) 2683 { 2684 } 2685 2686 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev, 2687 bool enable) 2688 { 2689 } 2690 2691 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable) 2692 { 2693 u32 data, orig; 2694 2695 orig = data = RREG32(mmRLC_PG_CNTL); 2696 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP)) 2697 data &= ~0x8000; 2698 else 2699 data |= 0x8000; 2700 if (orig != data) 2701 WREG32(mmRLC_PG_CNTL, data); 2702 } 2703 2704 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable) 2705 { 2706 } 2707 /* 2708 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev) 2709 { 2710 const __le32 *fw_data; 2711 volatile u32 *dst_ptr; 2712 int me, i, max_me = 4; 2713 u32 bo_offset = 0; 2714 u32 table_offset, table_size; 2715 2716 if (adev->asic_type == CHIP_KAVERI) 2717 max_me = 5; 2718 2719 if (adev->gfx.rlc.cp_table_ptr == NULL) 2720 return; 2721 2722 dst_ptr = adev->gfx.rlc.cp_table_ptr; 2723 for (me = 0; me < max_me; me++) { 2724 if (me == 0) { 2725 const struct gfx_firmware_header_v1_0 *hdr = 2726 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 2727 fw_data = (const __le32 *) 2728 (adev->gfx.ce_fw->data + 2729 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2730 table_offset = le32_to_cpu(hdr->jt_offset); 2731 table_size = le32_to_cpu(hdr->jt_size); 2732 } else if (me == 1) { 2733 const struct gfx_firmware_header_v1_0 *hdr = 2734 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 2735 fw_data = (const __le32 *) 2736 (adev->gfx.pfp_fw->data + 2737 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2738 table_offset = le32_to_cpu(hdr->jt_offset); 2739 table_size = le32_to_cpu(hdr->jt_size); 2740 } else if (me == 2) { 2741 const struct gfx_firmware_header_v1_0 *hdr = 2742 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 2743 fw_data = (const __le32 *) 2744 (adev->gfx.me_fw->data + 2745 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2746 table_offset = le32_to_cpu(hdr->jt_offset); 2747 table_size = le32_to_cpu(hdr->jt_size); 2748 } else if (me == 3) { 2749 const struct gfx_firmware_header_v1_0 *hdr = 2750 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2751 fw_data = (const __le32 *) 2752 (adev->gfx.mec_fw->data + 2753 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2754 table_offset = le32_to_cpu(hdr->jt_offset); 2755 table_size = le32_to_cpu(hdr->jt_size); 2756 } else { 2757 const struct gfx_firmware_header_v1_0 *hdr = 2758 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 2759 fw_data = (const __le32 *) 2760 (adev->gfx.mec2_fw->data + 2761 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2762 table_offset = le32_to_cpu(hdr->jt_offset); 2763 table_size = le32_to_cpu(hdr->jt_size); 2764 } 2765 2766 for (i = 0; i < table_size; i ++) { 2767 dst_ptr[bo_offset + i] = 2768 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 2769 } 2770 2771 bo_offset += table_size; 2772 } 2773 } 2774 */ 2775 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev, 2776 bool enable) 2777 { 2778 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 2779 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10)); 2780 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); 2781 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); 2782 } else { 2783 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); 2784 (void)RREG32(mmDB_RENDER_CONTROL); 2785 } 2786 } 2787 2788 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev) 2789 { 2790 u32 tmp; 2791 2792 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask); 2793 2794 tmp = RREG32(mmRLC_MAX_PG_CU); 2795 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK; 2796 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT); 2797 WREG32(mmRLC_MAX_PG_CU, tmp); 2798 } 2799 2800 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev, 2801 bool enable) 2802 { 2803 u32 data, orig; 2804 2805 orig = data = RREG32(mmRLC_PG_CNTL); 2806 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG)) 2807 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2808 else 2809 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK; 2810 if (orig != data) 2811 WREG32(mmRLC_PG_CNTL, data); 2812 } 2813 2814 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev, 2815 bool enable) 2816 { 2817 u32 data, orig; 2818 2819 orig = data = RREG32(mmRLC_PG_CNTL); 2820 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG)) 2821 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2822 else 2823 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK; 2824 if (orig != data) 2825 WREG32(mmRLC_PG_CNTL, data); 2826 } 2827 2828 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev) 2829 { 2830 u32 tmp; 2831 2832 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2833 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); 2834 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2835 2836 tmp = RREG32(mmRLC_AUTO_PG_CTRL); 2837 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2838 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2839 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK; 2840 WREG32(mmRLC_AUTO_PG_CTRL, tmp); 2841 } 2842 2843 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable) 2844 { 2845 gfx_v6_0_enable_gfx_cgpg(adev, enable); 2846 gfx_v6_0_enable_gfx_static_mgpg(adev, enable); 2847 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable); 2848 } 2849 2850 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev) 2851 { 2852 u32 count = 0; 2853 const struct cs_section_def *sect = NULL; 2854 const struct cs_extent_def *ext = NULL; 2855 2856 if (adev->gfx.rlc.cs_data == NULL) 2857 return 0; 2858 2859 /* begin clear state */ 2860 count += 2; 2861 /* context control state */ 2862 count += 3; 2863 2864 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2865 for (ext = sect->section; ext->extent != NULL; ++ext) { 2866 if (sect->id == SECT_CONTEXT) 2867 count += 2 + ext->reg_count; 2868 else 2869 return 0; 2870 } 2871 } 2872 /* pa_sc_raster_config */ 2873 count += 3; 2874 /* end clear state */ 2875 count += 2; 2876 /* clear state */ 2877 count += 2; 2878 2879 return count; 2880 } 2881 2882 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, 2883 volatile u32 *buffer) 2884 { 2885 u32 count = 0, i; 2886 const struct cs_section_def *sect = NULL; 2887 const struct cs_extent_def *ext = NULL; 2888 2889 if (adev->gfx.rlc.cs_data == NULL) 2890 return; 2891 if (buffer == NULL) 2892 return; 2893 2894 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2895 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2896 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2897 buffer[count++] = cpu_to_le32(0x80000000); 2898 buffer[count++] = cpu_to_le32(0x80000000); 2899 2900 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 2901 for (ext = sect->section; ext->extent != NULL; ++ext) { 2902 if (sect->id == SECT_CONTEXT) { 2903 buffer[count++] = 2904 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 2905 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); 2906 for (i = 0; i < ext->reg_count; i++) 2907 buffer[count++] = cpu_to_le32(ext->extent[i]); 2908 } else { 2909 return; 2910 } 2911 } 2912 } 2913 2914 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2915 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); 2916 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config); 2917 2918 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2919 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 2920 2921 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 2922 buffer[count++] = cpu_to_le32(0); 2923 } 2924 2925 static void gfx_v6_0_init_pg(struct amdgpu_device *adev) 2926 { 2927 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2928 AMD_PG_SUPPORT_GFX_SMG | 2929 AMD_PG_SUPPORT_GFX_DMG | 2930 AMD_PG_SUPPORT_CP | 2931 AMD_PG_SUPPORT_GDS | 2932 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2933 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true); 2934 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true); 2935 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2936 gfx_v6_0_init_gfx_cgpg(adev); 2937 gfx_v6_0_enable_cp_pg(adev, true); 2938 gfx_v6_0_enable_gds_pg(adev, true); 2939 } else { 2940 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2941 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2942 2943 } 2944 gfx_v6_0_init_ao_cu_mask(adev); 2945 gfx_v6_0_update_gfx_pg(adev, true); 2946 } else { 2947 2948 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); 2949 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8); 2950 } 2951 } 2952 2953 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev) 2954 { 2955 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2956 AMD_PG_SUPPORT_GFX_SMG | 2957 AMD_PG_SUPPORT_GFX_DMG | 2958 AMD_PG_SUPPORT_CP | 2959 AMD_PG_SUPPORT_GDS | 2960 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2961 gfx_v6_0_update_gfx_pg(adev, false); 2962 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 2963 gfx_v6_0_enable_cp_pg(adev, false); 2964 gfx_v6_0_enable_gds_pg(adev, false); 2965 } 2966 } 2967 } 2968 2969 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) 2970 { 2971 uint64_t clock; 2972 2973 mutex_lock(&adev->gfx.gpu_clock_mutex); 2974 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 2975 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) | 2976 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 2977 mutex_unlock(&adev->gfx.gpu_clock_mutex); 2978 return clock; 2979 } 2980 2981 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 2982 { 2983 if (flags & AMDGPU_HAVE_CTX_SWITCH) 2984 gfx_v6_0_ring_emit_vgt_flush(ring); 2985 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2986 amdgpu_ring_write(ring, 0x80000000); 2987 amdgpu_ring_write(ring, 0); 2988 } 2989 2990 2991 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2992 { 2993 WREG32(mmSQ_IND_INDEX, 2994 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2995 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2996 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2997 (SQ_IND_INDEX__FORCE_READ_MASK)); 2998 return RREG32(mmSQ_IND_DATA); 2999 } 3000 3001 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 3002 uint32_t wave, uint32_t thread, 3003 uint32_t regno, uint32_t num, uint32_t *out) 3004 { 3005 WREG32(mmSQ_IND_INDEX, 3006 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 3007 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 3008 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 3009 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 3010 (SQ_IND_INDEX__FORCE_READ_MASK) | 3011 (SQ_IND_INDEX__AUTO_INCR_MASK)); 3012 while (num--) 3013 *(out++) = RREG32(mmSQ_IND_DATA); 3014 } 3015 3016 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 3017 { 3018 /* type 0 wave data */ 3019 dst[(*no_fields)++] = 0; 3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 3024 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 3025 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 3026 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 3027 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 3028 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 3029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 3030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 3031 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 3032 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); 3033 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); 3034 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); 3035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); 3036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 3037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 3038 } 3039 3040 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 3041 uint32_t wave, uint32_t start, 3042 uint32_t size, uint32_t *dst) 3043 { 3044 wave_read_regs( 3045 adev, simd, wave, 0, 3046 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 3047 } 3048 3049 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, 3050 u32 me, u32 pipe, u32 q, u32 vm) 3051 { 3052 DRM_INFO("Not implemented\n"); 3053 } 3054 3055 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { 3056 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, 3057 .select_se_sh = &gfx_v6_0_select_se_sh, 3058 .read_wave_data = &gfx_v6_0_read_wave_data, 3059 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs, 3060 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q 3061 }; 3062 3063 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { 3064 .init = gfx_v6_0_rlc_init, 3065 .resume = gfx_v6_0_rlc_resume, 3066 .stop = gfx_v6_0_rlc_stop, 3067 .reset = gfx_v6_0_rlc_reset, 3068 .start = gfx_v6_0_rlc_start 3069 }; 3070 3071 static int gfx_v6_0_early_init(void *handle) 3072 { 3073 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3074 3075 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; 3076 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS; 3077 adev->gfx.funcs = &gfx_v6_0_gfx_funcs; 3078 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs; 3079 gfx_v6_0_set_ring_funcs(adev); 3080 gfx_v6_0_set_irq_funcs(adev); 3081 3082 return 0; 3083 } 3084 3085 static int gfx_v6_0_sw_init(void *handle) 3086 { 3087 struct amdgpu_ring *ring; 3088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3089 int i, r; 3090 3091 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); 3092 if (r) 3093 return r; 3094 3095 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq); 3096 if (r) 3097 return r; 3098 3099 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq); 3100 if (r) 3101 return r; 3102 3103 gfx_v6_0_scratch_init(adev); 3104 3105 r = gfx_v6_0_init_microcode(adev); 3106 if (r) { 3107 DRM_ERROR("Failed to load gfx firmware!\n"); 3108 return r; 3109 } 3110 3111 r = adev->gfx.rlc.funcs->init(adev); 3112 if (r) { 3113 DRM_ERROR("Failed to init rlc BOs!\n"); 3114 return r; 3115 } 3116 3117 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3118 ring = &adev->gfx.gfx_ring[i]; 3119 ring->ring_obj = NULL; 3120 snprintf(ring->name, sizeof(ring->name), "gfx"); 3121 r = amdgpu_ring_init(adev, ring, 1024, 3122 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); 3123 if (r) 3124 return r; 3125 } 3126 3127 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3128 unsigned irq_type; 3129 3130 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) { 3131 DRM_ERROR("Too many (%d) compute rings!\n", i); 3132 break; 3133 } 3134 ring = &adev->gfx.compute_ring[i]; 3135 ring->ring_obj = NULL; 3136 ring->use_doorbell = false; 3137 ring->doorbell_index = 0; 3138 ring->me = 1; 3139 ring->pipe = i; 3140 ring->queue = i; 3141 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 3142 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; 3143 r = amdgpu_ring_init(adev, ring, 1024, 3144 &adev->gfx.eop_irq, irq_type); 3145 if (r) 3146 return r; 3147 } 3148 3149 return r; 3150 } 3151 3152 static int gfx_v6_0_sw_fini(void *handle) 3153 { 3154 int i; 3155 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3156 3157 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3158 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 3159 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3160 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 3161 3162 amdgpu_gfx_rlc_fini(adev); 3163 3164 return 0; 3165 } 3166 3167 static int gfx_v6_0_hw_init(void *handle) 3168 { 3169 int r; 3170 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3171 3172 gfx_v6_0_constants_init(adev); 3173 3174 r = adev->gfx.rlc.funcs->resume(adev); 3175 if (r) 3176 return r; 3177 3178 r = gfx_v6_0_cp_resume(adev); 3179 if (r) 3180 return r; 3181 3182 adev->gfx.ce_ram_size = 0x8000; 3183 3184 return r; 3185 } 3186 3187 static int gfx_v6_0_hw_fini(void *handle) 3188 { 3189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3190 3191 gfx_v6_0_cp_enable(adev, false); 3192 adev->gfx.rlc.funcs->stop(adev); 3193 gfx_v6_0_fini_pg(adev); 3194 3195 return 0; 3196 } 3197 3198 static int gfx_v6_0_suspend(void *handle) 3199 { 3200 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3201 3202 return gfx_v6_0_hw_fini(adev); 3203 } 3204 3205 static int gfx_v6_0_resume(void *handle) 3206 { 3207 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3208 3209 return gfx_v6_0_hw_init(adev); 3210 } 3211 3212 static bool gfx_v6_0_is_idle(void *handle) 3213 { 3214 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3215 3216 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK) 3217 return false; 3218 else 3219 return true; 3220 } 3221 3222 static int gfx_v6_0_wait_for_idle(void *handle) 3223 { 3224 unsigned i; 3225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3226 3227 for (i = 0; i < adev->usec_timeout; i++) { 3228 if (gfx_v6_0_is_idle(handle)) 3229 return 0; 3230 udelay(1); 3231 } 3232 return -ETIMEDOUT; 3233 } 3234 3235 static int gfx_v6_0_soft_reset(void *handle) 3236 { 3237 return 0; 3238 } 3239 3240 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 3241 enum amdgpu_interrupt_state state) 3242 { 3243 u32 cp_int_cntl; 3244 3245 switch (state) { 3246 case AMDGPU_IRQ_STATE_DISABLE: 3247 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3248 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3249 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3250 break; 3251 case AMDGPU_IRQ_STATE_ENABLE: 3252 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3253 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3254 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3255 break; 3256 default: 3257 break; 3258 } 3259 } 3260 3261 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3262 int ring, 3263 enum amdgpu_interrupt_state state) 3264 { 3265 u32 cp_int_cntl; 3266 switch (state){ 3267 case AMDGPU_IRQ_STATE_DISABLE: 3268 if (ring == 0) { 3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3270 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3271 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3272 break; 3273 } else { 3274 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3275 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3276 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3277 break; 3278 3279 } 3280 case AMDGPU_IRQ_STATE_ENABLE: 3281 if (ring == 0) { 3282 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3283 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK; 3284 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl); 3285 break; 3286 } else { 3287 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2); 3288 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK; 3289 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl); 3290 break; 3291 3292 } 3293 3294 default: 3295 BUG(); 3296 break; 3297 3298 } 3299 } 3300 3301 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 3302 struct amdgpu_irq_src *src, 3303 unsigned type, 3304 enum amdgpu_interrupt_state state) 3305 { 3306 u32 cp_int_cntl; 3307 3308 switch (state) { 3309 case AMDGPU_IRQ_STATE_DISABLE: 3310 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3311 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3312 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3313 break; 3314 case AMDGPU_IRQ_STATE_ENABLE: 3315 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3316 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK; 3317 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3318 break; 3319 default: 3320 break; 3321 } 3322 3323 return 0; 3324 } 3325 3326 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 3327 struct amdgpu_irq_src *src, 3328 unsigned type, 3329 enum amdgpu_interrupt_state state) 3330 { 3331 u32 cp_int_cntl; 3332 3333 switch (state) { 3334 case AMDGPU_IRQ_STATE_DISABLE: 3335 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3336 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3337 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3338 break; 3339 case AMDGPU_IRQ_STATE_ENABLE: 3340 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3341 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK; 3342 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3343 break; 3344 default: 3345 break; 3346 } 3347 3348 return 0; 3349 } 3350 3351 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev, 3352 struct amdgpu_irq_src *src, 3353 unsigned type, 3354 enum amdgpu_interrupt_state state) 3355 { 3356 switch (type) { 3357 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 3358 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state); 3359 break; 3360 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3361 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state); 3362 break; 3363 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3364 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state); 3365 break; 3366 default: 3367 break; 3368 } 3369 return 0; 3370 } 3371 3372 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev, 3373 struct amdgpu_irq_src *source, 3374 struct amdgpu_iv_entry *entry) 3375 { 3376 switch (entry->ring_id) { 3377 case 0: 3378 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 3379 break; 3380 case 1: 3381 case 2: 3382 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]); 3383 break; 3384 default: 3385 break; 3386 } 3387 return 0; 3388 } 3389 3390 static void gfx_v6_0_fault(struct amdgpu_device *adev, 3391 struct amdgpu_iv_entry *entry) 3392 { 3393 struct amdgpu_ring *ring; 3394 3395 switch (entry->ring_id) { 3396 case 0: 3397 ring = &adev->gfx.gfx_ring[0]; 3398 break; 3399 case 1: 3400 case 2: 3401 ring = &adev->gfx.compute_ring[entry->ring_id - 1]; 3402 break; 3403 default: 3404 return; 3405 } 3406 drm_sched_fault(&ring->sched); 3407 } 3408 3409 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev, 3410 struct amdgpu_irq_src *source, 3411 struct amdgpu_iv_entry *entry) 3412 { 3413 DRM_ERROR("Illegal register access in command stream\n"); 3414 gfx_v6_0_fault(adev, entry); 3415 return 0; 3416 } 3417 3418 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev, 3419 struct amdgpu_irq_src *source, 3420 struct amdgpu_iv_entry *entry) 3421 { 3422 DRM_ERROR("Illegal instruction in command stream\n"); 3423 gfx_v6_0_fault(adev, entry); 3424 return 0; 3425 } 3426 3427 static int gfx_v6_0_set_clockgating_state(void *handle, 3428 enum amd_clockgating_state state) 3429 { 3430 bool gate = false; 3431 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3432 3433 if (state == AMD_CG_STATE_GATE) 3434 gate = true; 3435 3436 gfx_v6_0_enable_gui_idle_interrupt(adev, false); 3437 if (gate) { 3438 gfx_v6_0_enable_mgcg(adev, true); 3439 gfx_v6_0_enable_cgcg(adev, true); 3440 } else { 3441 gfx_v6_0_enable_cgcg(adev, false); 3442 gfx_v6_0_enable_mgcg(adev, false); 3443 } 3444 gfx_v6_0_enable_gui_idle_interrupt(adev, true); 3445 3446 return 0; 3447 } 3448 3449 static int gfx_v6_0_set_powergating_state(void *handle, 3450 enum amd_powergating_state state) 3451 { 3452 bool gate = false; 3453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3454 3455 if (state == AMD_PG_STATE_GATE) 3456 gate = true; 3457 3458 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 3459 AMD_PG_SUPPORT_GFX_SMG | 3460 AMD_PG_SUPPORT_GFX_DMG | 3461 AMD_PG_SUPPORT_CP | 3462 AMD_PG_SUPPORT_GDS | 3463 AMD_PG_SUPPORT_RLC_SMU_HS)) { 3464 gfx_v6_0_update_gfx_pg(adev, gate); 3465 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) { 3466 gfx_v6_0_enable_cp_pg(adev, gate); 3467 gfx_v6_0_enable_gds_pg(adev, gate); 3468 } 3469 } 3470 3471 return 0; 3472 } 3473 3474 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 3475 .name = "gfx_v6_0", 3476 .early_init = gfx_v6_0_early_init, 3477 .late_init = NULL, 3478 .sw_init = gfx_v6_0_sw_init, 3479 .sw_fini = gfx_v6_0_sw_fini, 3480 .hw_init = gfx_v6_0_hw_init, 3481 .hw_fini = gfx_v6_0_hw_fini, 3482 .suspend = gfx_v6_0_suspend, 3483 .resume = gfx_v6_0_resume, 3484 .is_idle = gfx_v6_0_is_idle, 3485 .wait_for_idle = gfx_v6_0_wait_for_idle, 3486 .soft_reset = gfx_v6_0_soft_reset, 3487 .set_clockgating_state = gfx_v6_0_set_clockgating_state, 3488 .set_powergating_state = gfx_v6_0_set_powergating_state, 3489 }; 3490 3491 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 3492 .type = AMDGPU_RING_TYPE_GFX, 3493 .align_mask = 0xff, 3494 .nop = 0x80000000, 3495 .support_64bit_ptrs = false, 3496 .get_rptr = gfx_v6_0_ring_get_rptr, 3497 .get_wptr = gfx_v6_0_ring_get_wptr, 3498 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3499 .emit_frame_size = 3500 5 + 5 + /* hdp flush / invalidate */ 3501 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3502 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3503 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ 3504 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */ 3505 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3506 .emit_ib = gfx_v6_0_ring_emit_ib, 3507 .emit_fence = gfx_v6_0_ring_emit_fence, 3508 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3509 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3510 .test_ring = gfx_v6_0_ring_test_ring, 3511 .test_ib = gfx_v6_0_ring_test_ib, 3512 .insert_nop = amdgpu_ring_insert_nop, 3513 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, 3514 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3515 }; 3516 3517 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { 3518 .type = AMDGPU_RING_TYPE_COMPUTE, 3519 .align_mask = 0xff, 3520 .nop = 0x80000000, 3521 .get_rptr = gfx_v6_0_ring_get_rptr, 3522 .get_wptr = gfx_v6_0_ring_get_wptr, 3523 .set_wptr = gfx_v6_0_ring_set_wptr_compute, 3524 .emit_frame_size = 3525 5 + 5 + /* hdp flush / invalidate */ 3526 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ 3527 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ 3528 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ 3529 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ 3530 .emit_ib = gfx_v6_0_ring_emit_ib, 3531 .emit_fence = gfx_v6_0_ring_emit_fence, 3532 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, 3533 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, 3534 .test_ring = gfx_v6_0_ring_test_ring, 3535 .test_ib = gfx_v6_0_ring_test_ib, 3536 .insert_nop = amdgpu_ring_insert_nop, 3537 .emit_wreg = gfx_v6_0_ring_emit_wreg, 3538 }; 3539 3540 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) 3541 { 3542 int i; 3543 3544 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3545 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx; 3546 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3547 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute; 3548 } 3549 3550 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = { 3551 .set = gfx_v6_0_set_eop_interrupt_state, 3552 .process = gfx_v6_0_eop_irq, 3553 }; 3554 3555 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = { 3556 .set = gfx_v6_0_set_priv_reg_fault_state, 3557 .process = gfx_v6_0_priv_reg_irq, 3558 }; 3559 3560 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = { 3561 .set = gfx_v6_0_set_priv_inst_fault_state, 3562 .process = gfx_v6_0_priv_inst_irq, 3563 }; 3564 3565 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3566 { 3567 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3568 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs; 3569 3570 adev->gfx.priv_reg_irq.num_types = 1; 3571 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs; 3572 3573 adev->gfx.priv_inst_irq.num_types = 1; 3574 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs; 3575 } 3576 3577 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) 3578 { 3579 int i, j, k, counter, active_cu_number = 0; 3580 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 3581 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3582 unsigned disable_masks[4 * 2]; 3583 u32 ao_cu_num; 3584 3585 if (adev->flags & AMD_IS_APU) 3586 ao_cu_num = 2; 3587 else 3588 ao_cu_num = adev->gfx.config.max_cu_per_sh; 3589 3590 memset(cu_info, 0, sizeof(*cu_info)); 3591 3592 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3593 3594 mutex_lock(&adev->grbm_idx_mutex); 3595 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3596 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3597 mask = 1; 3598 ao_bitmap = 0; 3599 counter = 0; 3600 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3601 if (i < 4 && j < 2) 3602 gfx_v6_0_set_user_cu_inactive_bitmap( 3603 adev, disable_masks[i * 2 + j]); 3604 bitmap = gfx_v6_0_get_cu_enabled(adev); 3605 cu_info->bitmap[i][j] = bitmap; 3606 3607 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3608 if (bitmap & mask) { 3609 if (counter < ao_cu_num) 3610 ao_bitmap |= mask; 3611 counter ++; 3612 } 3613 mask <<= 1; 3614 } 3615 active_cu_number += counter; 3616 if (i < 2 && j < 2) 3617 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 3618 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 3619 } 3620 } 3621 3622 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3623 mutex_unlock(&adev->grbm_idx_mutex); 3624 3625 cu_info->number = active_cu_number; 3626 cu_info->ao_cu_mask = ao_cu_mask; 3627 } 3628 3629 const struct amdgpu_ip_block_version gfx_v6_0_ip_block = 3630 { 3631 .type = AMD_IP_BLOCK_TYPE_GFX, 3632 .major = 6, 3633 .minor = 0, 3634 .rev = 0, 3635 .funcs = &gfx_v6_0_ip_funcs, 3636 }; 3637
Indexes created Sat Sep 20 22:09:52 GMT 2025