1 /* $NetBSD: pci_intr_machdep.c,v 1.51 2020/08/01 12:36:35 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2009 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: pci_intr_machdep.c,v 1.51 2020/08/01 12:36:35 jdolecek Exp $"); 77 78 #include <sys/types.h> 79 #include <sys/param.h> 80 #include <sys/time.h> 81 #include <sys/systm.h> 82 #include <sys/cpu.h> 83 #include <sys/errno.h> 84 #include <sys/device.h> 85 #include <sys/intr.h> 86 #include <sys/kmem.h> 87 88 #include "ioapic.h" 89 #include "eisa.h" 90 #include "acpica.h" 91 #include "opt_mpbios.h" 92 #include "opt_acpi.h" 93 #include "opt_pci.h" 94 95 #include <dev/pci/pcivar.h> 96 97 #include <machine/i82489reg.h> 98 99 #if NIOAPIC > 0 || NACPICA > 0 100 #include <machine/i82093reg.h> 101 #include <machine/i82093var.h> 102 #include <machine/mpconfig.h> 103 #include <machine/mpbiosvar.h> 104 #include <machine/pic.h> 105 #include <x86/pci/pci_msi_machdep.h> 106 #else 107 #include <machine/i82093var.h> 108 #endif 109 110 #ifdef MPBIOS 111 #include <machine/mpbiosvar.h> 112 #endif 113 114 #if NACPICA > 0 115 #include <machine/mpacpi.h> 116 #endif 117 118 int 119 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 120 { 121 pci_intr_pin_t pin = pa->pa_intrpin; 122 pci_intr_line_t line = pa->pa_intrline; 123 pci_chipset_tag_t ipc, pc = pa->pa_pc; 124 #if NIOAPIC > 0 || NACPICA > 0 125 pci_intr_pin_t rawpin = pa->pa_rawintrpin; 126 int bus, dev, func; 127 #endif 128 129 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 130 if ((ipc->pc_present & PCI_OVERRIDE_INTR_MAP) == 0) 131 continue; 132 return (*ipc->pc_ov->ov_intr_map)(ipc->pc_ctx, pa, ihp); 133 } 134 135 if (pin == 0) { 136 /* No IRQ used. */ 137 goto bad; 138 } 139 140 *ihp = 0; 141 142 if (pin > PCI_INTERRUPT_PIN_MAX) { 143 aprint_normal("pci_intr_map: bad interrupt pin %d\n", pin); 144 goto bad; 145 } 146 147 #if NIOAPIC > 0 || NACPICA > 0 148 KASSERT(rawpin >= PCI_INTERRUPT_PIN_A); 149 KASSERT(rawpin <= PCI_INTERRUPT_PIN_D); 150 pci_decompose_tag(pc, pa->pa_tag, &bus, &dev, &func); 151 if (mp_busses != NULL) { 152 /* 153 * Note: PCI_INTERRUPT_PIN_A == 1 where intr_find_mpmapping 154 * wants pci bus_pin encoding which uses INT_A == 0. 155 */ 156 if (intr_find_mpmapping(bus, 157 (dev << 2) | (rawpin - PCI_INTERRUPT_PIN_A), ihp) == 0) { 158 if (APIC_IRQ_LEGACY_IRQ(*ihp) == 0) 159 *ihp |= line; 160 return 0; 161 } 162 /* 163 * No explicit PCI mapping found. This is not fatal, 164 * we'll try the ISA (or possibly EISA) mappings next. 165 */ 166 } 167 #endif 168 169 /* 170 * Section 6.2.4, `Miscellaneous Functions', says that 255 means 171 * `unknown' or `no connection' on a PC. We assume that a device with 172 * `no connection' either doesn't have an interrupt (in which case the 173 * pin number should be 0, and would have been noticed above), or 174 * wasn't configured by the BIOS (in which case we punt, since there's 175 * no real way we can know how the interrupt lines are mapped in the 176 * hardware). 177 * 178 * XXX 179 * Since IRQ 0 is only used by the clock, and we can't actually be sure 180 * that the BIOS did its job, we also recognize that as meaning that 181 * the BIOS has not configured the device. 182 */ 183 if (line == 0 || line == X86_PCI_INTERRUPT_LINE_NO_CONNECTION) { 184 aprint_normal("pci_intr_map: no mapping for pin %c (line=%02x)\n", 185 '@' + pin, line); 186 goto bad; 187 } else { 188 if (line >= NUM_LEGACY_IRQS) { 189 aprint_normal("pci_intr_map: bad interrupt line %d\n", line); 190 goto bad; 191 } 192 if (line == 2) { 193 aprint_normal("pci_intr_map: changed line 2 to line 9\n"); 194 line = 9; 195 } 196 } 197 #if NIOAPIC > 0 || NACPICA > 0 198 if (mp_busses != NULL) { 199 if (intr_find_mpmapping(mp_isa_bus, line, ihp) == 0) { 200 if ((*ihp & 0xff) == 0) 201 *ihp |= line; 202 return 0; 203 } 204 #if NEISA > 0 205 if (intr_find_mpmapping(mp_eisa_bus, line, ihp) == 0) { 206 if ((*ihp & 0xff) == 0) 207 *ihp |= line; 208 return 0; 209 } 210 #endif 211 aprint_normal("pci_intr_map: bus %d dev %d func %d pin %d; line %d\n", 212 bus, dev, func, pin, line); 213 aprint_normal("pci_intr_map: no MP mapping found\n"); 214 } 215 #endif 216 217 *ihp = line; 218 return 0; 219 220 bad: 221 *ihp = -1; 222 return 1; 223 } 224 225 const char * 226 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 227 size_t len) 228 { 229 pci_chipset_tag_t ipc; 230 231 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 232 if ((ipc->pc_present & PCI_OVERRIDE_INTR_STRING) == 0) 233 continue; 234 return (*ipc->pc_ov->ov_intr_string)(ipc->pc_ctx, pc, ih, 235 buf, len); 236 } 237 238 #if defined(__HAVE_PCI_MSI_MSIX) 239 if (INT_VIA_MSI(ih)) 240 return x86_pci_msi_string(pc, ih, buf, len); 241 #endif 242 243 return intr_string(ih & ~MPSAFE_MASK, buf, len); 244 } 245 246 247 const struct evcnt * 248 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 249 { 250 pci_chipset_tag_t ipc; 251 252 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 253 if ((ipc->pc_present & PCI_OVERRIDE_INTR_EVCNT) == 0) 254 continue; 255 return (*ipc->pc_ov->ov_intr_evcnt)(ipc->pc_ctx, pc, ih); 256 } 257 258 /* XXX for now, no evcnt parent reported */ 259 return NULL; 260 } 261 262 int 263 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 264 int attr, uint64_t data) 265 { 266 267 switch (attr) { 268 case PCI_INTR_MPSAFE: 269 if (data) { 270 *ih |= MPSAFE_MASK; 271 } else { 272 *ih &= ~MPSAFE_MASK; 273 } 274 /* XXX Set live if already mapped. */ 275 return 0; 276 default: 277 return ENODEV; 278 } 279 } 280 281 static int 282 pci_intr_find_intx_irq(pci_intr_handle_t ih, int *irq, struct pic **pic, 283 int *pin) 284 { 285 286 KASSERT(irq != NULL); 287 KASSERT(pic != NULL); 288 KASSERT(pin != NULL); 289 290 *pic = &i8259_pic; 291 *pin = *irq = APIC_IRQ_LEGACY_IRQ(ih); 292 293 #if NIOAPIC > 0 294 if (ih & APIC_INT_VIA_APIC) { 295 struct ioapic_softc *ioapic; 296 297 ioapic = ioapic_find(APIC_IRQ_APIC(ih)); 298 if (ioapic == NULL) 299 return ENOENT; 300 *pic = &ioapic->sc_pic; 301 *pin = APIC_IRQ_PIN(ih); 302 *irq = APIC_IRQ_LEGACY_IRQ(ih); 303 if (*irq < 0 || *irq >= NUM_LEGACY_IRQS) 304 *irq = -1; 305 } 306 #endif 307 308 return 0; 309 } 310 311 static void * 312 pci_intr_establish_xname_internal(pci_chipset_tag_t pc, pci_intr_handle_t ih, 313 int level, int (*func)(void *), void *arg, const char *xname) 314 { 315 int pin, irq; 316 struct pic *pic; 317 bool mpsafe; 318 pci_chipset_tag_t ipc; 319 320 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 321 if ((ipc->pc_present & PCI_OVERRIDE_INTR_ESTABLISH) == 0) 322 continue; 323 return (*ipc->pc_ov->ov_intr_establish)(ipc->pc_ctx, 324 pc, ih, level, func, arg); 325 } 326 327 328 #ifdef __HAVE_PCI_MSI_MSIX 329 if (INT_VIA_MSI(ih)) { 330 if (MSI_INT_IS_MSIX(ih)) 331 return x86_pci_msix_establish(pc, ih, level, func, arg, 332 xname); 333 else 334 return x86_pci_msi_establish(pc, ih, level, func, arg, 335 xname); 336 } 337 #endif 338 if (pci_intr_find_intx_irq(ih, &irq, &pic, &pin)) { 339 aprint_normal("%s: bad pic %d\n", __func__, 340 APIC_IRQ_APIC(ih)); 341 return NULL; 342 } 343 344 mpsafe = ((ih & MPSAFE_MASK) != 0); 345 346 return intr_establish_xname(irq, pic, pin, IST_LEVEL, level, func, arg, 347 mpsafe, xname); 348 } 349 350 void * 351 pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, 352 int level, int (*func)(void *), void *arg) 353 { 354 355 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, "unknown"); 356 } 357 358 void * 359 pci_intr_establish_xname(pci_chipset_tag_t pc, pci_intr_handle_t ih, 360 int level, int (*func)(void *), void *arg, const char *xname) 361 { 362 363 return pci_intr_establish_xname_internal(pc, ih, level, func, arg, xname); 364 } 365 366 367 void 368 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 369 { 370 pci_chipset_tag_t ipc; 371 372 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 373 if ((ipc->pc_present & PCI_OVERRIDE_INTR_DISESTABLISH) == 0) 374 continue; 375 (*ipc->pc_ov->ov_intr_disestablish)(ipc->pc_ctx, pc, cookie); 376 return; 377 } 378 379 /* MSI/MSI-X processing is switched in intr_disestablish(). */ 380 intr_disestablish(cookie); 381 } 382 383 #if NIOAPIC > 0 384 #ifdef __HAVE_PCI_MSI_MSIX 385 pci_intr_type_t 386 pci_intr_type(pci_chipset_tag_t pc, pci_intr_handle_t ih) 387 { 388 389 if (INT_VIA_MSI(ih)) { 390 if (MSI_INT_IS_MSIX(ih)) 391 return PCI_INTR_TYPE_MSIX; 392 else 393 return PCI_INTR_TYPE_MSI; 394 } else { 395 return PCI_INTR_TYPE_INTX; 396 } 397 } 398 399 static const char * 400 x86_pci_intx_create_intrid(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 401 size_t len) 402 { 403 #if !defined(XENPV) 404 int pin, irq; 405 struct pic *pic; 406 407 KASSERT(!INT_VIA_MSI(ih)); 408 409 pic = &i8259_pic; 410 pin = irq = APIC_IRQ_LEGACY_IRQ(ih); 411 412 if (pci_intr_find_intx_irq(ih, &irq, &pic, &pin)) { 413 aprint_normal("%s: bad pic %d\n", __func__, 414 APIC_IRQ_APIC(ih)); 415 return NULL; 416 } 417 418 return intr_create_intrid(irq, pic, pin, buf, len); 419 #else 420 return pci_intr_string(pc, ih, buf, len); 421 #endif /* !XENPV */ 422 } 423 424 static void 425 x86_pci_intx_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih) 426 { 427 char intrstr_buf[INTRIDBUF]; 428 const char *intrstr; 429 430 intrstr = pci_intr_string(NULL, *pih, intrstr_buf, sizeof(intrstr_buf)); 431 mutex_enter(&cpu_lock); 432 intr_free_io_intrsource(intrstr); 433 mutex_exit(&cpu_lock); 434 435 kmem_free(pih, sizeof(*pih)); 436 } 437 438 int 439 pci_intx_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **pih) 440 { 441 struct intrsource *isp; 442 pci_intr_handle_t *handle; 443 int error; 444 char intrstr_buf[INTRIDBUF]; 445 const char *intrstr; 446 447 handle = kmem_zalloc(sizeof(*handle), KM_SLEEP); 448 if (pci_intr_map(pa, handle) != 0) { 449 aprint_normal("cannot set up pci_intr_handle_t\n"); 450 error = EINVAL; 451 goto error; 452 } 453 454 /* 455 * must be the same intrstr as intr_establish_xname() 456 */ 457 intrstr = x86_pci_intx_create_intrid(pa->pa_pc, *handle, intrstr_buf, 458 sizeof(intrstr_buf)); 459 mutex_enter(&cpu_lock); 460 isp = intr_allocate_io_intrsource(intrstr); 461 mutex_exit(&cpu_lock); 462 if (isp == NULL) { 463 aprint_normal("can't allocate io_intersource\n"); 464 error = ENOMEM; 465 goto error; 466 } 467 468 *pih = handle; 469 return 0; 470 471 error: 472 kmem_free(handle, sizeof(*handle)); 473 return error; 474 } 475 476 /* 477 * Interrupt handler allocation utility. This function calls each allocation 478 * function as specified by arguments. 479 * Currently callee functions are pci_intx_alloc(), pci_msi_alloc_exact(), 480 * and pci_msix_alloc_exact(). 481 * pa : pci_attach_args 482 * ihps : interrupt handlers 483 * counts : The array of number of required interrupt handlers. 484 * It is overwritten by allocated the number of handlers. 485 * CAUTION: The size of counts[] must be PCI_INTR_TYPE_SIZE. 486 * max_type : "max" type of using interrupts. See below. 487 * e.g. 488 * If you want to use 5 MSI-X, 1 MSI, or INTx, you use "counts" as 489 * int counts[PCI_INTR_TYPE_SIZE]; 490 * counts[PCI_INTR_TYPE_MSIX] = 5; 491 * counts[PCI_INTR_TYPE_MSI] = 1; 492 * counts[PCI_INTR_TYPE_INTX] = 1; 493 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 494 * 495 * If you want to use hardware max number MSI-X or 1 MSI, 496 * and not to use INTx, you use "counts" as 497 * int counts[PCI_INTR_TYPE_SIZE]; 498 * counts[PCI_INTR_TYPE_MSIX] = -1; 499 * counts[PCI_INTR_TYPE_MSI] = 1; 500 * counts[PCI_INTR_TYPE_INTX] = 0; 501 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSIX); 502 * 503 * If you want to use 3 MSI or INTx, you can use "counts" as 504 * int counts[PCI_INTR_TYPE_SIZE]; 505 * counts[PCI_INTR_TYPE_MSI] = 3; 506 * counts[PCI_INTR_TYPE_INTX] = 1; 507 * error = pci_intr_alloc(pa, ihps, counts, PCI_INTR_TYPE_MSI); 508 * 509 * If you want to use 1 MSI or INTx (probably most general usage), 510 * you can simply use this API like 511 * below 512 * error = pci_intr_alloc(pa, ihps, NULL, 0); 513 * ^ ignored 514 */ 515 int 516 pci_intr_alloc(const struct pci_attach_args *pa, pci_intr_handle_t **ihps, 517 int *counts, pci_intr_type_t max_type) 518 { 519 int error; 520 int intx_count, msi_count, msix_count; 521 522 intx_count = msi_count = msix_count = 0; 523 if (counts == NULL) { /* simple pattern */ 524 msix_count = 1; 525 msi_count = 1; 526 intx_count = 1; 527 } else { 528 switch (max_type) { 529 case PCI_INTR_TYPE_MSIX: 530 msix_count = counts[PCI_INTR_TYPE_MSIX]; 531 /* FALLTHROUGH */ 532 case PCI_INTR_TYPE_MSI: 533 msi_count = counts[PCI_INTR_TYPE_MSI]; 534 /* FALLTHROUGH */ 535 case PCI_INTR_TYPE_INTX: 536 intx_count = counts[PCI_INTR_TYPE_INTX]; 537 break; 538 default: 539 return EINVAL; 540 } 541 } 542 543 if (counts != NULL) 544 memset(counts, 0, sizeof(counts[0]) * PCI_INTR_TYPE_SIZE); 545 error = EINVAL; 546 547 /* try MSI-X */ 548 if (msix_count == -1) /* use hardware max */ 549 msix_count = pci_msix_count(pa->pa_pc, pa->pa_tag); 550 if (msix_count > 0) { 551 error = pci_msix_alloc_exact(pa, ihps, msix_count); 552 if (error == 0) { 553 if (counts != NULL) 554 counts[PCI_INTR_TYPE_MSIX] = msix_count; 555 goto out; 556 } 557 } 558 559 /* try MSI */ 560 if (msi_count == -1) /* use hardware max */ 561 msi_count = pci_msi_count(pa->pa_pc, pa->pa_tag); 562 if (msi_count > 0) { 563 error = pci_msi_alloc_exact(pa, ihps, msi_count); 564 if (error == 0) { 565 if (counts != NULL) 566 counts[PCI_INTR_TYPE_MSI] = msi_count; 567 goto out; 568 } 569 } 570 571 /* try INTx */ 572 if (intx_count != 0) { /* The number of INTx is always 1. */ 573 error = pci_intx_alloc(pa, ihps); 574 if (error == 0) { 575 if (counts != NULL) 576 counts[PCI_INTR_TYPE_INTX] = 1; 577 } 578 } 579 580 out: 581 return error; 582 } 583 584 void 585 pci_intr_release(pci_chipset_tag_t pc, pci_intr_handle_t *pih, int count) 586 { 587 if (pih == NULL) 588 return; 589 590 if (INT_VIA_MSI(*pih)) { 591 if (MSI_INT_IS_MSIX(*pih)) 592 return x86_pci_msix_release(pc, pih, count); 593 else 594 return x86_pci_msi_release(pc, pih, count); 595 } else { 596 KASSERT(count == 1); 597 return x86_pci_intx_release(pc, pih); 598 } 599 600 } 601 #endif /* __HAVE_PCI_MSI_MSIX */ 602 #endif /* NIOAPIC > 0 */ 603
Indexes created Tue Sep 23 07:09:52 GMT 2025