| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni_dma.c | 164 u32 rb_cntl; local in function:cayman_dma_stop
171 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
172 rb_cntl &= ~DMA_RB_ENABLE;
173 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
176 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
177 rb_cntl &= ~DMA_RB_ENABLE;
178 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);
195 u32 rb_cntl, dma_cntl, ib_cntl; local in function:cayman_dma_resume
216 rb_cntl = rb_bufsz << 1;
218 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE
[all...] |
| radeon_r600_dma.c | 106 u32 rb_cntl = RREG32(DMA_RB_CNTL); local in function:r600_dma_stop
111 rb_cntl &= ~DMA_RB_ENABLE;
112 WREG32(DMA_RB_CNTL, rb_cntl);
128 u32 rb_cntl, dma_cntl, ib_cntl; local in function:r600_dma_resume
137 rb_cntl = rb_bufsz << 1;
139 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
141 WREG32(DMA_RB_CNTL, rb_cntl);
154 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
175 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
|
| radeon_cik_sdma.c | 257 u32 rb_cntl, reg_offset; local in function:cik_sdma_gfx_stop
269 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
270 rb_cntl &= ~SDMA_RB_ENABLE;
271 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
373 u32 rb_cntl, ib_cntl; local in function:cik_sdma_gfx_resume
394 rb_cntl = rb_bufsz << 1;
396 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
398 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
411 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
420 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE)
[all...] |
| radeon_ni.c | 1696 uint32_t rb_cntl; local in function:cayman_cp_resume
1701 rb_cntl = order_base_2(ring->ring_size / 8);
1702 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1704 rb_cntl |= BUF_SWAP_32BIT;
1706 WREG32(cp_rb_cntl[i], rb_cntl);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dma.c | 120 u32 rb_cntl; local in function:si_dma_stop
126 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]);
127 rb_cntl &= ~DMA_RB_ENABLE;
128 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
139 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; local in function:si_dma_start
151 rb_cntl = rb_bufsz << 1;
153 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
155 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl);
166 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
183 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE)
[all...] |
| amdgpu_cik_sdma.c | 315 u32 rb_cntl; local in function:cik_sdma_gfx_stop
323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
440 u32 rb_cntl, ib_cntl; local in function:cik_sdma_gfx_resume
468 rb_cntl = rb_bufsz << 1;
470 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
487 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
497 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK)
[all...] |
| amdgpu_sdma_v2_4.c | 349 u32 rb_cntl, ib_cntl; local in function:sdma_v2_4_gfx_stop
357 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
358 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
359 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
419 u32 rb_cntl, ib_cntl; local in function:sdma_v2_4_gfx_resume
445 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
448 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)
[all...] |
| amdgpu_sdma_v3_0.c | 523 u32 rb_cntl, ib_cntl; local in function:sdma_v3_0_gfx_stop
531 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
533 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
654 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v3_0_gfx_resume
683 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
684 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
686 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)
[all...] |
| amdgpu_sdma_v4_0.c | 916 u32 rb_cntl, ib_cntl; local in function:sdma_v4_0_gfx_stop
927 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
928 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
929 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
960 u32 rb_cntl, ib_cntl; local in function:sdma_v4_0_page_stop
973 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
974 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
976 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1093 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v4_0_gfx_resume
1183 u32 rb_cntl, ib_cntl, wptr_poll_cntl; local in function:sdma_v4_0_page_resume
[all...] |
| amdgpu_sdma_v5_0.c | 497 u32 rb_cntl, ib_cntl; local in function:sdma_v5_0_gfx_stop
505 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
507 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
619 u32 rb_cntl, ib_cntl; local in function:sdma_v5_0_gfx_resume
637 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
640 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)
[all...] |
