| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik_sdma.c | 180 u32 ref_and_mask; local in function:cik_sdma_hdp_flush_ring_emit
183 ref_and_mask = SDMA0;
185 ref_and_mask = SDMA1;
190 radeon_ring_write(ring, ref_and_mask); /* reference */
191 radeon_ring_write(ring, ref_and_mask); /* mask */
|
| radeon_cik.c | 3525 u32 ref_and_mask; local in function:cik_hdp_flush_cp_ring_emit
3533 ref_and_mask = CP2 << ring->pipe;
3536 ref_and_mask = CP6 << ring->pipe;
3543 ref_and_mask = CP0;
3553 radeon_ring_write(ring, ref_and_mask);
3554 radeon_ring_write(ring, ref_and_mask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_cik_sdma.c | 256 u32 ref_and_mask; local in function:cik_sdma_ring_emit_hdp_flush
259 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
261 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
266 amdgpu_ring_write(ring, ref_and_mask); /* reference */
267 amdgpu_ring_write(ring, ref_and_mask); /* mask */
|
| amdgpu_sdma_v2_4.c | 286 u32 ref_and_mask = 0; local in function:sdma_v2_4_ring_emit_hdp_flush
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
298 amdgpu_ring_write(ring, ref_and_mask); /* reference */
299 amdgpu_ring_write(ring, ref_and_mask); /* mask */
|
| amdgpu_sdma_v3_0.c | 460 u32 ref_and_mask = 0; local in function:sdma_v3_0_ring_emit_hdp_flush
463 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
465 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
472 amdgpu_ring_write(ring, ref_and_mask); /* reference */
473 amdgpu_ring_write(ring, ref_and_mask); /* mask */
|
| amdgpu_sdma_v4_0.c | 856 u32 ref_and_mask = 0; local in function:sdma_v4_0_ring_emit_hdp_flush
859 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
864 ref_and_mask, ref_and_mask, 10);
|
| amdgpu_sdma_v5_0.c | 422 u32 ref_and_mask = 0; local in function:sdma_v5_0_ring_emit_hdp_flush
426 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
428 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
435 amdgpu_ring_write(ring, ref_and_mask); /* reference */
436 amdgpu_ring_write(ring, ref_and_mask); /* mask */
|
| amdgpu_gfx_v10_0.c | 4382 u32 ref_and_mask, reg_mem_engine; local in function:gfx_v10_0_ring_emit_hdp_flush
4388 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4391 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4398 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4405 ref_and_mask, ref_and_mask, 0x20);
|
| amdgpu_gfx_v7_0.c | 2141 u32 ref_and_mask; local in function:gfx_v7_0_ring_emit_hdp_flush
2147 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2150 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2156 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2165 amdgpu_ring_write(ring, ref_and_mask);
2166 amdgpu_ring_write(ring, ref_and_mask);
|
| amdgpu_gfx_v8_0.c | 6045 u32 ref_and_mask, reg_mem_engine; local in function:gfx_v8_0_ring_emit_hdp_flush
6051 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6054 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6061 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6071 amdgpu_ring_write(ring, ref_and_mask);
6072 amdgpu_ring_write(ring, ref_and_mask);
|
| amdgpu_gfx_v9_0.c | 4884 u32 ref_and_mask, reg_mem_engine; local in function:gfx_v9_0_ring_emit_hdp_flush
4890 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
4893 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
4900 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
4907 ref_and_mask, ref_and_mask, 0x20);
|
