| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/basics/ |
| amdgpu_conversion.c | 100 uint32_t reg_value = local in function:convert_float_matrix
109 matrix[i] = (uint16_t)reg_value;
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v9_4.c | 864 uint32_t reg_value; local in function:gfx_v9_4_query_ras_error_count
879 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
881 if (reg_value)
884 j, k, reg_value, &sec_count,
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| soc15.h | 52 uint32_t reg_value; member in struct:soc15_reg_entry
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| amdgpu_mmhub_v1_0.c | 738 uint32_t reg_value; local in function:mmhub_v1_0_query_ras_error_count
744 reg_value =
746 if (reg_value)
748 reg_value, &sec_count, &ded_count);
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| amdgpu_mmhub_v9_4.c | 1587 uint32_t reg_value; local in function:mmhub_v9_4_query_ras_error_count
1593 reg_value =
1595 if (reg_value)
1597 reg_value, &sec_count, &ded_count);
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| mmsch_v1_0.h | 77 uint32_t reg_value; member in struct:mmsch_v1_0_cmd_direct_write
98 uint32_t reg_value; member in struct:mmsch_v1_0_cmd_indirect_write
107 direct_wt->reg_value = value;
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| amdgpu_sdma_v4_0.c | 2565 uint32_t reg_value = 0; local in function:sdma_v4_0_query_ras_error_count
2567 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2569 if (reg_value)
2570 sdma_v4_0_get_ras_error_count(reg_value,
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| psp_gfx_if.h | 94 uint32_t reg_value; /* Value to be set to the IH_RB_CNTL... register*/ member in struct:psp_gfx_cmd_gbr_ih_reg
273 uint32_t reg_value; member in struct:psp_gfx_cmd_reg_prog
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| amdgpu_gfx_v9_0.c | 4259 ib.ptr[ib.length_dw++] = vgpr_init_regs[i].reg_value;
4287 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value;
4315 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value;
6389 uint32_t reg_value; local in function:gfx_v9_0_query_ras_error_count
6403 reg_value =
6405 if (reg_value)
6407 j, k, reg_value,
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| /src/usr.bin/scmdctl/ |
| scmdctl.c | 163 int8_t reg_value; local in function:main
302 reg_value = (int8_t)strtoi(argv[5], NULL, 0, -127, 127, &error);
304 err(EXIT_FAILURE,"Bad conversion for set motor for reg_value: %s", argv[5]);
310 error = common_set_motor(&func_block, fd, debug, (int)module, motor, reg_value);
426 reg_value = (int8_t)strtoi(argv[4], NULL, 0, 0, 0xff, &error);
428 err(EXIT_FAILURE,"Bad conversion for write register for reg_value: %s", argv[4]);
430 error = uart_write_register(fd,debug,module,reg,reg_value);
432 error = i2cspi_write_register(fd,debug,module,reg,reg_value);
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 1111 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); local in function:smu10_thermal_get_temperature
1113 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
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| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| intel_uncore.c | 2032 u32 uninitialized_var(reg_value);
2033 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value)
2047 *out_value = reg_value;
2082 u32 reg_value; local in function:__intel_wait_for_register
2092 fast_timeout_us, 0, ®_value);
2098 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore,
2100 (reg_value & mask) == value,
2104 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2107 *out_value = reg_value;
[all...] |
| i915_drv.c | 2417 u32 reg_value; local in function:vlv_wait_for_pw_status
2427 ret = wait_for(((reg_value =
2432 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
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