1 /* $NetBSD: amdgpu_mmhub_v9_4.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_mmhub_v9_4.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $"); 27 28 #include "amdgpu.h" 29 #include "amdgpu_ras.h" 30 #include "mmhub_v9_4.h" 31 32 #include "mmhub/mmhub_9_4_1_offset.h" 33 #include "mmhub/mmhub_9_4_1_sh_mask.h" 34 #include "mmhub/mmhub_9_4_1_default.h" 35 #include "athub/athub_1_0_offset.h" 36 #include "athub/athub_1_0_sh_mask.h" 37 #include "vega10_enum.h" 38 #include "soc15.h" 39 #include "soc15_common.h" 40 41 #define MMHUB_NUM_INSTANCES 2 42 #define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000 43 44 u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev) 45 { 46 /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */ 47 u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); 48 u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP); 49 50 base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 51 base <<= 24; 52 53 top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 54 top <<= 24; 55 56 adev->gmc.fb_start = base; 57 adev->gmc.fb_end = top; 58 59 return base; 60 } 61 62 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid, 63 uint32_t vmid, uint64_t value) 64 { 65 /* two registers distance between mmVML2VC0_VM_CONTEXT0_* to 66 * mmVML2VC0_VM_CONTEXT1_* 67 */ 68 int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 69 - mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 70 71 WREG32_SOC15_OFFSET(MMHUB, 0, 72 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 73 dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 74 lower_32_bits(value)); 75 76 WREG32_SOC15_OFFSET(MMHUB, 0, 77 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 78 dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 79 upper_32_bits(value)); 80 81 } 82 83 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev, 84 int hubid) 85 { 86 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 87 88 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base); 89 90 WREG32_SOC15_OFFSET(MMHUB, 0, 91 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 92 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 93 (u32)(adev->gmc.gart_start >> 12)); 94 WREG32_SOC15_OFFSET(MMHUB, 0, 95 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 96 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 97 (u32)(adev->gmc.gart_start >> 44)); 98 99 WREG32_SOC15_OFFSET(MMHUB, 0, 100 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 101 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 102 (u32)(adev->gmc.gart_end >> 12)); 103 WREG32_SOC15_OFFSET(MMHUB, 0, 104 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 105 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 106 (u32)(adev->gmc.gart_end >> 44)); 107 } 108 109 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 110 uint64_t page_table_base) 111 { 112 int i; 113 114 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) 115 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid, 116 page_table_base); 117 } 118 119 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev, 120 int hubid) 121 { 122 uint64_t value; 123 uint32_t tmp; 124 125 /* Program the AGP BAR */ 126 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE, 127 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 128 0); 129 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP, 130 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 131 adev->gmc.agp_end >> 24); 132 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT, 133 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 134 adev->gmc.agp_start >> 24); 135 136 if (!amdgpu_sriov_vf(adev)) { 137 /* Program the system aperture low logical page number. */ 138 WREG32_SOC15_OFFSET( 139 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR, 140 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 141 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 142 WREG32_SOC15_OFFSET( 143 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 144 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 145 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 146 147 /* Set default page address. */ 148 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 149 adev->vm_manager.vram_base_offset; 150 WREG32_SOC15_OFFSET( 151 MMHUB, 0, 152 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 153 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 154 (u32)(value >> 12)); 155 WREG32_SOC15_OFFSET( 156 MMHUB, 0, 157 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 158 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 159 (u32)(value >> 44)); 160 161 /* Program "protection fault". */ 162 WREG32_SOC15_OFFSET( 163 MMHUB, 0, 164 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 165 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 166 (u32)(adev->dummy_page_addr >> 12)); 167 WREG32_SOC15_OFFSET( 168 MMHUB, 0, 169 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 170 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 171 (u32)((u64)adev->dummy_page_addr >> 44)); 172 173 tmp = RREG32_SOC15_OFFSET( 174 MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 175 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 176 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 177 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 178 WREG32_SOC15_OFFSET(MMHUB, 0, 179 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 180 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 181 tmp); 182 } 183 } 184 185 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid) 186 { 187 uint32_t tmp; 188 189 /* Setup TLB control */ 190 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 191 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 192 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 193 194 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 195 ENABLE_L1_TLB, 1); 196 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 197 SYSTEM_ACCESS_MODE, 3); 198 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 199 ENABLE_ADVANCED_DRIVER_MODEL, 1); 200 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 201 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 202 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 203 ECO_BITS, 0); 204 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 205 MTYPE, MTYPE_UC);/* XXX for emulation. */ 206 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 207 ATC_EN, 1); 208 209 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 210 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 211 } 212 213 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid) 214 { 215 uint32_t tmp; 216 217 /* Setup L2 cache */ 218 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 219 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 220 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 221 ENABLE_L2_CACHE, 1); 222 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 223 ENABLE_L2_FRAGMENT_PROCESSING, 1); 224 /* XXX for emulation, Refer to closed source code.*/ 225 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 226 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 227 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 228 PDE_FAULT_CLASSIFICATION, 0); 229 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 230 CONTEXT1_IDENTITY_ACCESS_MODE, 1); 231 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 232 IDENTITY_MODE_FRAGMENT_SIZE, 0); 233 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 234 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 235 236 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 237 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 238 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 239 INVALIDATE_ALL_L1_TLBS, 1); 240 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 241 INVALIDATE_L2_CACHE, 1); 242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 243 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 244 245 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT; 246 if (adev->gmc.translate_further) { 247 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12); 248 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 249 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 250 } else { 251 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9); 252 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 253 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 254 } 255 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 256 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 257 258 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT; 259 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 260 VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 261 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 262 VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 263 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4, 264 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 265 } 266 267 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev, 268 int hubid) 269 { 270 uint32_t tmp; 271 272 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 273 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 274 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 275 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 276 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, 277 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 278 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 279 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 280 } 281 282 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev, 283 int hubid) 284 { 285 WREG32_SOC15_OFFSET(MMHUB, 0, 286 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 287 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF); 288 WREG32_SOC15_OFFSET(MMHUB, 0, 289 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 290 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F); 291 292 WREG32_SOC15_OFFSET(MMHUB, 0, 293 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 294 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 295 WREG32_SOC15_OFFSET(MMHUB, 0, 296 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 297 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 298 299 WREG32_SOC15_OFFSET(MMHUB, 0, 300 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 301 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 302 WREG32_SOC15_OFFSET(MMHUB, 0, 303 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 304 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 305 } 306 307 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid) 308 { 309 uint32_t tmp; 310 int i; 311 312 for (i = 0; i <= 14; i++) { 313 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 314 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i); 315 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 316 ENABLE_CONTEXT, 1); 317 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 318 PAGE_TABLE_DEPTH, 319 adev->vm_manager.num_level); 320 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 321 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 322 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 323 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 324 1); 325 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 326 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 327 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 328 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 329 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 330 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 331 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 332 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 333 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 334 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 335 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 336 PAGE_TABLE_BLOCK_SIZE, 337 adev->vm_manager.block_size - 9); 338 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 339 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 340 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 341 !amdgpu_noretry); 342 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 343 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i, 344 tmp); 345 WREG32_SOC15_OFFSET(MMHUB, 0, 346 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 347 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); 348 WREG32_SOC15_OFFSET(MMHUB, 0, 349 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 350 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0); 351 WREG32_SOC15_OFFSET(MMHUB, 0, 352 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 353 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 354 lower_32_bits(adev->vm_manager.max_pfn - 1)); 355 WREG32_SOC15_OFFSET(MMHUB, 0, 356 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 357 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 358 upper_32_bits(adev->vm_manager.max_pfn - 1)); 359 } 360 } 361 362 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev, 363 int hubid) 364 { 365 unsigned i; 366 367 for (i = 0; i < 18; ++i) { 368 WREG32_SOC15_OFFSET(MMHUB, 0, 369 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 370 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, 371 0xffffffff); 372 WREG32_SOC15_OFFSET(MMHUB, 0, 373 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 374 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i, 375 0x1f); 376 } 377 } 378 379 int mmhub_v9_4_gart_enable(struct amdgpu_device *adev) 380 { 381 int i; 382 383 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 384 /* GART Enable. */ 385 mmhub_v9_4_init_gart_aperture_regs(adev, i); 386 mmhub_v9_4_init_system_aperture_regs(adev, i); 387 mmhub_v9_4_init_tlb_regs(adev, i); 388 if (!amdgpu_sriov_vf(adev)) 389 mmhub_v9_4_init_cache_regs(adev, i); 390 391 mmhub_v9_4_enable_system_domain(adev, i); 392 if (!amdgpu_sriov_vf(adev)) 393 mmhub_v9_4_disable_identity_aperture(adev, i); 394 mmhub_v9_4_setup_vmid_config(adev, i); 395 mmhub_v9_4_program_invalidation(adev, i); 396 } 397 398 return 0; 399 } 400 401 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev) 402 { 403 u32 tmp; 404 u32 i, j; 405 406 for (j = 0; j < MMHUB_NUM_INSTANCES; j++) { 407 /* Disable all tables */ 408 for (i = 0; i < 16; i++) 409 WREG32_SOC15_OFFSET(MMHUB, 0, 410 mmVML2VC0_VM_CONTEXT0_CNTL, 411 j * MMHUB_INSTANCE_REGISTER_OFFSET + 412 i, 0); 413 414 /* Setup TLB control */ 415 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 416 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 417 j * MMHUB_INSTANCE_REGISTER_OFFSET); 418 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 419 ENABLE_L1_TLB, 0); 420 tmp = REG_SET_FIELD(tmp, 421 VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 422 ENABLE_ADVANCED_DRIVER_MODEL, 0); 423 WREG32_SOC15_OFFSET(MMHUB, 0, 424 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 425 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 426 427 /* Setup L2 cache */ 428 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 429 j * MMHUB_INSTANCE_REGISTER_OFFSET); 430 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 431 ENABLE_L2_CACHE, 0); 432 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 433 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 434 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 435 j * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 436 } 437 } 438 439 /** 440 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling 441 * 442 * @adev: amdgpu_device pointer 443 * @value: true redirects VM faults to the default page 444 */ 445 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value) 446 { 447 u32 tmp; 448 int i; 449 450 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 451 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 452 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 453 i * MMHUB_INSTANCE_REGISTER_OFFSET); 454 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 455 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 456 value); 457 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 458 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 459 value); 460 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 461 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, 462 value); 463 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 464 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, 465 value); 466 tmp = REG_SET_FIELD(tmp, 467 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 468 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 469 value); 470 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 471 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, 472 value); 473 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 474 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 475 value); 476 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 477 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 478 value); 479 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 480 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 481 value); 482 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 483 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 484 value); 485 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 486 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 487 value); 488 if (!value) { 489 tmp = REG_SET_FIELD(tmp, 490 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 491 CRASH_ON_NO_RETRY_FAULT, 1); 492 tmp = REG_SET_FIELD(tmp, 493 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 494 CRASH_ON_RETRY_FAULT, 1); 495 } 496 497 WREG32_SOC15_OFFSET(MMHUB, 0, 498 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 499 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 500 } 501 } 502 503 void mmhub_v9_4_init(struct amdgpu_device *adev) 504 { 505 struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = 506 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]}; 507 int i; 508 509 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 510 hub[i]->ctx0_ptb_addr_lo32 = 511 SOC15_REG_OFFSET(MMHUB, 0, 512 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + 513 i * MMHUB_INSTANCE_REGISTER_OFFSET; 514 hub[i]->ctx0_ptb_addr_hi32 = 515 SOC15_REG_OFFSET(MMHUB, 0, 516 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + 517 i * MMHUB_INSTANCE_REGISTER_OFFSET; 518 hub[i]->vm_inv_eng0_sem = 519 SOC15_REG_OFFSET(MMHUB, 0, 520 mmVML2VC0_VM_INVALIDATE_ENG0_SEM) + 521 i * MMHUB_INSTANCE_REGISTER_OFFSET; 522 hub[i]->vm_inv_eng0_req = 523 SOC15_REG_OFFSET(MMHUB, 0, 524 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) + 525 i * MMHUB_INSTANCE_REGISTER_OFFSET; 526 hub[i]->vm_inv_eng0_ack = 527 SOC15_REG_OFFSET(MMHUB, 0, 528 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) + 529 i * MMHUB_INSTANCE_REGISTER_OFFSET; 530 hub[i]->vm_context0_cntl = 531 SOC15_REG_OFFSET(MMHUB, 0, 532 mmVML2VC0_VM_CONTEXT0_CNTL) + 533 i * MMHUB_INSTANCE_REGISTER_OFFSET; 534 hub[i]->vm_l2_pro_fault_status = 535 SOC15_REG_OFFSET(MMHUB, 0, 536 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) + 537 i * MMHUB_INSTANCE_REGISTER_OFFSET; 538 hub[i]->vm_l2_pro_fault_cntl = 539 SOC15_REG_OFFSET(MMHUB, 0, 540 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) + 541 i * MMHUB_INSTANCE_REGISTER_OFFSET; 542 } 543 } 544 545 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 546 bool enable) 547 { 548 uint32_t def, data, def1, data1; 549 int i, j; 550 int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2; 551 552 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 553 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 554 mmATCL2_0_ATC_L2_MISC_CG, 555 i * MMHUB_INSTANCE_REGISTER_OFFSET); 556 557 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 558 data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 559 else 560 data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 561 562 if (def != data) 563 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 564 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 565 566 for (j = 0; j < 5; j++) { 567 def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0, 568 mmDAGB0_CNTL_MISC2, 569 i * MMHUB_INSTANCE_REGISTER_OFFSET + 570 j * dist); 571 if (enable && 572 (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 573 data1 &= 574 ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 575 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 576 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 577 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 578 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 579 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 580 } else { 581 data1 |= 582 (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 583 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 584 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 585 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 586 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 587 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 588 } 589 590 if (def1 != data1) 591 WREG32_SOC15_OFFSET(MMHUB, 0, 592 mmDAGB0_CNTL_MISC2, 593 i * MMHUB_INSTANCE_REGISTER_OFFSET + 594 j * dist, data1); 595 596 if (i == 1 && j == 3) 597 break; 598 } 599 } 600 } 601 602 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 603 bool enable) 604 { 605 uint32_t def, data; 606 int i; 607 608 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 609 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 610 mmATCL2_0_ATC_L2_MISC_CG, 611 i * MMHUB_INSTANCE_REGISTER_OFFSET); 612 613 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 614 data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 615 else 616 data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 617 618 if (def != data) 619 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 620 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 621 } 622 } 623 624 int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev, 625 enum amd_clockgating_state state) 626 { 627 if (amdgpu_sriov_vf(adev)) 628 return 0; 629 630 switch (adev->asic_type) { 631 case CHIP_ARCTURUS: 632 mmhub_v9_4_update_medium_grain_clock_gating(adev, 633 state == AMD_CG_STATE_GATE); 634 mmhub_v9_4_update_medium_grain_light_sleep(adev, 635 state == AMD_CG_STATE_GATE); 636 break; 637 default: 638 break; 639 } 640 641 return 0; 642 } 643 644 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags) 645 { 646 int data, data1; 647 648 if (amdgpu_sriov_vf(adev)) 649 *flags = 0; 650 651 /* AMD_CG_SUPPORT_MC_MGCG */ 652 data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 653 654 data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 655 656 if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) && 657 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 658 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 659 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 660 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 661 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 662 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 663 *flags |= AMD_CG_SUPPORT_MC_MGCG; 664 665 /* AMD_CG_SUPPORT_MC_LS */ 666 if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 667 *flags |= AMD_CG_SUPPORT_MC_LS; 668 } 669 670 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = { 671 /* MMHUB Range 0 */ 672 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 673 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 674 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 675 }, 676 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 677 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 678 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 679 }, 680 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 681 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 682 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 683 }, 684 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 685 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 686 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT), 687 }, 688 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 689 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 690 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT), 691 }, 692 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 693 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 694 0, 0, 695 }, 696 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 697 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 698 0, 0, 699 }, 700 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 701 SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT), 702 0, 0, 703 }, 704 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 705 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 706 0, 0, 707 }, 708 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 709 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 710 0, 0, 711 }, 712 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 713 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 714 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 715 }, 716 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 717 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 718 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 719 }, 720 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 721 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 722 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 723 }, 724 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 725 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 726 0, 0, 727 }, 728 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 729 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 730 0, 0, 731 }, 732 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 733 0, 0, 734 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 735 }, 736 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 737 0, 0, 738 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 739 }, 740 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 741 0, 0, 742 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 743 }, 744 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 745 0, 0, 746 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 747 }, 748 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 749 0, 0, 750 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 751 }, 752 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 753 0, 0, 754 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 755 }, 756 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 757 0, 0, 758 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 759 }, 760 { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 761 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), 762 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), 763 }, 764 { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 765 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT), 766 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT), 767 }, 768 { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 769 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT), 770 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT), 771 }, 772 { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 773 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT), 774 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT), 775 }, 776 777 /* MMHUB Range 1 */ 778 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 779 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 780 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 781 }, 782 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 783 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 784 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 785 }, 786 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 787 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 788 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 789 }, 790 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 791 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 792 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT), 793 }, 794 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 795 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 796 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT), 797 }, 798 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 799 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 800 0, 0, 801 }, 802 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 803 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 804 0, 0, 805 }, 806 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 807 SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT), 808 0, 0, 809 }, 810 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 811 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 812 0, 0, 813 }, 814 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 815 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 816 0, 0, 817 }, 818 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 819 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 820 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 821 }, 822 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 823 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 824 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 825 }, 826 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 827 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 828 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 829 }, 830 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 831 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 832 0, 0, 833 }, 834 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 835 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 836 0, 0, 837 }, 838 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 839 0, 0, 840 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 841 }, 842 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 843 0, 0, 844 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 845 }, 846 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 847 0, 0, 848 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 849 }, 850 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 851 0, 0, 852 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 853 }, 854 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 855 0, 0, 856 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 857 }, 858 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 859 0, 0, 860 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 861 }, 862 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 863 0, 0, 864 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 865 }, 866 { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 867 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT), 868 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT), 869 }, 870 { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 871 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT), 872 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT), 873 }, 874 { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 875 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT), 876 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT), 877 }, 878 { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 879 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT), 880 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT), 881 }, 882 883 /* MMHAB Range 2*/ 884 { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 885 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 886 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 887 }, 888 { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 889 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 890 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 891 }, 892 { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 893 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 894 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 895 }, 896 { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 897 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 898 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT), 899 }, 900 { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 901 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 902 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT), 903 }, 904 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 905 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 906 0, 0, 907 }, 908 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 909 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 910 0, 0, 911 }, 912 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 913 SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT), 914 0, 0, 915 }, 916 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 917 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 918 0, 0, 919 }, 920 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 921 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 922 0, 0, 923 }, 924 { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 925 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 926 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 927 }, 928 { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 929 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 930 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 931 }, 932 { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 933 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 934 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 935 }, 936 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 937 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 938 0, 0, 939 }, 940 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 941 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 942 0, 0, 943 }, 944 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 945 0, 0, 946 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 947 }, 948 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 949 0, 0, 950 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 951 }, 952 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 953 0, 0, 954 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 955 }, 956 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 957 0, 0, 958 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 959 }, 960 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 961 0, 0, 962 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 963 }, 964 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 965 0, 0, 966 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 967 }, 968 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 969 0, 0, 970 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 971 }, 972 { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 973 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT), 974 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT), 975 }, 976 { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 977 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT), 978 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT), 979 }, 980 { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 981 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT), 982 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT), 983 }, 984 { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 985 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT), 986 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT), 987 }, 988 989 /* MMHUB Rang 3 */ 990 { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 991 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 992 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 993 }, 994 { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 995 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 996 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 997 }, 998 { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 999 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1000 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1001 }, 1002 { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1003 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1004 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1005 }, 1006 { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1007 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1008 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1009 }, 1010 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1011 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1012 0, 0, 1013 }, 1014 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1015 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1016 0, 0, 1017 }, 1018 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1019 SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1020 0, 0, 1021 }, 1022 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1023 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1024 0, 0, 1025 }, 1026 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1027 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1028 0, 0, 1029 }, 1030 { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1031 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1032 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1033 }, 1034 { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1035 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1036 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1037 }, 1038 { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1039 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1040 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1041 }, 1042 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1043 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1044 0, 0, 1045 }, 1046 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1047 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1048 0, 0, 1049 }, 1050 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1051 0, 0, 1052 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1053 }, 1054 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1055 0, 0, 1056 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1057 }, 1058 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1059 0, 0, 1060 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1061 }, 1062 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1063 0, 0, 1064 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1065 }, 1066 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1067 0, 0, 1068 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1069 }, 1070 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1071 0, 0, 1072 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1073 }, 1074 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1075 0, 0, 1076 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1077 }, 1078 { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1079 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1080 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1081 }, 1082 { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1083 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1084 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1085 }, 1086 { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1087 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1088 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1089 }, 1090 { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1091 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1092 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1093 }, 1094 1095 /* MMHUB Range 4 */ 1096 { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1097 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1098 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1099 }, 1100 { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1101 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1102 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1103 }, 1104 { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1105 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1106 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1107 }, 1108 { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1109 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1110 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1111 }, 1112 { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1113 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1114 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1115 }, 1116 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1117 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1118 0, 0, 1119 }, 1120 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1121 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1122 0, 0, 1123 }, 1124 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1125 SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1126 0, 0, 1127 }, 1128 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1129 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1130 0, 0, 1131 }, 1132 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1133 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1134 0, 0, 1135 }, 1136 { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1137 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1138 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1139 }, 1140 { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1141 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1142 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1143 }, 1144 { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1145 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1146 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1147 }, 1148 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1149 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1150 0, 0, 1151 }, 1152 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1153 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1154 0, 0, 1155 }, 1156 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1157 0, 0, 1158 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1159 }, 1160 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1161 0, 0, 1162 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1163 }, 1164 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1165 0, 0, 1166 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1167 }, 1168 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1169 0, 0, 1170 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1171 }, 1172 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1173 0, 0, 1174 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1175 }, 1176 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1177 0, 0, 1178 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1179 }, 1180 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1181 0, 0, 1182 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1183 }, 1184 { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1185 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1186 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1187 }, 1188 { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1189 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1190 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1191 }, 1192 { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1193 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1194 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1195 }, 1196 { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1197 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1198 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1199 }, 1200 1201 /* MMHUAB Range 5 */ 1202 { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1203 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1204 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1205 }, 1206 { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1207 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1208 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1209 }, 1210 { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1211 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1212 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1213 }, 1214 { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1215 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1216 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1217 }, 1218 { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1219 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1220 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1221 }, 1222 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1223 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1224 0, 0, 1225 }, 1226 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1227 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1228 0, 0, 1229 }, 1230 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1231 SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1232 0, 0, 1233 }, 1234 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1235 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1236 0, 0, 1237 }, 1238 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1239 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1240 0, 0, 1241 }, 1242 { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1243 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1244 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1245 }, 1246 { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1247 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1248 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1249 }, 1250 { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1251 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1252 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1253 }, 1254 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1255 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1256 0, 0, 1257 }, 1258 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1259 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1260 0, 0, 1261 }, 1262 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1263 0, 0, 1264 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1265 }, 1266 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1267 0, 0, 1268 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1269 }, 1270 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1271 0, 0, 1272 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1273 }, 1274 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1275 0, 0, 1276 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1277 }, 1278 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1279 0, 0, 1280 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1281 }, 1282 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1283 0, 0, 1284 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1285 }, 1286 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1287 0, 0, 1288 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1289 }, 1290 { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1291 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1292 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1293 }, 1294 { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1295 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1296 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1297 }, 1298 { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1299 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1300 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1301 }, 1302 { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1303 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1304 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1305 }, 1306 1307 /* MMHUB Range 6 */ 1308 { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1309 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1310 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1311 }, 1312 { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1313 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1314 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1315 }, 1316 { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1317 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1318 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1319 }, 1320 { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1321 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1322 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1323 }, 1324 { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1325 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1326 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1327 }, 1328 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1329 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1330 0, 0, 1331 }, 1332 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1333 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1334 0, 0, 1335 }, 1336 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1337 SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1338 0, 0, 1339 }, 1340 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1341 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1342 0, 0, 1343 }, 1344 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1345 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1346 0, 0, 1347 }, 1348 { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1349 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1350 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1351 }, 1352 { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1353 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1354 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1355 }, 1356 { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1357 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1358 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1359 }, 1360 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1361 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1362 0, 0, 1363 }, 1364 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1365 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1366 0, 0, 1367 }, 1368 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1369 0, 0, 1370 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1371 }, 1372 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1373 0, 0, 1374 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1375 }, 1376 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1377 0, 0, 1378 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1379 }, 1380 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1381 0, 0, 1382 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1383 }, 1384 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1385 0, 0, 1386 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1387 }, 1388 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1389 0, 0, 1390 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1391 }, 1392 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1393 0, 0, 1394 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1395 }, 1396 { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1397 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1398 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1399 }, 1400 { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1401 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1402 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1403 }, 1404 { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1405 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1406 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1407 }, 1408 { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1409 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1410 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1411 }, 1412 1413 /* MMHUB Range 7*/ 1414 { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1415 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1416 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1417 }, 1418 { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1419 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1420 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1421 }, 1422 { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1423 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1424 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1425 }, 1426 { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1427 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1428 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1429 }, 1430 { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1431 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1432 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1433 }, 1434 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1435 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1436 0, 0, 1437 }, 1438 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1439 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1440 0, 0, 1441 }, 1442 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1443 SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1444 0, 0, 1445 }, 1446 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1447 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1448 0, 0, 1449 }, 1450 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1451 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1452 0, 0, 1453 }, 1454 { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1455 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1456 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1457 }, 1458 { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1459 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1460 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1461 }, 1462 { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1463 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1464 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1465 }, 1466 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1467 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1468 0, 0, 1469 }, 1470 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1471 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1472 0, 0, 1473 }, 1474 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1475 0, 0, 1476 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1477 }, 1478 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1479 0, 0, 1480 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1481 }, 1482 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1483 0, 0, 1484 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1485 }, 1486 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1487 0, 0, 1488 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1489 }, 1490 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1491 0, 0, 1492 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1493 }, 1494 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1495 0, 0, 1496 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1497 }, 1498 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1499 0, 0, 1500 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1501 }, 1502 { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1503 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1504 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1505 }, 1506 { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1507 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1508 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1509 }, 1510 { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1511 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1512 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1513 }, 1514 { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1515 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1516 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1517 } 1518 }; 1519 1520 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = { 1521 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 }, 1522 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 }, 1523 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 }, 1524 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 }, 1525 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 }, 1526 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 }, 1527 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 }, 1528 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 }, 1529 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 }, 1530 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 }, 1531 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 }, 1532 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 }, 1533 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 }, 1534 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 }, 1535 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 }, 1536 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 }, 1537 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 }, 1538 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 }, 1539 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 }, 1540 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 }, 1541 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 }, 1542 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 }, 1543 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 }, 1544 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 }, 1545 }; 1546 1547 static int mmhub_v9_4_get_ras_error_count(const struct soc15_reg_entry *reg, 1548 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) 1549 { 1550 uint32_t i; 1551 uint32_t sec_cnt, ded_cnt; 1552 1553 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) { 1554 if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset) 1555 continue; 1556 1557 sec_cnt = (value & 1558 mmhub_v9_4_ras_fields[i].sec_count_mask) >> 1559 mmhub_v9_4_ras_fields[i].sec_count_shift; 1560 if (sec_cnt) { 1561 DRM_INFO("MMHUB SubBlock %s, SEC %d\n", 1562 mmhub_v9_4_ras_fields[i].name, 1563 sec_cnt); 1564 *sec_count += sec_cnt; 1565 } 1566 1567 ded_cnt = (value & 1568 mmhub_v9_4_ras_fields[i].ded_count_mask) >> 1569 mmhub_v9_4_ras_fields[i].ded_count_shift; 1570 if (ded_cnt) { 1571 DRM_INFO("MMHUB SubBlock %s, DED %d\n", 1572 mmhub_v9_4_ras_fields[i].name, 1573 ded_cnt); 1574 *ded_count += ded_cnt; 1575 } 1576 } 1577 1578 return 0; 1579 } 1580 1581 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev, 1582 void *ras_error_status) 1583 { 1584 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1585 uint32_t sec_count = 0, ded_count = 0; 1586 uint32_t i; 1587 uint32_t reg_value; 1588 1589 err_data->ue_count = 0; 1590 err_data->ce_count = 0; 1591 1592 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) { 1593 reg_value = 1594 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); 1595 if (reg_value) 1596 mmhub_v9_4_get_ras_error_count(&mmhub_v9_4_edc_cnt_regs[i], 1597 reg_value, &sec_count, &ded_count); 1598 } 1599 1600 err_data->ce_count += sec_count; 1601 err_data->ue_count += ded_count; 1602 } 1603 1604 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = { 1605 .ras_late_init = amdgpu_mmhub_ras_late_init, 1606 .query_ras_error_count = mmhub_v9_4_query_ras_error_count, 1607 }; 1608
Indexes created Sun Sep 21 19:09:51 GMT 2025