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    Searched defs:regval (Results 1 - 25 of 91) sorted by relevancy

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  /src/sys/arch/netwinder/pci/
pci_machdep.c 17 pcireg_t regval; local
71 regval = pci_conf_read(pba->pba_pc, tag, 0x40);
72 regval &= 0xff00ff00;
73 regval |= 0x00000022;
74 pci_conf_write(pba->pba_pc, tag, 0x40, regval);
76 regval = pci_conf_read(pba->pba_pc, tag, 0x80);
77 regval &= 0x0000ff00;
78 regval |= 0xe0010002;
79 pci_conf_write(pba->pba_pc, tag, 0x80, regval);
91 regval = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG)
    [all...]
  /src/sys/arch/mips/sibyte/pci/
sbpcihb.c 81 uint64_t regval; local
85 regval = mips3_ld((void *)MIPS_PHYS_TO_KSEG0(A_SCD_SYSTEM_CFG));
86 host = (regval & M_SYS_PCI_HOST) != 0;
sbbrz.c 173 uint64_t regval; local
177 regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
178 host = (regval & M_SYS_PCI_HOST) != 0;
sbbrz_pci.c 142 uint64_t regval; local
150 regval = mips3_ld((register_t)MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG));
151 host = (regval & M_SYS_PCI_HOST) != 0;
  /src/sys/dev/ic/
vga_common.c 50 u_int8_t regval; local
62 regval = bus_space_read_1(iot, ioh_vga, VGA_MISC_DATAR);
63 mono = !(regval & 1);
90 regval = bus_space_read_1(iot, ioh_vga, VGA_ATC_DATAR);
92 bus_space_write_1(iot, ioh_vga, VGA_ATC_DATAW, regval ^ 0x0f);
95 if (bus_space_read_1(iot, ioh_vga, VGA_ATC_DATAR) != (regval ^ 0x0f))
98 bus_space_write_1(iot, ioh_vga, VGA_ATC_DATAW, regval);
bt485.c 196 u_int8_t regval; local
209 regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_0);
210 regval |= 0x80;
215 regval |= 0x02;
216 data->ramdac_wr(data->cookie, BT485_REG_COMMAND_0, regval);
222 regval = data->ramdac_rd(data->cookie, BT485_REG_COMMAND_2);
223 regval &= ~0x03;
224 regval |= 0x24;
225 data->ramdac_wr(data->cookie, BT485_REG_COMMAND_2, regval);
228 regval = bt485_rd_i(data, BT485_IREG_COMMAND_3)
481 u_int8_t regval; local
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_opp.c 389 uint32_t regval = enable ? 1 : 0; local
391 REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/
amdgpu_hw_ddc.c 80 uint32_t regval; local
92 regval = REG_GET_3(gpio.MASK_reg,
106 REG_SET_2(gpio.MASK_reg, regval,
124 REG_SET(gpio.MASK_reg, regval,
133 REG_SET(gpio.MASK_reg, regval,
169 REG_SET(gpio.MASK_reg, regval,
  /src/external/gpl3/gdb/dist/gdb/
m32r-linux-nat.c 89 elf_greg_t regval;
94 regval = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
97 regval = ((psw >> 8) & 1);
100 regval = *(regp + regmap[i]);
105 regcache->raw_supply (i, &regval);
87 elf_greg_t regval; local
rs6000-lynx178-tdep.c 307 gdb_byte regval[8]; local
314 regcache->cooked_read (tdep->ppc_fp0_regnum + 1, regval);
315 target_float_convert (regval, regtype, readbuf, valtype);
319 target_float_convert (writebuf, valtype, regval, regtype);
320 regcache->cooked_write (tdep->ppc_fp0_regnum + 1, regval);
335 ULONGEST regval; local
339 &regval);
341 regval);
364 gdb_byte regval[8]; local
366 regcache->cooked_read (tdep->ppc_gp0_regnum + 3, regval);
    [all...]
findvar.c 577 struct value *regval = frame_unwind_register_value (next_frame, regnum);
578 int reg_len = type_length_units (regval->type ()) - reg_offset;
585 regval->contents_copy (value, offset, reg_offset, reg_len);
576 struct value *regval = frame_unwind_register_value (next_frame, regnum); local
ft32-tdep.c 128 CORE_ADDR regval; local
132 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order);
133 regcache_cooked_write_unsigned (regcache, FT32_R0_REGNUM, regval);
136 regval = extract_unsigned_integer (valbuf + 4,
138 regcache_cooked_write_unsigned (regcache, FT32_R1_REGNUM, regval);
  /src/external/gpl3/gdb.old/dist/gdb/
m32r-linux-nat.c 89 elf_greg_t regval;
94 regval = ((0x00c1 & bbpsw) << 8) | ((0xc100 & psw) >> 8);
97 regval = ((psw >> 8) & 1);
100 regval = *(regp + regmap[i]);
105 regcache->raw_supply (i, &regval);
87 elf_greg_t regval; local
rs6000-lynx178-tdep.c 307 gdb_byte regval[8]; local
314 regcache->cooked_read (tdep->ppc_fp0_regnum + 1, regval);
315 target_float_convert (regval, regtype, readbuf, valtype);
319 target_float_convert (writebuf, valtype, regval, regtype);
320 regcache->cooked_write (tdep->ppc_fp0_regnum + 1, regval);
335 ULONGEST regval; local
339 &regval);
341 regval);
364 gdb_byte regval[8]; local
366 regcache->cooked_read (tdep->ppc_gp0_regnum + 3, regval);
    [all...]
  /src/sys/arch/hpcmips/dev/
mq200.c 93 unsigned long regval; local
100 regval = bus_space_read_4(iot, ioh, MQ200_PC00R);
102 regval & 0xffff, (regval >> 16) & 0xffff);
103 if (regval != ((MQ200_PRODUCT_ID << 16) | MQ200_VENDOR_ID))
112 unsigned long regval; local
128 regval = mq200_read(sc, MQ200_PC08R);
129 printf("MQ200 Rev.%02lx video controller", regval & 0xff);
ite8181.c 225 unsigned long regval; local
232 regval = ite8181_config_read_4(iot, ioh, ITE8181_ID);
234 regval & 0xffff, (regval >> 16) & 0xffff));
235 if (regval != ((ITE8181_PRODUCT_ID << 16) | ITE8181_VENDER_ID))
244 unsigned long regval; local
254 regval = ite8181_config_read_4(sc->sc_iot, sc->sc_ioh, ITE8181_CLASS);
255 printf("ITE8181 Rev.%02lx", regval & ITE8181_REV_MASK);
  /src/sys/dev/i2c/
mt2131.c 131 uint8_t regval; local
166 regval = (fr - 27501) / 55000;
168 if(regval > 0x13)
169 regval = 0x13;
171 rv = mt2131_write(sc, UPC_1, regval);
181 rv = mt2131_read(sc, 0x08, &regval);
185 if (( regval & 0x88 ) == 0x88 ) {
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_hw_sequencer.c 78 uint16_t regval[12]; member in struct:out_csc_color_matrix_type
221 val = output_csc_matrix[i].regval;
  /src/external/gpl3/gdb/dist/sim/erc32/
interf.c 316 int regval; local
318 regval = (value[0] << 24) | (value[1] << 16)
320 set_regi(&sregs, regno, regval);
  /src/external/gpl3/gdb.old/dist/sim/erc32/
interf.c 316 int regval; local
318 regval = (value[0] << 24) | (value[1] << 16)
320 set_regi(&sregs, regno, regval);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_opp_csc_v.c 137 tbl_entry->regval[0],
143 tbl_entry->regval[1],
155 tbl_entry->regval[2],
161 tbl_entry->regval[3],
173 tbl_entry->regval[4],
179 tbl_entry->regval[5],
191 tbl_entry->regval[6],
197 tbl_entry->regval[7],
209 tbl_entry->regval[8],
215 tbl_entry->regval[9]
513 uint32_t regval[12]; member in struct:input_csc_matrix
541 const uint32_t *regval = NULL; local
    [all...]
amdgpu_dce110_timing_generator_v.c 599 uint32_t regval; local
602 regval = dm_read_reg(tg->ctx, address);
603 set_reg_field_value(regval, early_cntl,
605 dm_write_reg(tg->ctx, address, regval);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_mpc.c 140 const uint16_t *regval,
152 if (regval == NULL) {
185 regval,
201 const uint16_t *regval = NULL; local
208 regval = find_color_matrix(color_space, &arr_size);
210 if (regval == NULL) {
244 regval,
  /src/external/gpl3/gdb/dist/gdbserver/
linux-i386-ipa.cc 88 int regval; local
91 regval = *(short *) (((char *) buf) + i386_ft_collect_regmap[i]);
93 regval = *(int *) (((char *) buf) + i386_ft_collect_regmap[i]);
95 supply_register (regcache, i, &regval);
  /src/external/gpl3/gdb/dist/sim/arm/
wrapper.c 541 ARMword regval; local
564 regval = ARMul_GetReg (state, state->Mode, rn);
580 regval = ARMul_GetCPSR (state);
647 tomem (state, memory, regval);
651 regval = 0;

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