1 /* $NetBSD: pci_machdep.c,v 1.7 2012/10/27 17:18:05 chs Exp $ */ 2 3 #include <sys/cdefs.h> 4 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.7 2012/10/27 17:18:05 chs Exp $"); 5 6 #include <sys/param.h> 7 #include <sys/device.h> 8 #include <dev/pci/pcireg.h> 9 #include <dev/pci/pcivar.h> 10 11 #include <arm/footbridge/dc21285reg.h> 12 13 void 14 netwinder_pci_attach_hook(device_t parent, device_t self, 15 struct pcibus_attach_args *pba) 16 { 17 pcireg_t regval; 18 pcireg_t intreg; 19 pcitag_t tag; 20 21 /* 22 * Initialize the TULIP 23 */ 24 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 9, 0); 25 pci_conf_write(pba->pba_pc, tag, 26 PCI_COMMAND_STATUS_REG, 27 PCI_COMMAND_IO_ENABLE| 28 PCI_COMMAND_MEM_ENABLE| 29 PCI_COMMAND_MASTER_ENABLE); 30 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 31 intreg = PCI_INTERRUPT_CODE( 32 PCI_INTERRUPT_LATENCY(intreg), 33 PCI_INTERRUPT_GRANT(intreg), 34 PCI_INTERRUPT_PIN(intreg), 35 0x40|IRQ_IN_L1); 36 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 37 pci_conf_write(pba->pba_pc, tag, 0x10, 0x400 | PCI_MAPREG_TYPE_IO); 38 pci_conf_write(pba->pba_pc, tag, 0x14, 0x00800000); 39 40 /* 41 * Initialize the PCI NE2000 42 */ 43 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 12, 0); 44 pci_conf_write(pba->pba_pc, tag, 45 PCI_COMMAND_STATUS_REG, 46 PCI_COMMAND_IO_ENABLE| 47 PCI_COMMAND_MASTER_ENABLE); 48 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 49 intreg = PCI_INTERRUPT_CODE( 50 PCI_INTERRUPT_LATENCY(intreg), 51 PCI_INTERRUPT_GRANT(intreg), 52 PCI_INTERRUPT_PIN(intreg), 53 0x40|IRQ_IN_L0); 54 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 55 pci_conf_write(pba->pba_pc, tag, 0x10, 0x300 | PCI_MAPREG_TYPE_IO); 56 57 #if 0 58 /* 59 * Initialize the PCI-ISA Bridge 60 */ 61 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 0); 62 pci_conf_write(pba->pba_pc, tag, 63 PCI_COMMAND_STATUS_REG, 64 PCI_COMMAND_IO_ENABLE| 65 PCI_COMMAND_MEM_ENABLE| 66 PCI_COMMAND_MASTER_ENABLE); 67 pci_conf_write(pba->pba_pc, tag, 0x10, 0); 68 pci_conf_write(pba->pba_pc, tag, 0x48, 69 pci_conf_read(pba->pba_pc, tag, 0x48)|0xff); 70 71 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 72 regval &= 0xff00ff00; 73 regval |= 0x00000022; 74 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 75 76 regval = pci_conf_read(pba->pba_pc, tag, 0x80); 77 regval &= 0x0000ff00; 78 regval |= 0xe0010002; 79 pci_conf_write(pba->pba_pc, tag, 0x80, regval); 80 #endif 81 82 /* 83 * Initialize the PCIIDE Controller 84 */ 85 tag = pci_make_tag(pba->pba_pc, pba->pba_bus, 11, 1); 86 pci_conf_write(pba->pba_pc, tag, 87 PCI_COMMAND_STATUS_REG, 88 PCI_COMMAND_IO_ENABLE| 89 PCI_COMMAND_MASTER_ENABLE); 90 91 regval = pci_conf_read(pba->pba_pc, tag, PCI_CLASS_REG); 92 regval = PCI_CLASS_CODE(PCI_CLASS(regval), PCI_SUBCLASS(regval), 0x8A); 93 pci_conf_write(pba->pba_pc, tag, PCI_CLASS_REG, regval); 94 95 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 96 regval &= ~0x10; /* disable secondary port */ 97 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 98 99 pci_conf_write(pba->pba_pc, tag, 0x10, 0x01f0 | PCI_MAPREG_TYPE_IO); 100 pci_conf_write(pba->pba_pc, tag, 0x14, 0x03f4 | PCI_MAPREG_TYPE_IO); 101 pci_conf_write(pba->pba_pc, tag, 0x18, 0x0170 | PCI_MAPREG_TYPE_IO); 102 pci_conf_write(pba->pba_pc, tag, 0x1c, 0x0374 | PCI_MAPREG_TYPE_IO); 103 pci_conf_write(pba->pba_pc, tag, 0x20, 0xe800 | PCI_MAPREG_TYPE_IO); 104 intreg = pci_conf_read(pba->pba_pc, tag, PCI_INTERRUPT_REG); 105 intreg = PCI_INTERRUPT_CODE( 106 PCI_INTERRUPT_LATENCY(intreg), 107 PCI_INTERRUPT_GRANT(intreg), 108 PCI_INTERRUPT_PIN(intreg), 109 0x8e); 110 pci_conf_write(pba->pba_pc, tag, PCI_INTERRUPT_REG, intreg); 111 112 /* 113 * Make sure we are in legacy mode 114 */ 115 regval = pci_conf_read(pba->pba_pc, tag, 0x40); 116 regval &= ~0x800; 117 pci_conf_write(pba->pba_pc, tag, 0x40, regval); 118 } 119
Indexes created Sat Sep 20 22:09:52 GMT 2025