1 /* $NetBSD: siside.c,v 1.38 2019/02/05 11:30:07 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.38 2019/02/05 11:30:07 mrg Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_sis_reg.h> 38 39 static void sis_chip_map(struct pciide_softc *, const struct pci_attach_args *); 40 static void sis_sata_chip_map(struct pciide_softc *, 41 const struct pci_attach_args *); 42 static void sis_setup_channel(struct ata_channel *); 43 static void sis96x_setup_channel(struct ata_channel *); 44 45 static int sis_hostbr_match(const struct pci_attach_args *); 46 static int sis_south_match(const struct pci_attach_args *); 47 48 static int siside_match(device_t, cfdata_t, void *); 49 static void siside_attach(device_t, device_t, void *); 50 51 CFATTACH_DECL_NEW(siside, sizeof(struct pciide_softc), 52 siside_match, siside_attach, pciide_detach, NULL); 53 54 static const struct pciide_product_desc pciide_sis_products[] = { 55 { PCI_PRODUCT_SIS_5597_IDE, 56 0, 57 NULL, 58 sis_chip_map, 59 }, 60 { PCI_PRODUCT_SIS_180_SATA, 61 0, 62 NULL, 63 sis_sata_chip_map, 64 }, 65 { PCI_PRODUCT_SIS_181_SATA, 66 0, 67 NULL, 68 sis_sata_chip_map, 69 }, 70 { PCI_PRODUCT_SIS_182_SATA, 71 0, 72 NULL, 73 sis_sata_chip_map, 74 }, 75 { 0, 76 0, 77 NULL, 78 NULL 79 } 80 }; 81 82 static int 83 siside_match(device_t parent, cfdata_t match, void *aux) 84 { 85 struct pci_attach_args *pa = aux; 86 87 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 88 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 89 return (2); 90 } 91 return (0); 92 } 93 94 static void 95 siside_attach(device_t parent, device_t self, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 struct pciide_softc *sc = device_private(self); 99 pci_chipset_tag_t pc = pa->pa_pc; 100 pcitag_t tag = pa->pa_tag; 101 pcireg_t csr; 102 103 sc->sc_wdcdev.sc_atac.atac_dev = self; 104 105 pciide_common_attach(sc, pa, 106 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 107 108 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 109 if (csr & PCI_COMMAND_INTERRUPT_DISABLE) { 110 csr &= ~PCI_COMMAND_INTERRUPT_DISABLE; 111 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 112 } 113 } 114 115 static const struct sis_hostbr_type { 116 u_int16_t id; 117 u_int8_t rev; 118 u_int8_t udma_mode; 119 const char *name; 120 u_int8_t type; 121 #define SIS_TYPE_NOUDMA 0 122 #define SIS_TYPE_66 1 123 #define SIS_TYPE_100OLD 2 124 #define SIS_TYPE_100NEW 3 125 #define SIS_TYPE_133OLD 4 126 #define SIS_TYPE_133NEW 5 127 #define SIS_TYPE_SOUTH 6 128 } sis_hostbr_type[] = { 129 /* Most infos here are from sos (at) freebsd.org */ 130 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 131 #if 0 132 /* 133 * controllers associated to a rev 0x2 530 Host to PCI Bridge 134 * have problems with UDMA (info provided by Christos) 135 */ 136 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 137 #endif 138 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 139 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 140 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 141 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 142 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 143 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 144 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 145 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 150 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 151 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 152 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 153 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 155 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 156 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 157 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 158 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 159 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 160 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 161 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_100NEW}, 162 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 163 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 164 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 165 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 166 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 167 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 168 /* 169 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 170 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 171 */ 172 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 173 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 174 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 175 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 176 }; 177 178 static const struct sis_hostbr_type *sis_hostbr_type_match; 179 180 static int 181 sis_hostbr_match(const struct pci_attach_args *pa) 182 { 183 int i; 184 pcireg_t id, masqid, reg; 185 186 id = pa->pa_id; 187 188 if (PCI_VENDOR(id) != PCI_VENDOR_SIS) 189 return 0; 190 if (PCI_PRODUCT(id) == PCI_PRODUCT_SIS_85C503) { 191 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 192 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 193 reg | SIS96x_DETECT_MASQ); 194 masqid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 195 if (((PCI_PRODUCT(masqid) & 0xfff0) != 0x0960) 196 && (PCI_PRODUCT(masqid) != 0x0018)) { 197 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 198 reg); 199 } else { 200 id = masqid; 201 } 202 } 203 204 sis_hostbr_type_match = NULL; 205 for (i = 0; i < __arraycount(sis_hostbr_type); i++) { 206 if (PCI_PRODUCT(id) == sis_hostbr_type[i].id && 207 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 208 sis_hostbr_type_match = &sis_hostbr_type[i]; 209 } 210 return (sis_hostbr_type_match != NULL); 211 } 212 213 static int 214 sis_south_match(const struct pci_attach_args *pa) 215 { 216 217 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 218 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 219 PCI_REVISION(pa->pa_class) >= 0x10); 220 } 221 222 static void 223 sis_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 224 { 225 struct pciide_channel *cp; 226 int channel; 227 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 228 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 229 pcireg_t rev = PCI_REVISION(pa->pa_class); 230 231 if (pciide_chipen(sc, pa) == 0) 232 return; 233 234 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 235 "Silicon Integrated Systems "); 236 pci_find_device(NULL, sis_hostbr_match); 237 if (sis_hostbr_type_match) { 238 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 239 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 240 pciide_pci_read(sc->sc_pc, sc->sc_tag, 241 SIS_REG_57) & 0x7f); 242 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 243 PCI_ID_REG)) == SIS_PRODUCT_5518) { 244 aprint_normal("96X UDMA%d ", 245 sis_hostbr_type_match->udma_mode); 246 sc->sis_type = SIS_TYPE_133NEW; 247 sc->sc_wdcdev.sc_atac.atac_udma_cap = 248 sis_hostbr_type_match->udma_mode; 249 } else { 250 if (pci_find_device(NULL, sis_south_match)) { 251 sc->sis_type = SIS_TYPE_133OLD; 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 253 sis_hostbr_type_match->udma_mode; 254 } else { 255 sc->sis_type = SIS_TYPE_100NEW; 256 sc->sc_wdcdev.sc_atac.atac_udma_cap = 257 sis_hostbr_type_match->udma_mode; 258 } 259 } 260 } else { 261 sc->sis_type = sis_hostbr_type_match->type; 262 sc->sc_wdcdev.sc_atac.atac_udma_cap = 263 sis_hostbr_type_match->udma_mode; 264 } 265 aprint_normal("%s", sis_hostbr_type_match->name); 266 } else { 267 aprint_normal("5597/5598"); 268 if (rev >= 0xd0) { 269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 270 sc->sis_type = SIS_TYPE_66; 271 } else { 272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 273 sc->sis_type = SIS_TYPE_NOUDMA; 274 } 275 } 276 aprint_normal(" IDE controller (rev. 0x%02x)\n", 277 PCI_REVISION(pa->pa_class)); 278 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 279 "bus-master DMA support present"); 280 pciide_mapreg_dma(sc, pa); 281 aprint_verbose("\n"); 282 283 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 284 if (sc->sc_dma_ok) { 285 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 286 sc->sc_wdcdev.irqack = pciide_irqack; 287 if (sc->sis_type >= SIS_TYPE_66) 288 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 289 } 290 291 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 292 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 293 294 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 295 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 296 sc->sc_wdcdev.wdc_maxdrives = 2; 297 switch(sc->sis_type) { 298 case SIS_TYPE_NOUDMA: 299 case SIS_TYPE_66: 300 case SIS_TYPE_100OLD: 301 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 302 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 303 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 304 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 305 break; 306 case SIS_TYPE_100NEW: 307 case SIS_TYPE_133OLD: 308 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 309 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 310 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 311 break; 312 case SIS_TYPE_133NEW: 313 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 314 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 315 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 316 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 317 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 318 break; 319 } 320 321 wdc_allocate_regs(&sc->sc_wdcdev); 322 323 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 324 channel++) { 325 cp = &sc->pciide_channels[channel]; 326 if (pciide_chansetup(sc, channel, interface) == 0) 327 continue; 328 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 329 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 330 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 331 "%s channel ignored (disabled)\n", cp->name); 332 cp->ata_channel.ch_flags |= ATACH_DISABLED; 333 continue; 334 } 335 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 336 } 337 } 338 339 static void 340 sis96x_setup_channel(struct ata_channel *chp) 341 { 342 struct ata_drive_datas *drvp; 343 int drive, s; 344 u_int32_t sis_tim; 345 u_int32_t idedma_ctl; 346 int regtim; 347 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 348 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 349 350 sis_tim = 0; 351 idedma_ctl = 0; 352 /* setup DMA if needed */ 353 pciide_channel_dma_setup(cp); 354 355 for (drive = 0; drive < 2; drive++) { 356 regtim = SIS_TIM133( 357 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 358 chp->ch_channel, drive); 359 drvp = &chp->ch_drive[drive]; 360 /* If no drive, skip */ 361 if (drvp->drive_type == ATA_DRIVET_NONE) 362 continue; 363 /* add timing values, setup DMA if needed */ 364 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 365 /* use Ultra/DMA */ 366 s = splbio(); 367 drvp->drive_flags &= ~ATA_DRIVE_DMA; 368 splx(s); 369 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 370 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 371 if (drvp->UDMA_mode > 2) 372 drvp->UDMA_mode = 2; 373 } 374 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 375 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 376 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 377 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 378 /* 379 * use Multiword DMA 380 * Timings will be used for both PIO and DMA, 381 * so adjust DMA mode if needed 382 */ 383 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 384 drvp->PIO_mode = drvp->DMA_mode + 2; 385 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 386 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 387 drvp->PIO_mode - 2 : 0; 388 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 389 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 390 } else { 391 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 392 } 393 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 394 "channel %d drive %d: 0x%x (reg 0x%x)\n", 395 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 396 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 397 } 398 if (idedma_ctl != 0) { 399 /* Add software bits in status register */ 400 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 401 idedma_ctl); 402 } 403 } 404 405 static void 406 sis_setup_channel(struct ata_channel *chp) 407 { 408 struct ata_drive_datas *drvp; 409 int drive, s; 410 u_int32_t sis_tim; 411 u_int32_t idedma_ctl; 412 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 413 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 414 415 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 416 "channel %d 0x%x\n", chp->ch_channel, 417 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 418 DEBUG_PROBE); 419 sis_tim = 0; 420 idedma_ctl = 0; 421 /* setup DMA if needed */ 422 pciide_channel_dma_setup(cp); 423 424 for (drive = 0; drive < 2; drive++) { 425 drvp = &chp->ch_drive[drive]; 426 /* If no drive, skip */ 427 if (drvp->drive_type == ATA_DRIVET_NONE) 428 continue; 429 /* add timing values, setup DMA if needed */ 430 if ((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 431 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) 432 goto pio; 433 434 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 435 /* use Ultra/DMA */ 436 s = splbio(); 437 drvp->drive_flags &= ~ATA_DRIVE_DMA; 438 splx(s); 439 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 440 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 441 if (drvp->UDMA_mode > 2) 442 drvp->UDMA_mode = 2; 443 } 444 switch (sc->sis_type) { 445 case SIS_TYPE_66: 446 case SIS_TYPE_100OLD: 447 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 448 SIS_TIM66_UDMA_TIME_OFF(drive); 449 break; 450 case SIS_TYPE_100NEW: 451 sis_tim |= 452 sis_udma100new_tim[drvp->UDMA_mode] << 453 SIS_TIM100_UDMA_TIME_OFF(drive); 454 break; 455 case SIS_TYPE_133OLD: 456 sis_tim |= 457 sis_udma133old_tim[drvp->UDMA_mode] << 458 SIS_TIM100_UDMA_TIME_OFF(drive); 459 break; 460 default: 461 aprint_error("unknown SiS IDE type %d\n", 462 sc->sis_type); 463 } 464 } else { 465 /* 466 * use Multiword DMA 467 * Timings will be used for both PIO and DMA, 468 * so adjust DMA mode if needed 469 */ 470 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 471 drvp->PIO_mode = drvp->DMA_mode + 2; 472 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 473 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 474 drvp->PIO_mode - 2 : 0; 475 if (drvp->DMA_mode == 0) 476 drvp->PIO_mode = 0; 477 } 478 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 479 pio: switch (sc->sis_type) { 480 case SIS_TYPE_NOUDMA: 481 case SIS_TYPE_66: 482 case SIS_TYPE_100OLD: 483 sis_tim |= sis_pio_act[drvp->PIO_mode] << 484 SIS_TIM66_ACT_OFF(drive); 485 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 486 SIS_TIM66_REC_OFF(drive); 487 break; 488 case SIS_TYPE_100NEW: 489 case SIS_TYPE_133OLD: 490 sis_tim |= sis_pio_act[drvp->PIO_mode] << 491 SIS_TIM100_ACT_OFF(drive); 492 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 493 SIS_TIM100_REC_OFF(drive); 494 break; 495 default: 496 aprint_error("unknown SiS IDE type %d\n", 497 sc->sis_type); 498 } 499 } 500 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 501 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 502 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 503 sis_tim); 504 if (idedma_ctl != 0) { 505 /* Add software bits in status register */ 506 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 507 idedma_ctl); 508 } 509 } 510 511 static void 512 sis_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 513 { 514 struct pciide_channel *cp; 515 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 516 int channel; 517 518 if (pciide_chipen(sc, pa) == 0) 519 return; 520 521 if (interface == 0) { 522 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 523 DEBUG_PROBE); 524 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 525 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 526 } 527 528 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 529 "Silicon Integrated Systems 180/96X SATA controller " 530 "(rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 531 532 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 533 "bus-master DMA support present"); 534 pciide_mapreg_dma(sc, pa); 535 aprint_verbose("\n"); 536 537 if (sc->sc_dma_ok) { 538 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 539 sc->sc_wdcdev.irqack = pciide_irqack; 540 } 541 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 542 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 543 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 544 545 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 546 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 547 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 548 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 549 sc->sc_wdcdev.wdc_maxdrives = 2; 550 551 wdc_allocate_regs(&sc->sc_wdcdev); 552 553 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 554 channel++) { 555 cp = &sc->pciide_channels[channel]; 556 if (pciide_chansetup(sc, channel, interface) == 0) 557 continue; 558 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 559 } 560 } 561
Indexes created Sat Sep 27 22:09:54 GMT 2025