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Searched defs:tisr (Results 1 - 2 of 2) sorted by relevancy

/src/external/gpl3/gdb.old/dist/sim/mips/
dv-tx3904tmr.c	`58 4: TISR: timer interrupt status register 163 unsigned_4 tisr; member in struct:tx3904tmr 164 #define SET_TISR_TWIS(c) ((c)->tisr \|= 0x08) 165 #define SET_TISR_TPIBS(c) ((c)->tisr \|= 0x04) 166 #define SET_TISR_TPIAS(c) ((c)->tisr \|= 0x02) 167 #define SET_TISR_TIIS(c) ((c)->tisr \|= 0x01) 266 controller->tisr = 301 controller->tisr = 342 case TISR_REG: register_value = controller->tisr; break; 450 if (controller->tisr != 0) /* any interrupts active? * [all...]`
/src/external/gpl3/gdb/dist/sim/mips/
dv-tx3904tmr.c	`58 4: TISR: timer interrupt status register 163 unsigned_4 tisr; member in struct:tx3904tmr 164 #define SET_TISR_TWIS(c) ((c)->tisr \|= 0x08) 165 #define SET_TISR_TPIBS(c) ((c)->tisr \|= 0x04) 166 #define SET_TISR_TPIAS(c) ((c)->tisr \|= 0x02) 167 #define SET_TISR_TIIS(c) ((c)->tisr \|= 0x01) 266 controller->tisr = 301 controller->tisr = 342 case TISR_REG: register_value = controller->tisr; break; 450 if (controller->tisr != 0) /* any interrupts active? * [all...]`

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