| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dce_calcs.c | 106 struct bw_fixed yclk[3]; local in function:calculate_bandwidth
131 yclk[low] = vbios->low_yclk;
132 yclk[mid] = vbios->mid_yclk;
133 yclk[high] = vbios->high_yclk;
1061 /*the dmif and mcifwr yclk(pclk) required is the one that allows the transfer of all pipe's data buffer size in memory in the time for data transfer*/
1149 /*it will take 4 memclk cycles or 8 yclk cycles to fetch 64 bytes of data from the hbm memory (2 read commands).*/
1150 /*it will take 2 memclk cycles or 4 yclk cycles to fetch 32 bytes of data from the hbm memory (1 read command).*/
1193 data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100)))));
1195 data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width))));
1270 /*for cpu p-state change to be possible for a yclk(pclk) and sclk level the dispclk required has to be enough for the blackout duration*
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 702 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce10_wm_params
729 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v10_0_dram_bandwidth
733 yclk.full = dfixed_const(wm->yclk);
734 yclk.full = dfixed_div(yclk, a);
739 bandwidth.full = dfixed_mul(dram_channels, yclk);
758 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v10_0_dram_bandwidth_for_display
762 yclk.full = dfixed_const(wm->yclk);
[all...] |
| amdgpu_dce_v11_0.c | 728 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce10_wm_params
755 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v11_0_dram_bandwidth
759 yclk.full = dfixed_const(wm->yclk);
760 yclk.full = dfixed_div(yclk, a);
765 bandwidth.full = dfixed_mul(dram_channels, yclk);
784 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v11_0_dram_bandwidth_for_display
788 yclk.full = dfixed_const(wm->yclk);
[all...] |
| amdgpu_dce_v6_0.c | 500 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce6_wm_params
527 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v6_0_dram_bandwidth
531 yclk.full = dfixed_const(wm->yclk);
532 yclk.full = dfixed_div(yclk, a);
537 bandwidth.full = dfixed_mul(dram_channels, yclk);
556 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v6_0_dram_bandwidth_for_display
560 yclk.full = dfixed_const(wm->yclk);
[all...] |
| amdgpu_dce_v8_0.c | 637 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce8_wm_params
664 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v8_0_dram_bandwidth
668 yclk.full = dfixed_const(wm->yclk);
669 yclk.full = dfixed_div(yclk, a);
674 bandwidth.full = dfixed_mul(dram_channels, yclk);
693 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce_v8_0_dram_bandwidth_for_display
697 yclk.full = dfixed_const(wm->yclk);
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 1938 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:evergreen_wm_params
1956 fixed20_12 yclk, dram_channels, bandwidth; local in function:evergreen_dram_bandwidth
1960 yclk.full = dfixed_const(wm->yclk);
1961 yclk.full = dfixed_div(yclk, a);
1966 bandwidth.full = dfixed_mul(dram_channels, yclk);
1976 fixed20_12 yclk, dram_channels, bandwidth; local in function:evergreen_dram_bandwidth_for_display
1980 yclk.full = dfixed_const(wm->yclk);
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| radeon_si.c | 2066 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce6_wm_params
2084 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce6_dram_bandwidth
2088 yclk.full = dfixed_const(wm->yclk);
2089 yclk.full = dfixed_div(yclk, a);
2094 bandwidth.full = dfixed_mul(dram_channels, yclk);
2104 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce6_dram_bandwidth_for_display
2108 yclk.full = dfixed_const(wm->yclk);
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| radeon_cik.c | 8983 u32 yclk; /* bandwidth per dram data pin in kHz */ member in struct:dce8_wm_params
9010 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce8_dram_bandwidth
9014 yclk.full = dfixed_const(wm->yclk);
9015 yclk.full = dfixed_div(yclk, a);
9020 bandwidth.full = dfixed_mul(dram_channels, yclk);
9039 fixed20_12 yclk, dram_channels, bandwidth; local in function:dce8_dram_bandwidth_for_display
9043 yclk.full = dfixed_const(wm->yclk);
[all...] |
