1 /* $NetBSD: amdgpu_dce_v10_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_v10_0.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 28 29 #include <drm/drm_fourcc.h> 30 #include <drm/drm_vblank.h> 31 32 #include "amdgpu.h" 33 #include "amdgpu_pm.h" 34 #include "amdgpu_i2c.h" 35 #include "vid.h" 36 #include "atom.h" 37 #include "amdgpu_atombios.h" 38 #include "atombios_crtc.h" 39 #include "atombios_encoders.h" 40 #include "amdgpu_pll.h" 41 #include "amdgpu_connectors.h" 42 #include "amdgpu_display.h" 43 #include "dce_v10_0.h" 44 45 #include "dce/dce_10_0_d.h" 46 #include "dce/dce_10_0_sh_mask.h" 47 #include "dce/dce_10_0_enum.h" 48 #include "oss/oss_3_0_d.h" 49 #include "oss/oss_3_0_sh_mask.h" 50 #include "gmc/gmc_8_1_d.h" 51 #include "gmc/gmc_8_1_sh_mask.h" 52 53 #include "ivsrcid/ivsrcid_vislands30.h" 54 55 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 56 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 57 58 static const u32 crtc_offsets[] = 59 { 60 CRTC0_REGISTER_OFFSET, 61 CRTC1_REGISTER_OFFSET, 62 CRTC2_REGISTER_OFFSET, 63 CRTC3_REGISTER_OFFSET, 64 CRTC4_REGISTER_OFFSET, 65 CRTC5_REGISTER_OFFSET, 66 CRTC6_REGISTER_OFFSET 67 }; 68 69 static const u32 hpd_offsets[] = 70 { 71 HPD0_REGISTER_OFFSET, 72 HPD1_REGISTER_OFFSET, 73 HPD2_REGISTER_OFFSET, 74 HPD3_REGISTER_OFFSET, 75 HPD4_REGISTER_OFFSET, 76 HPD5_REGISTER_OFFSET 77 }; 78 79 static const uint32_t dig_offsets[] = { 80 DIG0_REGISTER_OFFSET, 81 DIG1_REGISTER_OFFSET, 82 DIG2_REGISTER_OFFSET, 83 DIG3_REGISTER_OFFSET, 84 DIG4_REGISTER_OFFSET, 85 DIG5_REGISTER_OFFSET, 86 DIG6_REGISTER_OFFSET 87 }; 88 89 static const struct { 90 uint32_t reg; 91 uint32_t vblank; 92 uint32_t vline; 93 uint32_t hpd; 94 95 } interrupt_status_offsets[] = { { 96 .reg = mmDISP_INTERRUPT_STATUS, 97 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 115 }, { 116 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 117 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 118 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 119 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 120 }, { 121 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 122 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 123 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 124 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 125 } }; 126 127 static const u32 golden_settings_tonga_a11[] = 128 { 129 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 130 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 131 mmFBC_MISC, 0x1f311fff, 0x12300000, 132 mmHDMI_CONTROL, 0x31000111, 0x00000011, 133 }; 134 135 static const u32 tonga_mgcg_cgcg_init[] = 136 { 137 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 138 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 139 }; 140 141 static const u32 golden_settings_fiji_a10[] = 142 { 143 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 144 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 145 mmFBC_MISC, 0x1f311fff, 0x12300000, 146 mmHDMI_CONTROL, 0x31000111, 0x00000011, 147 }; 148 149 static const u32 fiji_mgcg_cgcg_init[] = 150 { 151 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 152 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 153 }; 154 155 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 156 { 157 switch (adev->asic_type) { 158 case CHIP_FIJI: 159 amdgpu_device_program_register_sequence(adev, 160 fiji_mgcg_cgcg_init, 161 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 162 amdgpu_device_program_register_sequence(adev, 163 golden_settings_fiji_a10, 164 ARRAY_SIZE(golden_settings_fiji_a10)); 165 break; 166 case CHIP_TONGA: 167 amdgpu_device_program_register_sequence(adev, 168 tonga_mgcg_cgcg_init, 169 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 170 amdgpu_device_program_register_sequence(adev, 171 golden_settings_tonga_a11, 172 ARRAY_SIZE(golden_settings_tonga_a11)); 173 break; 174 default: 175 break; 176 } 177 } 178 179 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 180 u32 block_offset, u32 reg) 181 { 182 unsigned long flags; 183 u32 r; 184 185 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 186 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 187 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 188 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 189 190 return r; 191 } 192 193 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 194 u32 block_offset, u32 reg, u32 v) 195 { 196 unsigned long flags; 197 198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 200 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 202 } 203 204 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 205 { 206 if (crtc >= adev->mode_info.num_crtc) 207 return 0; 208 else 209 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 210 } 211 212 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 213 { 214 unsigned i; 215 216 /* Enable pflip interrupts */ 217 for (i = 0; i < adev->mode_info.num_crtc; i++) 218 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 219 } 220 221 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 222 { 223 unsigned i; 224 225 /* Disable pflip interrupts */ 226 for (i = 0; i < adev->mode_info.num_crtc; i++) 227 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 228 } 229 230 /** 231 * dce_v10_0_page_flip - pageflip callback. 232 * 233 * @adev: amdgpu_device pointer 234 * @crtc_id: crtc to cleanup pageflip on 235 * @crtc_base: new address of the crtc (GPU MC address) 236 * 237 * Triggers the actual pageflip by updating the primary 238 * surface base address. 239 */ 240 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 241 int crtc_id, u64 crtc_base, bool async) 242 { 243 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 244 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 245 u32 tmp; 246 247 /* flip at hsync for async, default is vsync */ 248 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 249 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 250 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); 251 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 252 /* update pitch */ 253 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 254 fb->pitches[0] / fb->format->cpp[0]); 255 /* update the primary scanout address */ 256 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 257 upper_32_bits(crtc_base)); 258 /* writing to the low address triggers the update */ 259 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 260 lower_32_bits(crtc_base)); 261 /* post the write */ 262 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 263 } 264 265 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 266 u32 *vbl, u32 *position) 267 { 268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 269 return -EINVAL; 270 271 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 272 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 273 274 return 0; 275 } 276 277 /** 278 * dce_v10_0_hpd_sense - hpd sense callback. 279 * 280 * @adev: amdgpu_device pointer 281 * @hpd: hpd (hotplug detect) pin 282 * 283 * Checks if a digital monitor is connected (evergreen+). 284 * Returns true if connected, false if not connected. 285 */ 286 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 287 enum amdgpu_hpd_id hpd) 288 { 289 bool connected = false; 290 291 if (hpd >= adev->mode_info.num_hpd) 292 return connected; 293 294 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 295 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 296 connected = true; 297 298 return connected; 299 } 300 301 /** 302 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 303 * 304 * @adev: amdgpu_device pointer 305 * @hpd: hpd (hotplug detect) pin 306 * 307 * Set the polarity of the hpd pin (evergreen+). 308 */ 309 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 310 enum amdgpu_hpd_id hpd) 311 { 312 u32 tmp; 313 bool connected = dce_v10_0_hpd_sense(adev, hpd); 314 315 if (hpd >= adev->mode_info.num_hpd) 316 return; 317 318 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 319 if (connected) 320 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 321 else 322 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 323 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 324 } 325 326 /** 327 * dce_v10_0_hpd_init - hpd setup callback. 328 * 329 * @adev: amdgpu_device pointer 330 * 331 * Setup the hpd pins used by the card (evergreen+). 332 * Enable the pin, set the polarity, and enable the hpd interrupts. 333 */ 334 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 335 { 336 struct drm_device *dev = adev->ddev; 337 struct drm_connector *connector; 338 struct drm_connector_list_iter iter; 339 u32 tmp; 340 341 drm_connector_list_iter_begin(dev, &iter); 342 drm_for_each_connector_iter(connector, &iter) { 343 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 344 345 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 346 continue; 347 348 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 349 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 350 /* don't try to enable hpd on eDP or LVDS avoid breaking the 351 * aux dp channel on imac and help (but not completely fix) 352 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 353 * also avoid interrupt storms during dpms. 354 */ 355 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 356 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 357 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 358 continue; 359 } 360 361 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 362 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 363 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 364 365 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 366 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 367 DC_HPD_CONNECT_INT_DELAY, 368 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 369 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 370 DC_HPD_DISCONNECT_INT_DELAY, 371 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 372 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 373 374 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 375 amdgpu_irq_get(adev, &adev->hpd_irq, 376 amdgpu_connector->hpd.hpd); 377 } 378 drm_connector_list_iter_end(&iter); 379 } 380 381 /** 382 * dce_v10_0_hpd_fini - hpd tear down callback. 383 * 384 * @adev: amdgpu_device pointer 385 * 386 * Tear down the hpd pins used by the card (evergreen+). 387 * Disable the hpd interrupts. 388 */ 389 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 390 { 391 struct drm_device *dev = adev->ddev; 392 struct drm_connector *connector; 393 struct drm_connector_list_iter iter; 394 u32 tmp; 395 396 drm_connector_list_iter_begin(dev, &iter); 397 drm_for_each_connector_iter(connector, &iter) { 398 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 399 400 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 401 continue; 402 403 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 404 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 405 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 406 407 amdgpu_irq_put(adev, &adev->hpd_irq, 408 amdgpu_connector->hpd.hpd); 409 } 410 drm_connector_list_iter_end(&iter); 411 } 412 413 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 414 { 415 return mmDC_GPIO_HPD_A; 416 } 417 418 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 419 { 420 u32 crtc_hung = 0; 421 u32 crtc_status[6]; 422 u32 i, j, tmp; 423 424 for (i = 0; i < adev->mode_info.num_crtc; i++) { 425 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 426 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 427 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 428 crtc_hung |= (1 << i); 429 } 430 } 431 432 for (j = 0; j < 10; j++) { 433 for (i = 0; i < adev->mode_info.num_crtc; i++) { 434 if (crtc_hung & (1 << i)) { 435 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 436 if (tmp != crtc_status[i]) 437 crtc_hung &= ~(1 << i); 438 } 439 } 440 if (crtc_hung == 0) 441 return false; 442 udelay(100); 443 } 444 445 return true; 446 } 447 448 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 449 bool render) 450 { 451 u32 tmp; 452 453 /* Lockout access through VGA aperture*/ 454 tmp = RREG32(mmVGA_HDP_CONTROL); 455 if (render) 456 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 457 else 458 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 459 WREG32(mmVGA_HDP_CONTROL, tmp); 460 461 /* disable VGA render */ 462 tmp = RREG32(mmVGA_RENDER_CONTROL); 463 if (render) 464 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 465 else 466 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 467 WREG32(mmVGA_RENDER_CONTROL, tmp); 468 } 469 470 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev) 471 { 472 int num_crtc = 0; 473 474 switch (adev->asic_type) { 475 case CHIP_FIJI: 476 case CHIP_TONGA: 477 num_crtc = 6; 478 break; 479 default: 480 num_crtc = 0; 481 } 482 return num_crtc; 483 } 484 485 void dce_v10_0_disable_dce(struct amdgpu_device *adev) 486 { 487 /*Disable VGA render and enabled crtc, if has DCE engine*/ 488 if (amdgpu_atombios_has_dce_engine_info(adev)) { 489 u32 tmp; 490 int crtc_enabled, i; 491 492 dce_v10_0_set_vga_render_state(adev, false); 493 494 /*Disable crtc*/ 495 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) { 496 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 497 CRTC_CONTROL, CRTC_MASTER_EN); 498 if (crtc_enabled) { 499 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 500 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 501 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 502 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 503 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 504 } 505 } 506 } 507 } 508 509 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 510 { 511 struct drm_device *dev = encoder->dev; 512 struct amdgpu_device *adev = dev->dev_private; 513 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 514 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 515 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 516 int bpc = 0; 517 u32 tmp = 0; 518 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 519 520 if (connector) { 521 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 522 bpc = amdgpu_connector_get_monitor_bpc(connector); 523 dither = amdgpu_connector->dither; 524 } 525 526 /* LVDS/eDP FMT is set up by atom */ 527 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 528 return; 529 530 /* not needed for analog */ 531 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 532 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 533 return; 534 535 if (bpc == 0) 536 return; 537 538 switch (bpc) { 539 case 6: 540 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 541 /* XXX sort out optimal dither settings */ 542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 544 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 546 } else { 547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 549 } 550 break; 551 case 8: 552 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 553 /* XXX sort out optimal dither settings */ 554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 559 } else { 560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 561 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 562 } 563 break; 564 case 10: 565 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 566 /* XXX sort out optimal dither settings */ 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 572 } else { 573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 575 } 576 break; 577 default: 578 /* not needed */ 579 break; 580 } 581 582 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 583 } 584 585 586 /* display watermark setup */ 587 /** 588 * dce_v10_0_line_buffer_adjust - Set up the line buffer 589 * 590 * @adev: amdgpu_device pointer 591 * @amdgpu_crtc: the selected display controller 592 * @mode: the current display mode on the selected display 593 * controller 594 * 595 * Setup up the line buffer allocation for 596 * the selected display controller (CIK). 597 * Returns the line buffer size in pixels. 598 */ 599 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 600 struct amdgpu_crtc *amdgpu_crtc, 601 struct drm_display_mode *mode) 602 { 603 u32 tmp, buffer_alloc, i, mem_cfg; 604 u32 pipe_offset = amdgpu_crtc->crtc_id; 605 /* 606 * Line Buffer Setup 607 * There are 6 line buffers, one for each display controllers. 608 * There are 3 partitions per LB. Select the number of partitions 609 * to enable based on the display width. For display widths larger 610 * than 4096, you need use to use 2 display controllers and combine 611 * them using the stereo blender. 612 */ 613 if (amdgpu_crtc->base.enabled && mode) { 614 if (mode->crtc_hdisplay < 1920) { 615 mem_cfg = 1; 616 buffer_alloc = 2; 617 } else if (mode->crtc_hdisplay < 2560) { 618 mem_cfg = 2; 619 buffer_alloc = 2; 620 } else if (mode->crtc_hdisplay < 4096) { 621 mem_cfg = 0; 622 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 623 } else { 624 DRM_DEBUG_KMS("Mode too big for LB!\n"); 625 mem_cfg = 0; 626 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 627 } 628 } else { 629 mem_cfg = 1; 630 buffer_alloc = 0; 631 } 632 633 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 634 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 635 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 636 637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 638 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 639 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 640 641 for (i = 0; i < adev->usec_timeout; i++) { 642 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 643 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 644 break; 645 udelay(1); 646 } 647 648 if (amdgpu_crtc->base.enabled && mode) { 649 switch (mem_cfg) { 650 case 0: 651 default: 652 return 4096 * 2; 653 case 1: 654 return 1920 * 2; 655 case 2: 656 return 2560 * 2; 657 } 658 } 659 660 /* controller not enabled, so no lb used */ 661 return 0; 662 } 663 664 /** 665 * cik_get_number_of_dram_channels - get the number of dram channels 666 * 667 * @adev: amdgpu_device pointer 668 * 669 * Look up the number of video ram channels (CIK). 670 * Used for display watermark bandwidth calculations 671 * Returns the number of dram channels 672 */ 673 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 674 { 675 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 676 677 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 678 case 0: 679 default: 680 return 1; 681 case 1: 682 return 2; 683 case 2: 684 return 4; 685 case 3: 686 return 8; 687 case 4: 688 return 3; 689 case 5: 690 return 6; 691 case 6: 692 return 10; 693 case 7: 694 return 12; 695 case 8: 696 return 16; 697 } 698 } 699 700 struct dce10_wm_params { 701 u32 dram_channels; /* number of dram channels */ 702 u32 yclk; /* bandwidth per dram data pin in kHz */ 703 u32 sclk; /* engine clock in kHz */ 704 u32 disp_clk; /* display clock in kHz */ 705 u32 src_width; /* viewport width */ 706 u32 active_time; /* active display time in ns */ 707 u32 blank_time; /* blank time in ns */ 708 bool interlaced; /* mode is interlaced */ 709 fixed20_12 vsc; /* vertical scale ratio */ 710 u32 num_heads; /* number of active crtcs */ 711 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 712 u32 lb_size; /* line buffer allocated to pipe */ 713 u32 vtaps; /* vertical scaler taps */ 714 }; 715 716 /** 717 * dce_v10_0_dram_bandwidth - get the dram bandwidth 718 * 719 * @wm: watermark calculation data 720 * 721 * Calculate the raw dram bandwidth (CIK). 722 * Used for display watermark bandwidth calculations 723 * Returns the dram bandwidth in MBytes/s 724 */ 725 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 726 { 727 /* Calculate raw DRAM Bandwidth */ 728 fixed20_12 dram_efficiency; /* 0.7 */ 729 fixed20_12 yclk, dram_channels, bandwidth; 730 fixed20_12 a; 731 732 a.full = dfixed_const(1000); 733 yclk.full = dfixed_const(wm->yclk); 734 yclk.full = dfixed_div(yclk, a); 735 dram_channels.full = dfixed_const(wm->dram_channels * 4); 736 a.full = dfixed_const(10); 737 dram_efficiency.full = dfixed_const(7); 738 dram_efficiency.full = dfixed_div(dram_efficiency, a); 739 bandwidth.full = dfixed_mul(dram_channels, yclk); 740 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 741 742 return dfixed_trunc(bandwidth); 743 } 744 745 /** 746 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 747 * 748 * @wm: watermark calculation data 749 * 750 * Calculate the dram bandwidth used for display (CIK). 751 * Used for display watermark bandwidth calculations 752 * Returns the dram bandwidth for display in MBytes/s 753 */ 754 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 755 { 756 /* Calculate DRAM Bandwidth and the part allocated to display. */ 757 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 758 fixed20_12 yclk, dram_channels, bandwidth; 759 fixed20_12 a; 760 761 a.full = dfixed_const(1000); 762 yclk.full = dfixed_const(wm->yclk); 763 yclk.full = dfixed_div(yclk, a); 764 dram_channels.full = dfixed_const(wm->dram_channels * 4); 765 a.full = dfixed_const(10); 766 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 767 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 768 bandwidth.full = dfixed_mul(dram_channels, yclk); 769 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 770 771 return dfixed_trunc(bandwidth); 772 } 773 774 /** 775 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 776 * 777 * @wm: watermark calculation data 778 * 779 * Calculate the data return bandwidth used for display (CIK). 780 * Used for display watermark bandwidth calculations 781 * Returns the data return bandwidth in MBytes/s 782 */ 783 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 784 { 785 /* Calculate the display Data return Bandwidth */ 786 fixed20_12 return_efficiency; /* 0.8 */ 787 fixed20_12 sclk, bandwidth; 788 fixed20_12 a; 789 790 a.full = dfixed_const(1000); 791 sclk.full = dfixed_const(wm->sclk); 792 sclk.full = dfixed_div(sclk, a); 793 a.full = dfixed_const(10); 794 return_efficiency.full = dfixed_const(8); 795 return_efficiency.full = dfixed_div(return_efficiency, a); 796 a.full = dfixed_const(32); 797 bandwidth.full = dfixed_mul(a, sclk); 798 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 799 800 return dfixed_trunc(bandwidth); 801 } 802 803 /** 804 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 805 * 806 * @wm: watermark calculation data 807 * 808 * Calculate the dmif bandwidth used for display (CIK). 809 * Used for display watermark bandwidth calculations 810 * Returns the dmif bandwidth in MBytes/s 811 */ 812 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 813 { 814 /* Calculate the DMIF Request Bandwidth */ 815 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 816 fixed20_12 disp_clk, bandwidth; 817 fixed20_12 a, b; 818 819 a.full = dfixed_const(1000); 820 disp_clk.full = dfixed_const(wm->disp_clk); 821 disp_clk.full = dfixed_div(disp_clk, a); 822 a.full = dfixed_const(32); 823 b.full = dfixed_mul(a, disp_clk); 824 825 a.full = dfixed_const(10); 826 disp_clk_request_efficiency.full = dfixed_const(8); 827 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 828 829 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 830 831 return dfixed_trunc(bandwidth); 832 } 833 834 /** 835 * dce_v10_0_available_bandwidth - get the min available bandwidth 836 * 837 * @wm: watermark calculation data 838 * 839 * Calculate the min available bandwidth used for display (CIK). 840 * Used for display watermark bandwidth calculations 841 * Returns the min available bandwidth in MBytes/s 842 */ 843 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 844 { 845 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 846 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 847 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 848 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 849 850 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 851 } 852 853 /** 854 * dce_v10_0_average_bandwidth - get the average available bandwidth 855 * 856 * @wm: watermark calculation data 857 * 858 * Calculate the average available bandwidth used for display (CIK). 859 * Used for display watermark bandwidth calculations 860 * Returns the average available bandwidth in MBytes/s 861 */ 862 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 863 { 864 /* Calculate the display mode Average Bandwidth 865 * DisplayMode should contain the source and destination dimensions, 866 * timing, etc. 867 */ 868 fixed20_12 bpp; 869 fixed20_12 line_time; 870 fixed20_12 src_width; 871 fixed20_12 bandwidth; 872 fixed20_12 a; 873 874 a.full = dfixed_const(1000); 875 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 876 line_time.full = dfixed_div(line_time, a); 877 bpp.full = dfixed_const(wm->bytes_per_pixel); 878 src_width.full = dfixed_const(wm->src_width); 879 bandwidth.full = dfixed_mul(src_width, bpp); 880 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 881 bandwidth.full = dfixed_div(bandwidth, line_time); 882 883 return dfixed_trunc(bandwidth); 884 } 885 886 /** 887 * dce_v10_0_latency_watermark - get the latency watermark 888 * 889 * @wm: watermark calculation data 890 * 891 * Calculate the latency watermark (CIK). 892 * Used for display watermark bandwidth calculations 893 * Returns the latency watermark in ns 894 */ 895 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 896 { 897 /* First calculate the latency in ns */ 898 u32 mc_latency = 2000; /* 2000 ns. */ 899 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 900 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 901 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 902 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 903 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 904 (wm->num_heads * cursor_line_pair_return_time); 905 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 906 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 907 u32 tmp, dmif_size = 12288; 908 fixed20_12 a, b, c; 909 910 if (wm->num_heads == 0) 911 return 0; 912 913 a.full = dfixed_const(2); 914 b.full = dfixed_const(1); 915 if ((wm->vsc.full > a.full) || 916 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 917 (wm->vtaps >= 5) || 918 ((wm->vsc.full >= a.full) && wm->interlaced)) 919 max_src_lines_per_dst_line = 4; 920 else 921 max_src_lines_per_dst_line = 2; 922 923 a.full = dfixed_const(available_bandwidth); 924 b.full = dfixed_const(wm->num_heads); 925 a.full = dfixed_div(a, b); 926 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 927 tmp = min(dfixed_trunc(a), tmp); 928 929 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 930 931 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 932 b.full = dfixed_const(1000); 933 c.full = dfixed_const(lb_fill_bw); 934 b.full = dfixed_div(c, b); 935 a.full = dfixed_div(a, b); 936 line_fill_time = dfixed_trunc(a); 937 938 if (line_fill_time < wm->active_time) 939 return latency; 940 else 941 return latency + (line_fill_time - wm->active_time); 942 943 } 944 945 /** 946 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 947 * average and available dram bandwidth 948 * 949 * @wm: watermark calculation data 950 * 951 * Check if the display average bandwidth fits in the display 952 * dram bandwidth (CIK). 953 * Used for display watermark bandwidth calculations 954 * Returns true if the display fits, false if not. 955 */ 956 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 957 { 958 if (dce_v10_0_average_bandwidth(wm) <= 959 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 960 return true; 961 else 962 return false; 963 } 964 965 /** 966 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 967 * average and available bandwidth 968 * 969 * @wm: watermark calculation data 970 * 971 * Check if the display average bandwidth fits in the display 972 * available bandwidth (CIK). 973 * Used for display watermark bandwidth calculations 974 * Returns true if the display fits, false if not. 975 */ 976 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 977 { 978 if (dce_v10_0_average_bandwidth(wm) <= 979 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 980 return true; 981 else 982 return false; 983 } 984 985 /** 986 * dce_v10_0_check_latency_hiding - check latency hiding 987 * 988 * @wm: watermark calculation data 989 * 990 * Check latency hiding (CIK). 991 * Used for display watermark bandwidth calculations 992 * Returns true if the display fits, false if not. 993 */ 994 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 995 { 996 u32 lb_partitions = wm->lb_size / wm->src_width; 997 u32 line_time = wm->active_time + wm->blank_time; 998 u32 latency_tolerant_lines; 999 u32 latency_hiding; 1000 fixed20_12 a; 1001 1002 a.full = dfixed_const(1); 1003 if (wm->vsc.full > a.full) 1004 latency_tolerant_lines = 1; 1005 else { 1006 if (lb_partitions <= (wm->vtaps + 1)) 1007 latency_tolerant_lines = 1; 1008 else 1009 latency_tolerant_lines = 2; 1010 } 1011 1012 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1013 1014 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 1015 return true; 1016 else 1017 return false; 1018 } 1019 1020 /** 1021 * dce_v10_0_program_watermarks - program display watermarks 1022 * 1023 * @adev: amdgpu_device pointer 1024 * @amdgpu_crtc: the selected display controller 1025 * @lb_size: line buffer size 1026 * @num_heads: number of display controllers in use 1027 * 1028 * Calculate and program the display watermarks for the 1029 * selected display controller (CIK). 1030 */ 1031 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 1032 struct amdgpu_crtc *amdgpu_crtc, 1033 u32 lb_size, u32 num_heads) 1034 { 1035 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1036 struct dce10_wm_params wm_low, wm_high; 1037 u32 active_time; 1038 u32 line_time = 0; 1039 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1040 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1041 1042 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1043 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1044 (u32)mode->clock); 1045 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1046 (u32)mode->clock); 1047 line_time = min(line_time, (u32)65535); 1048 1049 /* watermark for high clocks */ 1050 if (adev->pm.dpm_enabled) { 1051 wm_high.yclk = 1052 amdgpu_dpm_get_mclk(adev, false) * 10; 1053 wm_high.sclk = 1054 amdgpu_dpm_get_sclk(adev, false) * 10; 1055 } else { 1056 wm_high.yclk = adev->pm.current_mclk * 10; 1057 wm_high.sclk = adev->pm.current_sclk * 10; 1058 } 1059 1060 wm_high.disp_clk = mode->clock; 1061 wm_high.src_width = mode->crtc_hdisplay; 1062 wm_high.active_time = active_time; 1063 wm_high.blank_time = line_time - wm_high.active_time; 1064 wm_high.interlaced = false; 1065 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1066 wm_high.interlaced = true; 1067 wm_high.vsc = amdgpu_crtc->vsc; 1068 wm_high.vtaps = 1; 1069 if (amdgpu_crtc->rmx_type != RMX_OFF) 1070 wm_high.vtaps = 2; 1071 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1072 wm_high.lb_size = lb_size; 1073 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1074 wm_high.num_heads = num_heads; 1075 1076 /* set for high clocks */ 1077 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); 1078 1079 /* possibly force display priority to high */ 1080 /* should really do this at mode validation time... */ 1081 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1082 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1083 !dce_v10_0_check_latency_hiding(&wm_high) || 1084 (adev->mode_info.disp_priority == 2)) { 1085 DRM_DEBUG_KMS("force priority to high\n"); 1086 } 1087 1088 /* watermark for low clocks */ 1089 if (adev->pm.dpm_enabled) { 1090 wm_low.yclk = 1091 amdgpu_dpm_get_mclk(adev, true) * 10; 1092 wm_low.sclk = 1093 amdgpu_dpm_get_sclk(adev, true) * 10; 1094 } else { 1095 wm_low.yclk = adev->pm.current_mclk * 10; 1096 wm_low.sclk = adev->pm.current_sclk * 10; 1097 } 1098 1099 wm_low.disp_clk = mode->clock; 1100 wm_low.src_width = mode->crtc_hdisplay; 1101 wm_low.active_time = active_time; 1102 wm_low.blank_time = line_time - wm_low.active_time; 1103 wm_low.interlaced = false; 1104 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1105 wm_low.interlaced = true; 1106 wm_low.vsc = amdgpu_crtc->vsc; 1107 wm_low.vtaps = 1; 1108 if (amdgpu_crtc->rmx_type != RMX_OFF) 1109 wm_low.vtaps = 2; 1110 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1111 wm_low.lb_size = lb_size; 1112 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1113 wm_low.num_heads = num_heads; 1114 1115 /* set for low clocks */ 1116 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); 1117 1118 /* possibly force display priority to high */ 1119 /* should really do this at mode validation time... */ 1120 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1121 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1122 !dce_v10_0_check_latency_hiding(&wm_low) || 1123 (adev->mode_info.disp_priority == 2)) { 1124 DRM_DEBUG_KMS("force priority to high\n"); 1125 } 1126 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1127 } 1128 1129 /* select wm A */ 1130 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1131 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1132 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1133 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1134 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1135 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1136 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1137 /* select wm B */ 1138 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1139 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1140 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1141 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1142 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1143 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1144 /* restore original selection */ 1145 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1146 1147 /* save values for DPM */ 1148 amdgpu_crtc->line_time = line_time; 1149 amdgpu_crtc->wm_high = latency_watermark_a; 1150 amdgpu_crtc->wm_low = latency_watermark_b; 1151 /* Save number of lines the linebuffer leads before the scanout */ 1152 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1153 } 1154 1155 /** 1156 * dce_v10_0_bandwidth_update - program display watermarks 1157 * 1158 * @adev: amdgpu_device pointer 1159 * 1160 * Calculate and program the display watermarks and line 1161 * buffer allocation (CIK). 1162 */ 1163 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1164 { 1165 struct drm_display_mode *mode = NULL; 1166 u32 num_heads = 0, lb_size; 1167 int i; 1168 1169 amdgpu_display_update_priority(adev); 1170 1171 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1172 if (adev->mode_info.crtcs[i]->base.enabled) 1173 num_heads++; 1174 } 1175 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1176 mode = &adev->mode_info.crtcs[i]->base.mode; 1177 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1178 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1179 lb_size, num_heads); 1180 } 1181 } 1182 1183 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1184 { 1185 int i; 1186 u32 offset, tmp; 1187 1188 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1189 offset = adev->mode_info.audio.pin[i].offset; 1190 tmp = RREG32_AUDIO_ENDPT(offset, 1191 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1192 if (((tmp & 1193 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1194 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1195 adev->mode_info.audio.pin[i].connected = false; 1196 else 1197 adev->mode_info.audio.pin[i].connected = true; 1198 } 1199 } 1200 1201 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1202 { 1203 int i; 1204 1205 dce_v10_0_audio_get_connected_pins(adev); 1206 1207 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1208 if (adev->mode_info.audio.pin[i].connected) 1209 return &adev->mode_info.audio.pin[i]; 1210 } 1211 DRM_ERROR("No connected audio pins found!\n"); 1212 return NULL; 1213 } 1214 1215 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1216 { 1217 struct amdgpu_device *adev = encoder->dev->dev_private; 1218 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1219 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1220 u32 tmp; 1221 1222 if (!dig || !dig->afmt || !dig->afmt->pin) 1223 return; 1224 1225 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1226 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1227 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1228 } 1229 1230 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1231 struct drm_display_mode *mode) 1232 { 1233 struct drm_device *dev = encoder->dev; 1234 struct amdgpu_device *adev = dev->dev_private; 1235 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1236 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1237 struct drm_connector *connector; 1238 struct drm_connector_list_iter iter; 1239 struct amdgpu_connector *amdgpu_connector = NULL; 1240 u32 tmp; 1241 int interlace = 0; 1242 1243 if (!dig || !dig->afmt || !dig->afmt->pin) 1244 return; 1245 1246 drm_connector_list_iter_begin(dev, &iter); 1247 drm_for_each_connector_iter(connector, &iter) { 1248 if (connector->encoder == encoder) { 1249 amdgpu_connector = to_amdgpu_connector(connector); 1250 break; 1251 } 1252 } 1253 drm_connector_list_iter_end(&iter); 1254 1255 if (!amdgpu_connector) { 1256 DRM_ERROR("Couldn't find encoder's connector\n"); 1257 return; 1258 } 1259 1260 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1261 interlace = 1; 1262 if (connector->latency_present[interlace]) { 1263 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1264 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1265 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1266 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1267 } else { 1268 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1269 VIDEO_LIPSYNC, 0); 1270 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1271 AUDIO_LIPSYNC, 0); 1272 } 1273 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1274 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1275 } 1276 1277 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1278 { 1279 struct drm_device *dev = encoder->dev; 1280 struct amdgpu_device *adev = dev->dev_private; 1281 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1282 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1283 struct drm_connector *connector; 1284 struct drm_connector_list_iter iter; 1285 struct amdgpu_connector *amdgpu_connector = NULL; 1286 u32 tmp; 1287 u8 *sadb = NULL; 1288 int sad_count; 1289 1290 if (!dig || !dig->afmt || !dig->afmt->pin) 1291 return; 1292 1293 drm_connector_list_iter_begin(dev, &iter); 1294 drm_for_each_connector_iter(connector, &iter) { 1295 if (connector->encoder == encoder) { 1296 amdgpu_connector = to_amdgpu_connector(connector); 1297 break; 1298 } 1299 } 1300 drm_connector_list_iter_end(&iter); 1301 1302 if (!amdgpu_connector) { 1303 DRM_ERROR("Couldn't find encoder's connector\n"); 1304 return; 1305 } 1306 1307 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1308 if (sad_count < 0) { 1309 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1310 sad_count = 0; 1311 } 1312 1313 /* program the speaker allocation */ 1314 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1315 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1317 DP_CONNECTION, 0); 1318 /* set HDMI mode */ 1319 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1320 HDMI_CONNECTION, 1); 1321 if (sad_count) 1322 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1323 SPEAKER_ALLOCATION, sadb[0]); 1324 else 1325 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1326 SPEAKER_ALLOCATION, 5); /* stereo */ 1327 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1328 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1329 1330 kfree(sadb); 1331 } 1332 1333 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1334 { 1335 struct drm_device *dev = encoder->dev; 1336 struct amdgpu_device *adev = dev->dev_private; 1337 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1338 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1339 struct drm_connector *connector; 1340 struct drm_connector_list_iter iter; 1341 struct amdgpu_connector *amdgpu_connector = NULL; 1342 struct cea_sad *sads; 1343 int i, sad_count; 1344 1345 static const u16 eld_reg_to_type[][2] = { 1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1355 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1356 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1357 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1358 }; 1359 1360 if (!dig || !dig->afmt || !dig->afmt->pin) 1361 return; 1362 1363 drm_connector_list_iter_begin(dev, &iter); 1364 drm_for_each_connector_iter(connector, &iter) { 1365 if (connector->encoder == encoder) { 1366 amdgpu_connector = to_amdgpu_connector(connector); 1367 break; 1368 } 1369 } 1370 drm_connector_list_iter_end(&iter); 1371 1372 if (!amdgpu_connector) { 1373 DRM_ERROR("Couldn't find encoder's connector\n"); 1374 return; 1375 } 1376 1377 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1378 if (sad_count < 0) 1379 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1380 if (sad_count <= 0) 1381 return; 1382 BUG_ON(!sads); 1383 1384 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1385 u32 tmp = 0; 1386 u8 stereo_freqs = 0; 1387 int max_channels = -1; 1388 int j; 1389 1390 for (j = 0; j < sad_count; j++) { 1391 struct cea_sad *sad = &sads[j]; 1392 1393 if (sad->format == eld_reg_to_type[i][1]) { 1394 if (sad->channels > max_channels) { 1395 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1396 MAX_CHANNELS, sad->channels); 1397 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1398 DESCRIPTOR_BYTE_2, sad->byte2); 1399 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1400 SUPPORTED_FREQUENCIES, sad->freq); 1401 max_channels = sad->channels; 1402 } 1403 1404 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1405 stereo_freqs |= sad->freq; 1406 else 1407 break; 1408 } 1409 } 1410 1411 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1412 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1413 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1414 } 1415 1416 kfree(sads); 1417 } 1418 1419 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1420 struct amdgpu_audio_pin *pin, 1421 bool enable) 1422 { 1423 if (!pin) 1424 return; 1425 1426 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1427 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1428 } 1429 1430 static const u32 pin_offsets[] = 1431 { 1432 AUD0_REGISTER_OFFSET, 1433 AUD1_REGISTER_OFFSET, 1434 AUD2_REGISTER_OFFSET, 1435 AUD3_REGISTER_OFFSET, 1436 AUD4_REGISTER_OFFSET, 1437 AUD5_REGISTER_OFFSET, 1438 AUD6_REGISTER_OFFSET, 1439 }; 1440 1441 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1442 { 1443 int i; 1444 1445 if (!amdgpu_audio) 1446 return 0; 1447 1448 adev->mode_info.audio.enabled = true; 1449 1450 adev->mode_info.audio.num_pins = 7; 1451 1452 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1453 adev->mode_info.audio.pin[i].channels = -1; 1454 adev->mode_info.audio.pin[i].rate = -1; 1455 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1456 adev->mode_info.audio.pin[i].status_bits = 0; 1457 adev->mode_info.audio.pin[i].category_code = 0; 1458 adev->mode_info.audio.pin[i].connected = false; 1459 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1460 adev->mode_info.audio.pin[i].id = i; 1461 /* disable audio. it will be set up later */ 1462 /* XXX remove once we switch to ip funcs */ 1463 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1464 } 1465 1466 return 0; 1467 } 1468 1469 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1470 { 1471 int i; 1472 1473 if (!amdgpu_audio) 1474 return; 1475 1476 if (!adev->mode_info.audio.enabled) 1477 return; 1478 1479 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1480 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1481 1482 adev->mode_info.audio.enabled = false; 1483 } 1484 1485 /* 1486 * update the N and CTS parameters for a given pixel clock rate 1487 */ 1488 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1489 { 1490 struct drm_device *dev = encoder->dev; 1491 struct amdgpu_device *adev = dev->dev_private; 1492 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1494 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1495 u32 tmp; 1496 1497 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1498 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1499 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1500 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1501 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1502 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1503 1504 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1505 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1506 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1507 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1508 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1509 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1510 1511 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1513 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1514 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1515 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1516 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1517 1518 } 1519 1520 /* 1521 * build a HDMI Video Info Frame 1522 */ 1523 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1524 void *buffer, size_t size) 1525 { 1526 struct drm_device *dev = encoder->dev; 1527 struct amdgpu_device *adev = dev->dev_private; 1528 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1529 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1530 uint8_t *frame = buffer + 3; 1531 uint8_t *header = buffer; 1532 1533 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1534 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1535 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1536 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1537 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1538 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1539 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1540 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1541 } 1542 1543 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1544 { 1545 struct drm_device *dev = encoder->dev; 1546 struct amdgpu_device *adev = dev->dev_private; 1547 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1548 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1549 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1550 u32 dto_phase = 24 * 1000; 1551 u32 dto_modulo = clock; 1552 u32 tmp; 1553 1554 if (!dig || !dig->afmt) 1555 return; 1556 1557 /* XXX two dtos; generally use dto0 for hdmi */ 1558 /* Express [24MHz / target pixel clock] as an exact rational 1559 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1560 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1561 */ 1562 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1563 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1564 amdgpu_crtc->crtc_id); 1565 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1566 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1567 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1568 } 1569 1570 /* 1571 * update the info frames with the data from the current display mode 1572 */ 1573 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1574 struct drm_display_mode *mode) 1575 { 1576 struct drm_device *dev = encoder->dev; 1577 struct amdgpu_device *adev = dev->dev_private; 1578 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1579 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1580 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1581 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1582 struct hdmi_avi_infoframe frame; 1583 ssize_t err; 1584 u32 tmp; 1585 int bpc = 8; 1586 1587 if (!dig || !dig->afmt) 1588 return; 1589 1590 /* Silent, r600_hdmi_enable will raise WARN for us */ 1591 if (!dig->afmt->enabled) 1592 return; 1593 1594 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1595 if (encoder->crtc) { 1596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1597 bpc = amdgpu_crtc->bpc; 1598 } 1599 1600 /* disable audio prior to setting up hw */ 1601 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1602 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1603 1604 dce_v10_0_audio_set_dto(encoder, mode->clock); 1605 1606 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1607 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1608 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1609 1610 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1611 1612 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1613 switch (bpc) { 1614 case 0: 1615 case 6: 1616 case 8: 1617 case 16: 1618 default: 1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1621 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1622 connector->name, bpc); 1623 break; 1624 case 10: 1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1627 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1628 connector->name); 1629 break; 1630 case 12: 1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1632 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1633 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1634 connector->name); 1635 break; 1636 } 1637 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1638 1639 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1640 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1641 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1642 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1643 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1644 1645 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1646 /* enable audio info frames (frames won't be set until audio is enabled) */ 1647 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1648 /* required for audio info values to be updated */ 1649 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1650 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1651 1652 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1653 /* required for audio info values to be updated */ 1654 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1655 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1656 1657 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1658 /* anything other than 0 */ 1659 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1660 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1661 1662 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1663 1664 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1665 /* set the default audio delay */ 1666 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1667 /* should be suffient for all audio modes and small enough for all hblanks */ 1668 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1669 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1670 1671 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1672 /* allow 60958 channel status fields to be updated */ 1673 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1674 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1675 1676 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1677 if (bpc > 8) 1678 /* clear SW CTS value */ 1679 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1680 else 1681 /* select SW CTS value */ 1682 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1683 /* allow hw to sent ACR packets when required */ 1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1685 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1686 1687 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1688 1689 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1690 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1691 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1692 1693 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1694 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1695 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1696 1697 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1698 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1699 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1700 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1701 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1702 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1703 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1704 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1705 1706 dce_v10_0_audio_write_speaker_allocation(encoder); 1707 1708 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1709 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1710 1711 dce_v10_0_afmt_audio_select_pin(encoder); 1712 dce_v10_0_audio_write_sad_regs(encoder); 1713 dce_v10_0_audio_write_latency_fields(encoder, mode); 1714 1715 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1716 if (err < 0) { 1717 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1718 return; 1719 } 1720 1721 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1722 if (err < 0) { 1723 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1724 return; 1725 } 1726 1727 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1728 1729 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1730 /* enable AVI info frames */ 1731 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1732 /* required for audio info values to be updated */ 1733 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1734 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1735 1736 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1737 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1738 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1739 1740 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1741 /* send audio packets */ 1742 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1743 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1744 1745 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1746 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1747 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1748 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1749 1750 /* enable audio after to setting up hw */ 1751 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 1752 } 1753 1754 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1755 { 1756 struct drm_device *dev = encoder->dev; 1757 struct amdgpu_device *adev = dev->dev_private; 1758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1759 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1760 1761 if (!dig || !dig->afmt) 1762 return; 1763 1764 /* Silent, r600_hdmi_enable will raise WARN for us */ 1765 if (enable && dig->afmt->enabled) 1766 return; 1767 if (!enable && !dig->afmt->enabled) 1768 return; 1769 1770 if (!enable && dig->afmt->pin) { 1771 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1772 dig->afmt->pin = NULL; 1773 } 1774 1775 dig->afmt->enabled = enable; 1776 1777 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1778 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1779 } 1780 1781 static int dce_v10_0_afmt_init(struct amdgpu_device *adev) 1782 { 1783 int i; 1784 1785 for (i = 0; i < adev->mode_info.num_dig; i++) 1786 adev->mode_info.afmt[i] = NULL; 1787 1788 /* DCE10 has audio blocks tied to DIG encoders */ 1789 for (i = 0; i < adev->mode_info.num_dig; i++) { 1790 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1791 if (adev->mode_info.afmt[i]) { 1792 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1793 adev->mode_info.afmt[i]->id = i; 1794 } else { 1795 int j; 1796 for (j = 0; j < i; j++) { 1797 kfree(adev->mode_info.afmt[j]); 1798 adev->mode_info.afmt[j] = NULL; 1799 } 1800 return -ENOMEM; 1801 } 1802 } 1803 return 0; 1804 } 1805 1806 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 1807 { 1808 int i; 1809 1810 for (i = 0; i < adev->mode_info.num_dig; i++) { 1811 kfree(adev->mode_info.afmt[i]); 1812 adev->mode_info.afmt[i] = NULL; 1813 } 1814 } 1815 1816 static const u32 vga_control_regs[6] = 1817 { 1818 mmD1VGA_CONTROL, 1819 mmD2VGA_CONTROL, 1820 mmD3VGA_CONTROL, 1821 mmD4VGA_CONTROL, 1822 mmD5VGA_CONTROL, 1823 mmD6VGA_CONTROL, 1824 }; 1825 1826 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 1827 { 1828 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1829 struct drm_device *dev = crtc->dev; 1830 struct amdgpu_device *adev = dev->dev_private; 1831 u32 vga_control; 1832 1833 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1834 if (enable) 1835 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1836 else 1837 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1838 } 1839 1840 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 1841 { 1842 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1843 struct drm_device *dev = crtc->dev; 1844 struct amdgpu_device *adev = dev->dev_private; 1845 1846 if (enable) 1847 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1848 else 1849 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1850 } 1851 1852 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 1853 struct drm_framebuffer *fb, 1854 int x, int y, int atomic) 1855 { 1856 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1857 struct drm_device *dev = crtc->dev; 1858 struct amdgpu_device *adev = dev->dev_private; 1859 struct drm_framebuffer *target_fb; 1860 struct drm_gem_object *obj; 1861 struct amdgpu_bo *abo; 1862 uint64_t fb_location, tiling_flags; 1863 uint32_t fb_format, fb_pitch_pixels; 1864 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1865 u32 pipe_config; 1866 u32 tmp, viewport_w, viewport_h; 1867 int r; 1868 bool bypass_lut = false; 1869 struct drm_format_name_buf format_name; 1870 1871 /* no fb bound */ 1872 if (!atomic && !crtc->primary->fb) { 1873 DRM_DEBUG_KMS("No FB bound\n"); 1874 return 0; 1875 } 1876 1877 if (atomic) 1878 target_fb = fb; 1879 else 1880 target_fb = crtc->primary->fb; 1881 1882 /* If atomic, assume fb object is pinned & idle & fenced and 1883 * just update base pointers 1884 */ 1885 obj = target_fb->obj[0]; 1886 abo = gem_to_amdgpu_bo(obj); 1887 r = amdgpu_bo_reserve(abo, false); 1888 if (unlikely(r != 0)) 1889 return r; 1890 1891 if (!atomic) { 1892 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1893 if (unlikely(r != 0)) { 1894 amdgpu_bo_unreserve(abo); 1895 return -EINVAL; 1896 } 1897 } 1898 fb_location = amdgpu_bo_gpu_offset(abo); 1899 1900 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1901 amdgpu_bo_unreserve(abo); 1902 1903 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1904 1905 switch (target_fb->format->format) { 1906 case DRM_FORMAT_C8: 1907 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1908 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1909 break; 1910 case DRM_FORMAT_XRGB4444: 1911 case DRM_FORMAT_ARGB4444: 1912 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1913 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1914 #ifdef __BIG_ENDIAN 1915 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1916 ENDIAN_8IN16); 1917 #endif 1918 break; 1919 case DRM_FORMAT_XRGB1555: 1920 case DRM_FORMAT_ARGB1555: 1921 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1922 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1923 #ifdef __BIG_ENDIAN 1924 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1925 ENDIAN_8IN16); 1926 #endif 1927 break; 1928 case DRM_FORMAT_BGRX5551: 1929 case DRM_FORMAT_BGRA5551: 1930 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1931 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1932 #ifdef __BIG_ENDIAN 1933 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1934 ENDIAN_8IN16); 1935 #endif 1936 break; 1937 case DRM_FORMAT_RGB565: 1938 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1939 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1940 #ifdef __BIG_ENDIAN 1941 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1942 ENDIAN_8IN16); 1943 #endif 1944 break; 1945 case DRM_FORMAT_XRGB8888: 1946 case DRM_FORMAT_ARGB8888: 1947 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1948 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1949 #ifdef __BIG_ENDIAN 1950 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1951 ENDIAN_8IN32); 1952 #endif 1953 break; 1954 case DRM_FORMAT_XRGB2101010: 1955 case DRM_FORMAT_ARGB2101010: 1956 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1957 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1958 #ifdef __BIG_ENDIAN 1959 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1960 ENDIAN_8IN32); 1961 #endif 1962 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1963 bypass_lut = true; 1964 break; 1965 case DRM_FORMAT_BGRX1010102: 1966 case DRM_FORMAT_BGRA1010102: 1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 1969 #ifdef __BIG_ENDIAN 1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1971 ENDIAN_8IN32); 1972 #endif 1973 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1974 bypass_lut = true; 1975 break; 1976 case DRM_FORMAT_XBGR8888: 1977 case DRM_FORMAT_ABGR8888: 1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1980 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); 1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); 1982 #ifdef __BIG_ENDIAN 1983 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1984 ENDIAN_8IN32); 1985 #endif 1986 break; 1987 default: 1988 DRM_ERROR("Unsupported screen format %s\n", 1989 drm_get_format_name(target_fb->format->format, &format_name)); 1990 return -EINVAL; 1991 } 1992 1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1995 1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2001 2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2004 ARRAY_2D_TILED_THIN1); 2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2006 tile_split); 2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2009 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2010 mtaspect); 2011 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2012 ADDR_SURF_MICRO_TILING_DISPLAY); 2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2015 ARRAY_1D_TILED_THIN1); 2016 } 2017 2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2019 pipe_config); 2020 2021 dce_v10_0_vga_enable(crtc, false); 2022 2023 /* Make sure surface address is updated at vertical blank rather than 2024 * horizontal blank 2025 */ 2026 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2027 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2028 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2029 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2030 2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2032 upper_32_bits(fb_location)); 2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2034 upper_32_bits(fb_location)); 2035 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2036 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2037 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2038 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2040 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2041 2042 /* 2043 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2044 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2045 * retain the full precision throughout the pipeline. 2046 */ 2047 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2048 if (bypass_lut) 2049 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2050 else 2051 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2052 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2053 2054 if (bypass_lut) 2055 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2056 2057 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2058 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2059 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2060 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2061 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2062 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2063 2064 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2065 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2066 2067 dce_v10_0_grph_enable(crtc, true); 2068 2069 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2070 target_fb->height); 2071 2072 x &= ~3; 2073 y &= ~1; 2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2075 (x << 16) | y); 2076 viewport_w = crtc->mode.hdisplay; 2077 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2078 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2079 (viewport_w << 16) | viewport_h); 2080 2081 /* set pageflip to happen anywhere in vblank interval */ 2082 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2083 2084 if (!atomic && fb && fb != crtc->primary->fb) { 2085 abo = gem_to_amdgpu_bo(fb->obj[0]); 2086 r = amdgpu_bo_reserve(abo, true); 2087 if (unlikely(r != 0)) 2088 return r; 2089 amdgpu_bo_unpin(abo); 2090 amdgpu_bo_unreserve(abo); 2091 } 2092 2093 /* Bytes per pixel may have changed */ 2094 dce_v10_0_bandwidth_update(adev); 2095 2096 return 0; 2097 } 2098 2099 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2100 struct drm_display_mode *mode) 2101 { 2102 struct drm_device *dev = crtc->dev; 2103 struct amdgpu_device *adev = dev->dev_private; 2104 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2105 u32 tmp; 2106 2107 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2108 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2109 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2110 else 2111 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2112 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2113 } 2114 2115 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2116 { 2117 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2118 struct drm_device *dev = crtc->dev; 2119 struct amdgpu_device *adev = dev->dev_private; 2120 u16 *r, *g, *b; 2121 int i; 2122 u32 tmp; 2123 2124 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2125 2126 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2127 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2128 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2129 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2130 2131 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2132 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2133 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2134 2135 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2136 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2137 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2138 2139 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2140 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2141 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2142 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2143 2144 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2145 2146 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2147 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2148 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2149 2150 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2151 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2152 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2153 2154 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2155 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2156 2157 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2158 r = crtc->gamma_store; 2159 g = r + crtc->gamma_size; 2160 b = g + crtc->gamma_size; 2161 for (i = 0; i < 256; i++) { 2162 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2163 ((*r++ & 0xffc0) << 14) | 2164 ((*g++ & 0xffc0) << 4) | 2165 (*b++ >> 6)); 2166 } 2167 2168 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2169 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2170 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2171 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2172 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2173 2174 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2175 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2176 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2177 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2178 2179 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2180 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2181 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2182 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2183 2184 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2185 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2186 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2187 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2188 2189 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2190 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2191 /* XXX this only needs to be programmed once per crtc at startup, 2192 * not sure where the best place for it is 2193 */ 2194 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2195 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2196 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2197 } 2198 2199 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2200 { 2201 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2202 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2203 2204 switch (amdgpu_encoder->encoder_id) { 2205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2206 if (dig->linkb) 2207 return 1; 2208 else 2209 return 0; 2210 break; 2211 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2212 if (dig->linkb) 2213 return 3; 2214 else 2215 return 2; 2216 break; 2217 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2218 if (dig->linkb) 2219 return 5; 2220 else 2221 return 4; 2222 break; 2223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2224 return 6; 2225 break; 2226 default: 2227 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2228 return 0; 2229 } 2230 } 2231 2232 /** 2233 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2234 * 2235 * @crtc: drm crtc 2236 * 2237 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2238 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2239 * monitors a dedicated PPLL must be used. If a particular board has 2240 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2241 * as there is no need to program the PLL itself. If we are not able to 2242 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2243 * avoid messing up an existing monitor. 2244 * 2245 * Asic specific PLL information 2246 * 2247 * DCE 10.x 2248 * Tonga 2249 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2250 * CI 2251 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2252 * 2253 */ 2254 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2255 { 2256 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2257 struct drm_device *dev = crtc->dev; 2258 struct amdgpu_device *adev = dev->dev_private; 2259 u32 pll_in_use; 2260 int pll; 2261 2262 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2263 if (adev->clock.dp_extclk) 2264 /* skip PPLL programming if using ext clock */ 2265 return ATOM_PPLL_INVALID; 2266 else { 2267 /* use the same PPLL for all DP monitors */ 2268 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2269 if (pll != ATOM_PPLL_INVALID) 2270 return pll; 2271 } 2272 } else { 2273 /* use the same PPLL for all monitors with the same clock */ 2274 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2275 if (pll != ATOM_PPLL_INVALID) 2276 return pll; 2277 } 2278 2279 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2280 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2281 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2282 return ATOM_PPLL2; 2283 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2284 return ATOM_PPLL1; 2285 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2286 return ATOM_PPLL0; 2287 DRM_ERROR("unable to allocate a PPLL\n"); 2288 return ATOM_PPLL_INVALID; 2289 } 2290 2291 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2292 { 2293 struct amdgpu_device *adev = crtc->dev->dev_private; 2294 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2295 uint32_t cur_lock; 2296 2297 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2298 if (lock) 2299 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2300 else 2301 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2302 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2303 } 2304 2305 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2306 { 2307 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2308 struct amdgpu_device *adev = crtc->dev->dev_private; 2309 u32 tmp; 2310 2311 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2312 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2313 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2314 } 2315 2316 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2317 { 2318 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2319 struct amdgpu_device *adev = crtc->dev->dev_private; 2320 u32 tmp; 2321 2322 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2323 upper_32_bits(amdgpu_crtc->cursor_addr)); 2324 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2325 lower_32_bits(amdgpu_crtc->cursor_addr)); 2326 2327 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2328 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2329 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2330 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2331 } 2332 2333 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 2334 int x, int y) 2335 { 2336 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2337 struct amdgpu_device *adev = crtc->dev->dev_private; 2338 int xorigin = 0, yorigin = 0; 2339 2340 amdgpu_crtc->cursor_x = x; 2341 amdgpu_crtc->cursor_y = y; 2342 2343 /* avivo cursor are offset into the total surface */ 2344 x += crtc->x; 2345 y += crtc->y; 2346 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2347 2348 if (x < 0) { 2349 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2350 x = 0; 2351 } 2352 if (y < 0) { 2353 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2354 y = 0; 2355 } 2356 2357 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2358 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2359 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2360 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2361 2362 return 0; 2363 } 2364 2365 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2366 int x, int y) 2367 { 2368 int ret; 2369 2370 dce_v10_0_lock_cursor(crtc, true); 2371 ret = dce_v10_0_cursor_move_locked(crtc, x, y); 2372 dce_v10_0_lock_cursor(crtc, false); 2373 2374 return ret; 2375 } 2376 2377 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 2378 struct drm_file *file_priv, 2379 uint32_t handle, 2380 uint32_t width, 2381 uint32_t height, 2382 int32_t hot_x, 2383 int32_t hot_y) 2384 { 2385 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2386 struct drm_gem_object *obj; 2387 struct amdgpu_bo *aobj; 2388 int ret; 2389 2390 if (!handle) { 2391 /* turn off cursor */ 2392 dce_v10_0_hide_cursor(crtc); 2393 obj = NULL; 2394 goto unpin; 2395 } 2396 2397 if ((width > amdgpu_crtc->max_cursor_width) || 2398 (height > amdgpu_crtc->max_cursor_height)) { 2399 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2400 return -EINVAL; 2401 } 2402 2403 obj = drm_gem_object_lookup(file_priv, handle); 2404 if (!obj) { 2405 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2406 return -ENOENT; 2407 } 2408 2409 aobj = gem_to_amdgpu_bo(obj); 2410 ret = amdgpu_bo_reserve(aobj, false); 2411 if (ret != 0) { 2412 drm_gem_object_put_unlocked(obj); 2413 return ret; 2414 } 2415 2416 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2417 amdgpu_bo_unreserve(aobj); 2418 if (ret) { 2419 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2420 drm_gem_object_put_unlocked(obj); 2421 return ret; 2422 } 2423 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2424 2425 dce_v10_0_lock_cursor(crtc, true); 2426 2427 if (width != amdgpu_crtc->cursor_width || 2428 height != amdgpu_crtc->cursor_height || 2429 hot_x != amdgpu_crtc->cursor_hot_x || 2430 hot_y != amdgpu_crtc->cursor_hot_y) { 2431 int x, y; 2432 2433 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2434 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2435 2436 dce_v10_0_cursor_move_locked(crtc, x, y); 2437 2438 amdgpu_crtc->cursor_width = width; 2439 amdgpu_crtc->cursor_height = height; 2440 amdgpu_crtc->cursor_hot_x = hot_x; 2441 amdgpu_crtc->cursor_hot_y = hot_y; 2442 } 2443 2444 dce_v10_0_show_cursor(crtc); 2445 dce_v10_0_lock_cursor(crtc, false); 2446 2447 unpin: 2448 if (amdgpu_crtc->cursor_bo) { 2449 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2450 ret = amdgpu_bo_reserve(aobj, true); 2451 if (likely(ret == 0)) { 2452 amdgpu_bo_unpin(aobj); 2453 amdgpu_bo_unreserve(aobj); 2454 } 2455 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); 2456 } 2457 2458 amdgpu_crtc->cursor_bo = obj; 2459 return 0; 2460 } 2461 2462 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2463 { 2464 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2465 2466 if (amdgpu_crtc->cursor_bo) { 2467 dce_v10_0_lock_cursor(crtc, true); 2468 2469 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2470 amdgpu_crtc->cursor_y); 2471 2472 dce_v10_0_show_cursor(crtc); 2473 2474 dce_v10_0_lock_cursor(crtc, false); 2475 } 2476 } 2477 2478 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2479 u16 *blue, uint32_t size, 2480 struct drm_modeset_acquire_ctx *ctx) 2481 { 2482 dce_v10_0_crtc_load_lut(crtc); 2483 2484 return 0; 2485 } 2486 2487 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2488 { 2489 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2490 2491 drm_crtc_cleanup(crtc); 2492 kfree(amdgpu_crtc); 2493 } 2494 2495 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2496 .cursor_set2 = dce_v10_0_crtc_cursor_set2, 2497 .cursor_move = dce_v10_0_crtc_cursor_move, 2498 .gamma_set = dce_v10_0_crtc_gamma_set, 2499 .set_config = amdgpu_display_crtc_set_config, 2500 .destroy = dce_v10_0_crtc_destroy, 2501 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2502 }; 2503 2504 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2505 { 2506 struct drm_device *dev = crtc->dev; 2507 struct amdgpu_device *adev = dev->dev_private; 2508 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2509 unsigned type; 2510 2511 switch (mode) { 2512 case DRM_MODE_DPMS_ON: 2513 amdgpu_crtc->enabled = true; 2514 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2515 dce_v10_0_vga_enable(crtc, true); 2516 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2517 dce_v10_0_vga_enable(crtc, false); 2518 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2519 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2520 amdgpu_crtc->crtc_id); 2521 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2522 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2523 drm_crtc_vblank_on(crtc); 2524 dce_v10_0_crtc_load_lut(crtc); 2525 break; 2526 case DRM_MODE_DPMS_STANDBY: 2527 case DRM_MODE_DPMS_SUSPEND: 2528 case DRM_MODE_DPMS_OFF: 2529 drm_crtc_vblank_off(crtc); 2530 if (amdgpu_crtc->enabled) { 2531 dce_v10_0_vga_enable(crtc, true); 2532 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2533 dce_v10_0_vga_enable(crtc, false); 2534 } 2535 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2536 amdgpu_crtc->enabled = false; 2537 break; 2538 } 2539 /* adjust pm to dpms */ 2540 amdgpu_pm_compute_clocks(adev); 2541 } 2542 2543 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2544 { 2545 /* disable crtc pair power gating before programming */ 2546 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2547 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2548 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2549 } 2550 2551 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2552 { 2553 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2554 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2555 } 2556 2557 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2558 { 2559 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2560 struct drm_device *dev = crtc->dev; 2561 struct amdgpu_device *adev = dev->dev_private; 2562 struct amdgpu_atom_ss ss; 2563 int i; 2564 2565 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2566 if (crtc->primary->fb) { 2567 int r; 2568 struct amdgpu_bo *abo; 2569 2570 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2571 r = amdgpu_bo_reserve(abo, true); 2572 if (unlikely(r)) 2573 DRM_ERROR("failed to reserve abo before unpin\n"); 2574 else { 2575 amdgpu_bo_unpin(abo); 2576 amdgpu_bo_unreserve(abo); 2577 } 2578 } 2579 /* disable the GRPH */ 2580 dce_v10_0_grph_enable(crtc, false); 2581 2582 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2583 2584 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2585 if (adev->mode_info.crtcs[i] && 2586 adev->mode_info.crtcs[i]->enabled && 2587 i != amdgpu_crtc->crtc_id && 2588 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2589 /* one other crtc is using this pll don't turn 2590 * off the pll 2591 */ 2592 goto done; 2593 } 2594 } 2595 2596 switch (amdgpu_crtc->pll_id) { 2597 case ATOM_PPLL0: 2598 case ATOM_PPLL1: 2599 case ATOM_PPLL2: 2600 /* disable the ppll */ 2601 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2602 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2603 break; 2604 default: 2605 break; 2606 } 2607 done: 2608 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2609 amdgpu_crtc->adjusted_clock = 0; 2610 amdgpu_crtc->encoder = NULL; 2611 amdgpu_crtc->connector = NULL; 2612 } 2613 2614 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2615 struct drm_display_mode *mode, 2616 struct drm_display_mode *adjusted_mode, 2617 int x, int y, struct drm_framebuffer *old_fb) 2618 { 2619 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2620 2621 if (!amdgpu_crtc->adjusted_clock) 2622 return -EINVAL; 2623 2624 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2625 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2626 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2627 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2628 amdgpu_atombios_crtc_scaler_setup(crtc); 2629 dce_v10_0_cursor_reset(crtc); 2630 /* update the hw version fpr dpm */ 2631 amdgpu_crtc->hw_mode = *adjusted_mode; 2632 2633 return 0; 2634 } 2635 2636 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2637 const struct drm_display_mode *mode, 2638 struct drm_display_mode *adjusted_mode) 2639 { 2640 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2641 struct drm_device *dev = crtc->dev; 2642 struct drm_encoder *encoder; 2643 2644 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2645 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2646 if (encoder->crtc == crtc) { 2647 amdgpu_crtc->encoder = encoder; 2648 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2649 break; 2650 } 2651 } 2652 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2653 amdgpu_crtc->encoder = NULL; 2654 amdgpu_crtc->connector = NULL; 2655 return false; 2656 } 2657 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2658 return false; 2659 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2660 return false; 2661 /* pick pll */ 2662 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2663 /* if we can't get a PPLL for a non-DP encoder, fail */ 2664 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2665 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2666 return false; 2667 2668 return true; 2669 } 2670 2671 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2672 struct drm_framebuffer *old_fb) 2673 { 2674 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2675 } 2676 2677 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2678 struct drm_framebuffer *fb, 2679 int x, int y, enum mode_set_atomic state) 2680 { 2681 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); 2682 } 2683 2684 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2685 .dpms = dce_v10_0_crtc_dpms, 2686 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2687 .mode_set = dce_v10_0_crtc_mode_set, 2688 .mode_set_base = dce_v10_0_crtc_set_base, 2689 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, 2690 .prepare = dce_v10_0_crtc_prepare, 2691 .commit = dce_v10_0_crtc_commit, 2692 .disable = dce_v10_0_crtc_disable, 2693 }; 2694 2695 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2696 { 2697 struct amdgpu_crtc *amdgpu_crtc; 2698 2699 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2700 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2701 if (amdgpu_crtc == NULL) 2702 return -ENOMEM; 2703 2704 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2705 2706 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2707 amdgpu_crtc->crtc_id = index; 2708 adev->mode_info.crtcs[index] = amdgpu_crtc; 2709 2710 amdgpu_crtc->max_cursor_width = 128; 2711 amdgpu_crtc->max_cursor_height = 128; 2712 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2713 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2714 2715 switch (amdgpu_crtc->crtc_id) { 2716 case 0: 2717 default: 2718 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2719 break; 2720 case 1: 2721 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2722 break; 2723 case 2: 2724 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2725 break; 2726 case 3: 2727 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2728 break; 2729 case 4: 2730 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2731 break; 2732 case 5: 2733 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2734 break; 2735 } 2736 2737 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2738 amdgpu_crtc->adjusted_clock = 0; 2739 amdgpu_crtc->encoder = NULL; 2740 amdgpu_crtc->connector = NULL; 2741 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2742 2743 return 0; 2744 } 2745 2746 static int dce_v10_0_early_init(void *handle) 2747 { 2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2749 2750 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2751 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2752 2753 dce_v10_0_set_display_funcs(adev); 2754 2755 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); 2756 2757 switch (adev->asic_type) { 2758 case CHIP_FIJI: 2759 case CHIP_TONGA: 2760 adev->mode_info.num_hpd = 6; 2761 adev->mode_info.num_dig = 7; 2762 break; 2763 default: 2764 /* FIXME: not supported yet */ 2765 return -EINVAL; 2766 } 2767 2768 dce_v10_0_set_irq_funcs(adev); 2769 2770 return 0; 2771 } 2772 2773 static int dce_v10_0_sw_init(void *handle) 2774 { 2775 int r, i; 2776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2777 2778 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2779 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2780 if (r) 2781 return r; 2782 } 2783 2784 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2785 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2786 if (r) 2787 return r; 2788 } 2789 2790 /* HPD hotplug */ 2791 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2792 if (r) 2793 return r; 2794 2795 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2796 2797 adev->ddev->mode_config.async_page_flip = true; 2798 2799 adev->ddev->mode_config.max_width = 16384; 2800 adev->ddev->mode_config.max_height = 16384; 2801 2802 adev->ddev->mode_config.preferred_depth = 24; 2803 adev->ddev->mode_config.prefer_shadow = 1; 2804 2805 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2806 2807 r = amdgpu_display_modeset_create_props(adev); 2808 if (r) 2809 return r; 2810 2811 adev->ddev->mode_config.max_width = 16384; 2812 adev->ddev->mode_config.max_height = 16384; 2813 2814 /* allocate crtcs */ 2815 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2816 r = dce_v10_0_crtc_init(adev, i); 2817 if (r) 2818 return r; 2819 } 2820 2821 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2822 amdgpu_display_print_display_setup(adev->ddev); 2823 else 2824 return -EINVAL; 2825 2826 /* setup afmt */ 2827 r = dce_v10_0_afmt_init(adev); 2828 if (r) 2829 return r; 2830 2831 r = dce_v10_0_audio_init(adev); 2832 if (r) 2833 return r; 2834 2835 drm_kms_helper_poll_init(adev->ddev); 2836 2837 adev->mode_info.mode_config_initialized = true; 2838 return 0; 2839 } 2840 2841 static int dce_v10_0_sw_fini(void *handle) 2842 { 2843 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2844 2845 kfree(adev->mode_info.bios_hardcoded_edid); 2846 2847 drm_kms_helper_poll_fini(adev->ddev); 2848 2849 dce_v10_0_audio_fini(adev); 2850 2851 dce_v10_0_afmt_fini(adev); 2852 2853 drm_mode_config_cleanup(adev->ddev); 2854 adev->mode_info.mode_config_initialized = false; 2855 2856 return 0; 2857 } 2858 2859 static int dce_v10_0_hw_init(void *handle) 2860 { 2861 int i; 2862 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2863 2864 dce_v10_0_init_golden_registers(adev); 2865 2866 /* disable vga render */ 2867 dce_v10_0_set_vga_render_state(adev, false); 2868 /* init dig PHYs, disp eng pll */ 2869 amdgpu_atombios_encoder_init_dig(adev); 2870 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2871 2872 /* initialize hpd */ 2873 dce_v10_0_hpd_init(adev); 2874 2875 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2876 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2877 } 2878 2879 dce_v10_0_pageflip_interrupt_init(adev); 2880 2881 return 0; 2882 } 2883 2884 static int dce_v10_0_hw_fini(void *handle) 2885 { 2886 int i; 2887 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2888 2889 dce_v10_0_hpd_fini(adev); 2890 2891 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2892 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2893 } 2894 2895 dce_v10_0_pageflip_interrupt_fini(adev); 2896 2897 return 0; 2898 } 2899 2900 static int dce_v10_0_suspend(void *handle) 2901 { 2902 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2903 2904 adev->mode_info.bl_level = 2905 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2906 2907 return dce_v10_0_hw_fini(handle); 2908 } 2909 2910 static int dce_v10_0_resume(void *handle) 2911 { 2912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2913 int ret; 2914 2915 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2916 adev->mode_info.bl_level); 2917 2918 ret = dce_v10_0_hw_init(handle); 2919 2920 /* turn on the BL */ 2921 if (adev->mode_info.bl_encoder) { 2922 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2923 adev->mode_info.bl_encoder); 2924 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2925 bl_level); 2926 } 2927 2928 return ret; 2929 } 2930 2931 static bool dce_v10_0_is_idle(void *handle) 2932 { 2933 return true; 2934 } 2935 2936 static int dce_v10_0_wait_for_idle(void *handle) 2937 { 2938 return 0; 2939 } 2940 2941 static bool dce_v10_0_check_soft_reset(void *handle) 2942 { 2943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2944 2945 return dce_v10_0_is_display_hung(adev); 2946 } 2947 2948 static int dce_v10_0_soft_reset(void *handle) 2949 { 2950 u32 srbm_soft_reset = 0, tmp; 2951 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2952 2953 if (dce_v10_0_is_display_hung(adev)) 2954 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2955 2956 if (srbm_soft_reset) { 2957 tmp = RREG32(mmSRBM_SOFT_RESET); 2958 tmp |= srbm_soft_reset; 2959 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2960 WREG32(mmSRBM_SOFT_RESET, tmp); 2961 tmp = RREG32(mmSRBM_SOFT_RESET); 2962 2963 udelay(50); 2964 2965 tmp &= ~srbm_soft_reset; 2966 WREG32(mmSRBM_SOFT_RESET, tmp); 2967 tmp = RREG32(mmSRBM_SOFT_RESET); 2968 2969 /* Wait a little for things to settle down */ 2970 udelay(50); 2971 } 2972 return 0; 2973 } 2974 2975 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2976 int crtc, 2977 enum amdgpu_interrupt_state state) 2978 { 2979 u32 lb_interrupt_mask; 2980 2981 if (crtc >= adev->mode_info.num_crtc) { 2982 DRM_DEBUG("invalid crtc %d\n", crtc); 2983 return; 2984 } 2985 2986 switch (state) { 2987 case AMDGPU_IRQ_STATE_DISABLE: 2988 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2989 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2990 VBLANK_INTERRUPT_MASK, 0); 2991 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2992 break; 2993 case AMDGPU_IRQ_STATE_ENABLE: 2994 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2995 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2996 VBLANK_INTERRUPT_MASK, 1); 2997 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2998 break; 2999 default: 3000 break; 3001 } 3002 } 3003 3004 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3005 int crtc, 3006 enum amdgpu_interrupt_state state) 3007 { 3008 u32 lb_interrupt_mask; 3009 3010 if (crtc >= adev->mode_info.num_crtc) { 3011 DRM_DEBUG("invalid crtc %d\n", crtc); 3012 return; 3013 } 3014 3015 switch (state) { 3016 case AMDGPU_IRQ_STATE_DISABLE: 3017 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3018 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3019 VLINE_INTERRUPT_MASK, 0); 3020 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3021 break; 3022 case AMDGPU_IRQ_STATE_ENABLE: 3023 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3024 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3025 VLINE_INTERRUPT_MASK, 1); 3026 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3027 break; 3028 default: 3029 break; 3030 } 3031 } 3032 3033 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 3034 struct amdgpu_irq_src *source, 3035 unsigned hpd, 3036 enum amdgpu_interrupt_state state) 3037 { 3038 u32 tmp; 3039 3040 if (hpd >= adev->mode_info.num_hpd) { 3041 DRM_DEBUG("invalid hdp %d\n", hpd); 3042 return 0; 3043 } 3044 3045 switch (state) { 3046 case AMDGPU_IRQ_STATE_DISABLE: 3047 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3048 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3049 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3050 break; 3051 case AMDGPU_IRQ_STATE_ENABLE: 3052 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3053 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3054 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3055 break; 3056 default: 3057 break; 3058 } 3059 3060 return 0; 3061 } 3062 3063 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3064 struct amdgpu_irq_src *source, 3065 unsigned type, 3066 enum amdgpu_interrupt_state state) 3067 { 3068 switch (type) { 3069 case AMDGPU_CRTC_IRQ_VBLANK1: 3070 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3071 break; 3072 case AMDGPU_CRTC_IRQ_VBLANK2: 3073 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3074 break; 3075 case AMDGPU_CRTC_IRQ_VBLANK3: 3076 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3077 break; 3078 case AMDGPU_CRTC_IRQ_VBLANK4: 3079 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3080 break; 3081 case AMDGPU_CRTC_IRQ_VBLANK5: 3082 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3083 break; 3084 case AMDGPU_CRTC_IRQ_VBLANK6: 3085 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3086 break; 3087 case AMDGPU_CRTC_IRQ_VLINE1: 3088 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3089 break; 3090 case AMDGPU_CRTC_IRQ_VLINE2: 3091 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3092 break; 3093 case AMDGPU_CRTC_IRQ_VLINE3: 3094 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3095 break; 3096 case AMDGPU_CRTC_IRQ_VLINE4: 3097 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3098 break; 3099 case AMDGPU_CRTC_IRQ_VLINE5: 3100 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3101 break; 3102 case AMDGPU_CRTC_IRQ_VLINE6: 3103 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3104 break; 3105 default: 3106 break; 3107 } 3108 return 0; 3109 } 3110 3111 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3112 struct amdgpu_irq_src *src, 3113 unsigned type, 3114 enum amdgpu_interrupt_state state) 3115 { 3116 u32 reg; 3117 3118 if (type >= adev->mode_info.num_crtc) { 3119 DRM_ERROR("invalid pageflip crtc %d\n", type); 3120 return -EINVAL; 3121 } 3122 3123 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3124 if (state == AMDGPU_IRQ_STATE_DISABLE) 3125 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3126 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3127 else 3128 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3129 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3130 3131 return 0; 3132 } 3133 3134 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3135 struct amdgpu_irq_src *source, 3136 struct amdgpu_iv_entry *entry) 3137 { 3138 unsigned long flags; 3139 unsigned crtc_id; 3140 struct amdgpu_crtc *amdgpu_crtc; 3141 struct amdgpu_flip_work *works; 3142 3143 crtc_id = (entry->src_id - 8) >> 1; 3144 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3145 3146 if (crtc_id >= adev->mode_info.num_crtc) { 3147 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3148 return -EINVAL; 3149 } 3150 3151 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3152 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3153 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3154 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3155 3156 /* IRQ could occur when in initial stage */ 3157 if (amdgpu_crtc == NULL) 3158 return 0; 3159 3160 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3161 works = amdgpu_crtc->pflip_works; 3162 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3163 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3164 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3165 amdgpu_crtc->pflip_status, 3166 AMDGPU_FLIP_SUBMITTED); 3167 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3168 return 0; 3169 } 3170 3171 /* page flip completed. clean up */ 3172 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3173 amdgpu_crtc->pflip_works = NULL; 3174 3175 /* wakeup usersapce */ 3176 if (works->event) 3177 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3178 3179 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3180 3181 drm_crtc_vblank_put(&amdgpu_crtc->base); 3182 schedule_work(&works->unpin_work); 3183 3184 return 0; 3185 } 3186 3187 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3188 int hpd) 3189 { 3190 u32 tmp; 3191 3192 if (hpd >= adev->mode_info.num_hpd) { 3193 DRM_DEBUG("invalid hdp %d\n", hpd); 3194 return; 3195 } 3196 3197 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3198 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3199 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3200 } 3201 3202 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3203 int crtc) 3204 { 3205 u32 tmp; 3206 3207 if (crtc >= adev->mode_info.num_crtc) { 3208 DRM_DEBUG("invalid crtc %d\n", crtc); 3209 return; 3210 } 3211 3212 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3213 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3214 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3215 } 3216 3217 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3218 int crtc) 3219 { 3220 u32 tmp; 3221 3222 if (crtc >= adev->mode_info.num_crtc) { 3223 DRM_DEBUG("invalid crtc %d\n", crtc); 3224 return; 3225 } 3226 3227 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3228 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3229 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3230 } 3231 3232 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3233 struct amdgpu_irq_src *source, 3234 struct amdgpu_iv_entry *entry) 3235 { 3236 unsigned crtc = entry->src_id - 1; 3237 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3238 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc); 3239 3240 switch (entry->src_data[0]) { 3241 case 0: /* vblank */ 3242 if (disp_int & interrupt_status_offsets[crtc].vblank) 3243 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3244 else 3245 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3246 3247 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3248 drm_handle_vblank(adev->ddev, crtc); 3249 } 3250 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3251 3252 break; 3253 case 1: /* vline */ 3254 if (disp_int & interrupt_status_offsets[crtc].vline) 3255 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3256 else 3257 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3258 3259 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3260 3261 break; 3262 default: 3263 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3264 break; 3265 } 3266 3267 return 0; 3268 } 3269 3270 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3271 struct amdgpu_irq_src *source, 3272 struct amdgpu_iv_entry *entry) 3273 { 3274 uint32_t disp_int, mask; 3275 unsigned hpd; 3276 3277 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3278 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3279 return 0; 3280 } 3281 3282 hpd = entry->src_data[0]; 3283 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3284 mask = interrupt_status_offsets[hpd].hpd; 3285 3286 if (disp_int & mask) { 3287 dce_v10_0_hpd_int_ack(adev, hpd); 3288 schedule_work(&adev->hotplug_work); 3289 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3290 } 3291 3292 return 0; 3293 } 3294 3295 static int dce_v10_0_set_clockgating_state(void *handle, 3296 enum amd_clockgating_state state) 3297 { 3298 return 0; 3299 } 3300 3301 static int dce_v10_0_set_powergating_state(void *handle, 3302 enum amd_powergating_state state) 3303 { 3304 return 0; 3305 } 3306 3307 static const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3308 .name = "dce_v10_0", 3309 .early_init = dce_v10_0_early_init, 3310 .late_init = NULL, 3311 .sw_init = dce_v10_0_sw_init, 3312 .sw_fini = dce_v10_0_sw_fini, 3313 .hw_init = dce_v10_0_hw_init, 3314 .hw_fini = dce_v10_0_hw_fini, 3315 .suspend = dce_v10_0_suspend, 3316 .resume = dce_v10_0_resume, 3317 .is_idle = dce_v10_0_is_idle, 3318 .wait_for_idle = dce_v10_0_wait_for_idle, 3319 .check_soft_reset = dce_v10_0_check_soft_reset, 3320 .soft_reset = dce_v10_0_soft_reset, 3321 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3322 .set_powergating_state = dce_v10_0_set_powergating_state, 3323 }; 3324 3325 static void 3326 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3327 struct drm_display_mode *mode, 3328 struct drm_display_mode *adjusted_mode) 3329 { 3330 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3331 3332 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3333 3334 /* need to call this here rather than in prepare() since we need some crtc info */ 3335 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3336 3337 /* set scaler clears this on some chips */ 3338 dce_v10_0_set_interleave(encoder->crtc, mode); 3339 3340 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3341 dce_v10_0_afmt_enable(encoder, true); 3342 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3343 } 3344 } 3345 3346 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3347 { 3348 struct amdgpu_device *adev = encoder->dev->dev_private; 3349 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3350 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3351 3352 if ((amdgpu_encoder->active_device & 3353 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3354 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3355 ENCODER_OBJECT_ID_NONE)) { 3356 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3357 if (dig) { 3358 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3359 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3360 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3361 } 3362 } 3363 3364 amdgpu_atombios_scratch_regs_lock(adev, true); 3365 3366 if (connector) { 3367 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3368 3369 /* select the clock/data port if it uses a router */ 3370 if (amdgpu_connector->router.cd_valid) 3371 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3372 3373 /* turn eDP panel on for mode set */ 3374 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3375 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3376 ATOM_TRANSMITTER_ACTION_POWER_ON); 3377 } 3378 3379 /* this is needed for the pll/ss setup to work correctly in some cases */ 3380 amdgpu_atombios_encoder_set_crtc_source(encoder); 3381 /* set up the FMT blocks */ 3382 dce_v10_0_program_fmt(encoder); 3383 } 3384 3385 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3386 { 3387 struct drm_device *dev = encoder->dev; 3388 struct amdgpu_device *adev = dev->dev_private; 3389 3390 /* need to call this here as we need the crtc set up */ 3391 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3392 amdgpu_atombios_scratch_regs_lock(adev, false); 3393 } 3394 3395 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3396 { 3397 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3398 struct amdgpu_encoder_atom_dig *dig; 3399 3400 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3401 3402 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3403 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3404 dce_v10_0_afmt_enable(encoder, false); 3405 dig = amdgpu_encoder->enc_priv; 3406 dig->dig_encoder = -1; 3407 } 3408 amdgpu_encoder->active_device = 0; 3409 } 3410 3411 /* these are handled by the primary encoders */ 3412 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3413 { 3414 3415 } 3416 3417 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3418 { 3419 3420 } 3421 3422 static void 3423 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3424 struct drm_display_mode *mode, 3425 struct drm_display_mode *adjusted_mode) 3426 { 3427 3428 } 3429 3430 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3431 { 3432 3433 } 3434 3435 static void 3436 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3437 { 3438 3439 } 3440 3441 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3442 .dpms = dce_v10_0_ext_dpms, 3443 .prepare = dce_v10_0_ext_prepare, 3444 .mode_set = dce_v10_0_ext_mode_set, 3445 .commit = dce_v10_0_ext_commit, 3446 .disable = dce_v10_0_ext_disable, 3447 /* no detect for TMDS/LVDS yet */ 3448 }; 3449 3450 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3451 .dpms = amdgpu_atombios_encoder_dpms, 3452 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3453 .prepare = dce_v10_0_encoder_prepare, 3454 .mode_set = dce_v10_0_encoder_mode_set, 3455 .commit = dce_v10_0_encoder_commit, 3456 .disable = dce_v10_0_encoder_disable, 3457 .detect = amdgpu_atombios_encoder_dig_detect, 3458 }; 3459 3460 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3461 .dpms = amdgpu_atombios_encoder_dpms, 3462 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3463 .prepare = dce_v10_0_encoder_prepare, 3464 .mode_set = dce_v10_0_encoder_mode_set, 3465 .commit = dce_v10_0_encoder_commit, 3466 .detect = amdgpu_atombios_encoder_dac_detect, 3467 }; 3468 3469 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3470 { 3471 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3472 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3473 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3474 kfree(amdgpu_encoder->enc_priv); 3475 drm_encoder_cleanup(encoder); 3476 kfree(amdgpu_encoder); 3477 } 3478 3479 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3480 .destroy = dce_v10_0_encoder_destroy, 3481 }; 3482 3483 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3484 uint32_t encoder_enum, 3485 uint32_t supported_device, 3486 u16 caps) 3487 { 3488 struct drm_device *dev = adev->ddev; 3489 struct drm_encoder *encoder; 3490 struct amdgpu_encoder *amdgpu_encoder; 3491 3492 /* see if we already added it */ 3493 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3494 amdgpu_encoder = to_amdgpu_encoder(encoder); 3495 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3496 amdgpu_encoder->devices |= supported_device; 3497 return; 3498 } 3499 3500 } 3501 3502 /* add a new one */ 3503 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3504 if (!amdgpu_encoder) 3505 return; 3506 3507 encoder = &amdgpu_encoder->base; 3508 switch (adev->mode_info.num_crtc) { 3509 case 1: 3510 encoder->possible_crtcs = 0x1; 3511 break; 3512 case 2: 3513 default: 3514 encoder->possible_crtcs = 0x3; 3515 break; 3516 case 4: 3517 encoder->possible_crtcs = 0xf; 3518 break; 3519 case 6: 3520 encoder->possible_crtcs = 0x3f; 3521 break; 3522 } 3523 3524 amdgpu_encoder->enc_priv = NULL; 3525 3526 amdgpu_encoder->encoder_enum = encoder_enum; 3527 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3528 amdgpu_encoder->devices = supported_device; 3529 amdgpu_encoder->rmx_type = RMX_OFF; 3530 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3531 amdgpu_encoder->is_ext_encoder = false; 3532 amdgpu_encoder->caps = caps; 3533 3534 switch (amdgpu_encoder->encoder_id) { 3535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3536 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3537 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3538 DRM_MODE_ENCODER_DAC, NULL); 3539 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3540 break; 3541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3542 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3543 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3544 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3545 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3546 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3547 amdgpu_encoder->rmx_type = RMX_FULL; 3548 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3549 DRM_MODE_ENCODER_LVDS, NULL); 3550 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3551 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3552 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3553 DRM_MODE_ENCODER_DAC, NULL); 3554 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3555 } else { 3556 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3557 DRM_MODE_ENCODER_TMDS, NULL); 3558 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3559 } 3560 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3561 break; 3562 case ENCODER_OBJECT_ID_SI170B: 3563 case ENCODER_OBJECT_ID_CH7303: 3564 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3565 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3566 case ENCODER_OBJECT_ID_TITFP513: 3567 case ENCODER_OBJECT_ID_VT1623: 3568 case ENCODER_OBJECT_ID_HDMI_SI1930: 3569 case ENCODER_OBJECT_ID_TRAVIS: 3570 case ENCODER_OBJECT_ID_NUTMEG: 3571 /* these are handled by the primary encoders */ 3572 amdgpu_encoder->is_ext_encoder = true; 3573 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3574 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3575 DRM_MODE_ENCODER_LVDS, NULL); 3576 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3577 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3578 DRM_MODE_ENCODER_DAC, NULL); 3579 else 3580 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3581 DRM_MODE_ENCODER_TMDS, NULL); 3582 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3583 break; 3584 } 3585 } 3586 3587 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3588 .bandwidth_update = &dce_v10_0_bandwidth_update, 3589 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3590 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3591 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3592 .hpd_sense = &dce_v10_0_hpd_sense, 3593 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3594 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3595 .page_flip = &dce_v10_0_page_flip, 3596 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3597 .add_encoder = &dce_v10_0_encoder_add, 3598 .add_connector = &amdgpu_connector_add, 3599 }; 3600 3601 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3602 { 3603 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3604 } 3605 3606 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3607 .set = dce_v10_0_set_crtc_irq_state, 3608 .process = dce_v10_0_crtc_irq, 3609 }; 3610 3611 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3612 .set = dce_v10_0_set_pageflip_irq_state, 3613 .process = dce_v10_0_pageflip_irq, 3614 }; 3615 3616 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3617 .set = dce_v10_0_set_hpd_irq_state, 3618 .process = dce_v10_0_hpd_irq, 3619 }; 3620 3621 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3622 { 3623 if (adev->mode_info.num_crtc > 0) 3624 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3625 else 3626 adev->crtc_irq.num_types = 0; 3627 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3628 3629 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3630 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3631 3632 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3633 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3634 } 3635 3636 const struct amdgpu_ip_block_version dce_v10_0_ip_block = 3637 { 3638 .type = AMD_IP_BLOCK_TYPE_DCE, 3639 .major = 10, 3640 .minor = 0, 3641 .rev = 0, 3642 .funcs = &dce_v10_0_ip_funcs, 3643 }; 3644 3645 const struct amdgpu_ip_block_version dce_v10_1_ip_block = 3646 { 3647 .type = AMD_IP_BLOCK_TYPE_DCE, 3648 .major = 10, 3649 .minor = 1, 3650 .rev = 0, 3651 .funcs = &dce_v10_0_ip_funcs, 3652 }; 3653
Indexes created Sat Sep 20 22:09:52 GMT 2025