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  /src/share/man/man9/
paravirt_membar_sync.9 1.1.6.2 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.1.4.2 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.1.2.2 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

Makefile 1.436 Sat Apr 06 03:06:24 UTC 2019 thorpej Overhaul the API used to fetch and store individual memory cells in
userspace. The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms. The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.
1.437.2.5 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.465.2.6 Sun Oct 19 10:34:40 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.474.2.1 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/sys/
paravirt_membar.h 1.1.6.2 Sun Oct 19 10:44:33 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.1.4.2 Sun Oct 19 10:34:43 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.1.2.2 Sun Oct 19 10:29:21 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/sys/arch/hppa/hppa/
support.S 1.7.30.2 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.7.4.1 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.8.2.1 Sun Oct 19 10:29:20 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/arch/riscv/riscv/
cpu_subr.c 1.5.4.1 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/sys/arch/arm/arm/
cpu_subr.c 1.5.12.1 Sun Oct 19 10:29:21 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.5.4.1 Sun Oct 19 10:34:43 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/common/lib/libc/arch/sparc/atomic/
membar_ops.S 1.8.10.1 Sun Oct 19 10:29:20 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.8.2.1 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/common/lib/libc/arch/sparc64/atomic/
membar_ops.S 1.9.10.1 Sun Oct 19 10:29:21 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.9.2.1 Sun Oct 19 10:34:43 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/common/lib/libc/arch/x86_64/atomic/
atomic.S 1.29.2.2 Sun Oct 19 10:34:43 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.31.2.1 Sun Oct 19 10:29:22 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/share/man/man4/
ixg.4 1.10.4.2 Thu Mar 11 16:04:25 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

1.12.4.1 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

ixv.4 1.3.2.4 Thu Mar 11 16:04:25 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

1.4.2.2 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

  /src/sys/arch/i386/i386/
cpufunc.S 1.34.2.1 Sun Oct 19 10:44:33 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.49.20.2 Sun Oct 19 10:34:43 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.53.2.1 Sun Oct 19 10:29:21 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/sys/arch/mips/mips/
cpu_subr.c 1.34.4.1 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.62.4.1 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

1.64.8.1 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/common/lib/libc/arch/i386/atomic/
atomic.S 1.36.2.2 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.37.2.1 Sun Oct 19 10:29:20 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/arch/amd64/amd64/
cpufunc.S 1.43.2.1 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.65.18.2 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.69.2.1 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/arch/virt68k/virt68k/
locore.s 1.16.2.1 Sun Oct 19 10:29:21 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/sys/dev/pci/ixgbe/
ixgbe_netbsd.h 1.7.6.3 Thu Mar 11 16:04:25 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

1.11.4.1 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.

ixgbe_vf.c 1.12.8.6 Thu Mar 11 16:04:25 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
1.18.2.3 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
ixgbe_x540.c 1.9.6.5 Thu Mar 11 16:04:25 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
1.16.8.1 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
  /src/sys/arch/alpha/alpha/
locore.s 1.123.4.2 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.143.4.1 Sun Oct 19 10:34:41 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.144.2.1 Sun Oct 19 10:29:20 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/arch/aarch64/aarch64/
aarch64_machdep.c 1.28.4.5 Sun Oct 19 10:44:33 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

  /src/sys/arch/sparc/sparc/
locore.s 1.274.2.2 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.283.4.2 Sun Oct 19 10:34:40 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.286.2.1 Sun Oct 19 10:29:19 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
  /src/sys/dev/pci/
files.pci 1.436 Tue Mar 09 10:03:18 UTC 2021 msaitoh branches: 1.436.4;
Modify some parameters to reduce packet dropping.

- Background: ixgbe doesn't use common MCLGET() interface and use the
driver specific cluster allocation mechanism (jcl). The cluster is
pre-allocated with a fixed number and the current number per queue
is num_rx_desc * 2 (2048*2=4096). It's too small. It also has a problem
that the max length of the pcq which is used in the TX path is big
(4096). Example:

100M <----- [ixg0 ixg1] <----- 1G
2048 TX descs <--- 4096 pcqs <---- 2048 RX descs

If a machine forwards a traffic from 1G interface to 100M interface,
It would require 2048+4096+2048=8192 descriptors, but the current number
is 2048*2=4096. It's too small. Even if the both interface's link speed
is the same and only small number of packet is queued in the pcq, 4096
jcl is small because 2048(RX)+TX(2048)=4096. If jcl is exhausted, not only
forwarding from ixg1 to ixg0 is dropped, but also another forwarding path
from ixg1 to another interface(e.g. wm0) is also dropped. Sockets also
queue packets, so if a lot of sockets are used and/or a socket buffer
size is changed to bigger one, it'll also become a problem. If the jcl
is exhausted, evcnt(9) counter "ixgX qY Rx no jumbo mbuf" is incremented.
Example:
vmstat -ev | grep ixg1 | grep "no jumbo"
ixg1 q0 Rx no jumbo mbuf 0 0 misc
ixg1 q1 Rx no jumbo mbuf 0 0 misc
ixg1 q2 Rx no jumbo mbuf 141326 0 misc
ixg1 q3 Rx no jumbo mbuf 0 0 misc


- To solve this problem:
- Add new config parameter IXGBE_JCLNUM_MULTI and set the default to 3
(2048 * 3). The minimum number is 2. The total number of jcl per queue
is available with hw.ixgN.num_jcl_per_queue sysctl.
- Reduce the max length of the pcq() which is used in the TX path from
4096 to 2048.

- Reviewed by knakahara@ and ozaki-r@.

- TODO: Use MCLGET().
Tue Mar 09 10:03:18 UTC 2021 msaitoh branches: 1.436.4;
Modify some parameters to reduce packet dropping.

- Background: ixgbe doesn't use common MCLGET() interface and use the
driver specific cluster allocation mechanism (jcl). The cluster is
pre-allocated with a fixed number and the current number per queue
is num_rx_desc * 2 (2048*2=4096). It's too small. It also has a problem
that the max length of the pcq which is used in the TX path is big
(4096). Example:

100M <----- [ixg0 ixg1] <----- 1G
2048 TX descs <--- 4096 pcqs <---- 2048 RX descs

If a machine forwards a traffic from 1G interface to 100M interface,
It would require 2048+4096+2048=8192 descriptors, but the current number
is 2048*2=4096. It's too small. Even if the both interface's link speed
is the same and only small number of packet is queued in the pcq, 4096
jcl is small because 2048(RX)+TX(2048)=4096. If jcl is exhausted, not only
forwarding from ixg1 to ixg0 is dropped, but also another forwarding path
from ixg1 to another interface(e.g. wm0) is also dropped. Sockets also
queue packets, so if a lot of sockets are used and/or a socket buffer
size is changed to bigger one, it'll also become a problem. If the jcl
is exhausted, evcnt(9) counter "ixgX qY Rx no jumbo mbuf" is incremented.
Example:
vmstat -ev | grep ixg1 | grep "no jumbo"
ixg1 q0 Rx no jumbo mbuf 0 0 misc
ixg1 q1 Rx no jumbo mbuf 0 0 misc
ixg1 q2 Rx no jumbo mbuf 141326 0 misc
ixg1 q3 Rx no jumbo mbuf 0 0 misc


- To solve this problem:
- Add new config parameter IXGBE_JCLNUM_MULTI and set the default to 3
(2048 * 3). The minimum number is 2. The total number of jcl per queue
is available with hw.ixgN.num_jcl_per_queue sysctl.
- Reduce the max length of the pcq() which is used in the TX path from
4096 to 2048.

- Reviewed by knakahara@ and ozaki-r@.

- TODO: Use MCLGET().
1.388.4.5 Thu Mar 11 16:04:24 UTC 2021 martin Pull up the following (all via patch), requested by msaitoh in ticket #1663:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.3, 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
1.413.2.3 Thu Mar 11 16:00:24 UTC 2021 martin Pull up the following (all via patch) requested by msaitoh in ticket #1231:

sys/dev/pci/ixgbe/ixgbe.c 1.259, 1.278-1.279
sys/dev/pci/ixgbe/ixgbe.h 1.75
sys/dev/pci/ixgbe/ixgbe_netbsd.h 1.12
sys/dev/pci/ixgbe/ixgbe_vf.c 1.24-1.26
sys/dev/pci/ixgbe/ixgbe_x550.c 1.17
sys/dev/pci/ixgbe/ixv.c 1.155-1.156
sys/dev/pci/ixgbe/ix_txrx.c 1.64-67
sys/dev/pci/files.pci 1.436
share/man/man4/ixg.4 1.13-1.14
share/man/man4/ixv.4 1.6-1.7

- Fix a problem that the RX path stalled when the mbuf cluster is
exhausted.
- Modify some parameters to reduce packet dropping. See also the
manual's OPTIONS section for the detail.
- ixv(4): The max number of queue(pair) is not 7 but 8. Correctly
reset the hardware.
- Add "TX " to "Queue No Descriptor Available" evcnt(9) name to make
it more understandable.
- Fix a bug that some advertise speeds can't be set with
hw.ixgN.advertise_speed if both 2.5G and 5G are set. Fix the error
message, too.
- Fix typo in comment or debug message.
1.436.4.1 Thu May 13 00:47:31 UTC 2021 thorpej Sync with HEAD.
  /src/sys/kern/
init_main.c 1.436 Wed Sep 28 15:52:47 UTC 2011 jruoho branches: 1.436.2;
Initialize cpufreq(9) normally from main().
Wed Sep 28 15:52:47 UTC 2011 jruoho branches: 1.436.2;
Initialize cpufreq(9) normally from main().
1.436.2.5 Thu May 22 11:41:03 UTC 2014 yamt sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
1.436.2.4 Tue Oct 30 17:22:26 UTC 2012 yamt sync with head
1.436.2.3 Tue Apr 17 00:08:22 UTC 2012 yamt sync with head
1.436.2.2 Sun Nov 20 10:52:33 UTC 2011 yamt - fix page loaning XXX make O->A loaning further
- add some statistics
1.436.2.1 Wed Nov 02 21:53:59 UTC 2011 yamt page cache related changes

- maintain object pages in radix tree rather than rb tree.
- reduce unnecessary page scan in putpages. esp. when an object has a ton of
pages cached but only a few of them are dirty.
- reduce the number of pmap operations by tracking page dirtiness more
precisely in uvm layer.
- fix nfs commit range tracking.
- fix nfs write clustering. XXX hack
  /src/sys/arch/sparc64/sparc64/
locore.s 1.436 Sat Sep 06 02:53:23 UTC 2025 riastradh paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs
1.421.2.2 Sun Oct 19 10:44:31 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.431.4.2 Sun Oct 19 10:34:42 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32
(all via patch)

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs
1.435.2.1 Sun Oct 19 10:29:20 UTC 2025 martin Pull up following revision(s) (requested by riastradh in ticket #60):

sys/arch/sparc/sparc/locore.s: revision 1.287
share/man/man9/Makefile: revision 1.475
sys/arch/mips/mips/cpu_subr.c: revision 1.65
sys/arch/riscv/riscv/cpu_subr.c: revision 1.6
sys/arch/mips/mips/cpu_subr.c: revision 1.66
sys/arch/amd64/amd64/cpufunc.S: revision 1.70
common/lib/libc/arch/i386/atomic/atomic.S: revision 1.38
common/lib/libc/arch/sparc/atomic/membar_ops.S: revision 1.9
sys/arch/hppa/hppa/support.S: revision 1.9
sys/arch/alpha/alpha/locore.s: revision 1.145
share/man/man9/paravirt_membar_sync.9: revision 1.1
sys/arch/sparc64/sparc64/locore.s: revision 1.436
distrib/sets/lists/comp/mi: revision 1.2499
sys/arch/i386/i386/cpufunc.S: revision 1.54
common/lib/libc/arch/sparc64/atomic/membar_ops.S: revision 1.10
sys/sys/paravirt_membar.h: revision 1.1
sys/arch/arm/arm/cpu_subr.c: revision 1.6
sys/arch/virt68k/virt68k/locore.s: revision 1.17
common/lib/libc/arch/x86_64/atomic/atomic.S: revision 1.32

paravirt_membar_sync(9): New memory barrier.

For use in paravirtualized drivers which require store-before-load
ordering -- irrespective of whether the kernel is built for a single
processor, or whether the (virtual) machine is booted with a single
processor.

This is even required on architectures that don't even have a
store-before-load ordering barrier, like m68k; adding, e.g., a virtio
bus is _as if_ the architecture has been extended with relaxed memory
ordering when talking with that new bus. Such architectures need
some way to request the hypervisor enforce that ordering -- on m68k,
that's done by issuing a CASL instruction, which qemu maps to an
atomic r/m/w with sequential consistency ordering in the host.

PR kern/59618: occasional virtio block device lock ups/hangs

mips: Fix asm arch options in new paravirt_membar_sync.
Need to explicitly enable mips2 (MIPS-II) instructions in order to
use sync. Fixes:
/tmp/ccxgOmXc.s: Assembler messages:
/tmp/ccxgOmXc.s:3576: Error: opcode not supported on this processor: mips1 (mips1) `sync'
--- cpu_subr.o ---
*** Failed target: cpu_subr.o

PR kern/59618: occasional virtio block device lock ups/hangs

Completed in 323 milliseconds

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