1 /* $NetBSD: zs.c,v 1.86 2026/11/11 03:05:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Zilog Z8530 Dual UART driver (machine-dependent part) 34 * 35 * Runs two serial lines per chip using slave drivers. 36 * Plain tty/async lines use the zs_async slave. 37 * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.86 2026/11/11 03:05:12 thorpej Exp $"); 42 43 #include "opt_ddb.h" 44 #include "opt_kgdb.h" 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/file.h> 51 #include <sys/ioctl.h> 52 #include <sys/kernel.h> 53 #include <sys/proc.h> 54 #include <sys/tty.h> 55 #include <sys/time.h> 56 #include <sys/syslog.h> 57 #include <sys/intr.h> 58 59 #include <ddb/db_active.h> 60 61 #include <machine/autoconf.h> 62 #include <machine/openfirm.h> 63 #include <machine/cpu.h> 64 #include <machine/eeprom.h> 65 #include <machine/psl.h> 66 #include <machine/z8530var.h> 67 68 #include <dev/cons.h> 69 #include <dev/ic/z8530reg.h> 70 #include <dev/sun/kbd_ms_ttyvar.h> 71 72 #include <dev/sbus/sbusvar.h> 73 #include <sparc64/dev/fhcvar.h> 74 #include <sparc64/dev/cons.h> 75 76 #include "ioconf.h" 77 #include "kbd.h" /* NKBD */ 78 #include "ms.h" /* NMS */ 79 #include "zs.h" /* NZS */ 80 81 /* Make life easier for the initialized arrays here. */ 82 #if NZS < 3 83 #undef NZS 84 #define NZS 3 85 #endif 86 87 /* 88 * Some warts needed by z8530tty.c - 89 * The default parity REALLY needs to be the same as the PROM uses, 90 * or you can not see messages done with printf during boot-up... 91 */ 92 int zs_def_cflag = (CREAD | CS8 | HUPCL); 93 94 /* 95 * The Sun provides a 4.9152 MHz clock to the ZS chips. 96 */ 97 #define PCLK (9600 * 512) /* PCLK pin input clock rate */ 98 99 #define ZS_DELAY() 100 101 /* The layout of this is hardware-dependent (padding, order). */ 102 struct zschan { 103 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 104 uint8_t zc_xxx0; 105 volatile uint8_t zc_data; /* data */ 106 uint8_t zc_xxx1; 107 }; 108 struct zsdevice { 109 /* Yes, they are backwards. */ 110 struct zschan zs_chan_b; 111 struct zschan zs_chan_a; 112 }; 113 114 /* ZS channel used as the console device (if any) */ 115 void *zs_conschan_get, *zs_conschan_put; 116 117 /* Saved PROM mappings */ 118 static struct zsdevice *zsaddr[NZS]; 119 120 static uint8_t zs_init_reg[16] = { 121 0, /* 0: CMD (reset, etc.) */ 122 0, /* 1: No interrupts yet. */ 123 0, /* 2: IVECT */ 124 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 125 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 126 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 127 0, /* 6: TXSYNC/SYNCLO */ 128 0, /* 7: RXSYNC/SYNCHI */ 129 0, /* 8: alias for data port */ 130 ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR, 131 0, /*10: Misc. TX/RX control bits */ 132 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 133 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 134 0, /*13: BAUDHI (default=9600) */ 135 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 136 ZSWR15_BREAK_IE, 137 }; 138 139 /* Console ops */ 140 static int zscngetc(dev_t); 141 static void zscnputc(dev_t, int); 142 static void zscnpollc(dev_t, int); 143 144 struct consdev zs_consdev = { 145 .cn_getc = zscngetc, 146 .cn_putc = zscnputc, 147 .cn_pollc = zscnpollc, 148 }; 149 150 151 /**************************************************************** 152 * Autoconfig 153 ****************************************************************/ 154 155 /* Definition of the driver for autoconfig. */ 156 static int zs_match_sbus(device_t, cfdata_t, void *); 157 static void zs_attach_sbus(device_t, device_t, void *); 158 159 static int zs_match_fhc(device_t, cfdata_t, void *); 160 static void zs_attach_fhc(device_t, device_t, void *); 161 162 static void zs_attach(struct zsc_softc *, struct zsdevice *, int); 163 static int zs_print(void *, const char *); 164 165 CFATTACH_DECL_NEW(zs, sizeof(struct zsc_softc), 166 zs_match_sbus, zs_attach_sbus, NULL, NULL); 167 168 CFATTACH_DECL_NEW(zs_fhc, sizeof(struct zsc_softc), 169 zs_match_fhc, zs_attach_fhc, NULL, NULL); 170 171 /* Interrupt handlers. */ 172 int zscheckintr(void *); 173 static int zshard(void *); 174 static void zssoft(void *); 175 176 static int zs_get_speed(struct zs_chanstate *); 177 178 /* Console device support */ 179 static int zs_console_flags(int, int, int); 180 181 /* Power management hooks */ 182 int zs_enable(struct zs_chanstate *); 183 void zs_disable(struct zs_chanstate *); 184 185 /* from dev/ic/z8530tty.c */ 186 struct tty *zstty_get_tty_from_dev(device_t); 187 188 /* 189 * Is the zs chip present? 190 */ 191 static int 192 zs_match_sbus(device_t parent, cfdata_t cf, void *aux) 193 { 194 struct sbus_attach_args *sa = aux; 195 196 if (strcmp(cf->cf_name, sa->sa_name) != 0) 197 return (0); 198 199 return (1); 200 } 201 202 static int 203 zs_match_fhc(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct fhc_attach_args *fa = aux; 206 207 if (strcmp(cf->cf_name, fa->fa_name) != 0) 208 return (0); 209 210 return (1); 211 } 212 213 static void 214 zs_attach_sbus(device_t parent, device_t self, void *aux) 215 { 216 struct zsc_softc *zsc = device_private(self); 217 struct sbus_attach_args *sa = aux; 218 bus_space_handle_t bh; 219 int zs_unit; 220 221 zsc->zsc_dev = self; 222 zs_unit = device_unit(self); 223 224 if (sa->sa_nintr == 0) { 225 aprint_error(": no interrupt lines\n"); 226 return; 227 } 228 229 /* Use the mapping setup by the Sun PROM if possible. */ 230 if (zsaddr[zs_unit] == NULL) { 231 /* Only map registers once. */ 232 if (sa->sa_npromvaddrs) { 233 /* 234 * We're converting from a 32-bit pointer to a 64-bit 235 * pointer. Since the 32-bit entity is negative, but 236 * the kernel is still mapped into the lower 4GB 237 * range, this needs to be zero-extended. 238 * 239 * XXXXX If we map the kernel and devices into the 240 * high 4GB range, this needs to be changed to 241 * sign-extend the address. 242 */ 243 sparc_promaddr_to_handle(sa->sa_bustag, 244 sa->sa_promvaddrs[0], &bh); 245 246 } else { 247 248 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 249 sa->sa_offset, 250 sa->sa_size, 251 BUS_SPACE_MAP_LINEAR, 252 &bh) != 0) { 253 aprint_error(": cannot map registers\n"); 254 return; 255 } 256 } 257 zsaddr[zs_unit] = bus_space_vaddr(sa->sa_bustag, bh); 258 } 259 zsc->zsc_bustag = sa->sa_bustag; 260 zsc->zsc_dmatag = sa->sa_dmatag; 261 zsc->zsc_promunit = prom_getpropint(sa->sa_node, "slave", -2); 262 zsc->zsc_node = sa->sa_node; 263 aprint_normal("\n"); 264 zs_attach(zsc, zsaddr[zs_unit], sa->sa_pri); 265 } 266 267 static void 268 zs_attach_fhc(device_t parent, device_t self, void *aux) 269 { 270 struct zsc_softc *zsc = device_private(self); 271 struct fhc_attach_args *fa = aux; 272 bus_space_handle_t bh; 273 int zs_unit; 274 275 zsc->zsc_dev = self; 276 zs_unit = device_unit(self); 277 278 if (fa->fa_nreg < 1 && fa->fa_npromvaddrs < 1) { 279 printf(": no registers\n"); 280 return; 281 } 282 283 if (fa->fa_nintr == 0) { 284 aprint_error(": no interrupt lines\n"); 285 return; 286 } 287 288 /* Use the mapping setup by the Sun PROM if possible. */ 289 if (zsaddr[zs_unit] == NULL) { 290 /* Only map registers once. */ 291 if (fa->fa_npromvaddrs) { 292 /* 293 * We're converting from a 32-bit pointer to a 64-bit 294 * pointer. Since the 32-bit entity is negative, but 295 * the kernel is still mapped into the lower 4GB 296 * range, this needs to be zero-extended. 297 * 298 * XXXXX If we map the kernel and devices into the 299 * high 4GB range, this needs to be changed to 300 * sign-extend the address. 301 */ 302 sparc_promaddr_to_handle(fa->fa_bustag, 303 fa->fa_promvaddrs[0], &bh); 304 305 } else { 306 307 if (fhc_bus_map(fa->fa_bustag, 308 fa->fa_reg[0].fbr_slot, 309 fa->fa_reg[0].fbr_offset, 310 fa->fa_reg[0].fbr_size, 311 BUS_SPACE_MAP_LINEAR, 312 &bh) != 0) { 313 aprint_error(": cannot map registers\n"); 314 return; 315 } 316 } 317 zsaddr[zs_unit] = bus_space_vaddr(fa->fa_bustag, bh); 318 } 319 zsc->zsc_bustag = fa->fa_bustag; 320 zsc->zsc_dmatag = NULL; 321 zsc->zsc_promunit = prom_getpropint(fa->fa_node, "slave", -2); 322 zsc->zsc_node = fa->fa_node; 323 aprint_normal("\n"); 324 zs_attach(zsc, zsaddr[zs_unit], fa->fa_intr[0]); 325 } 326 327 /* 328 * Attach a found zs. 329 * 330 * USE ROM PROPERTIES port-a-ignore-cd AND port-b-ignore-cd FOR 331 * SOFT CARRIER, AND keyboard PROPERTY FOR KEYBOARD/MOUSE? 332 */ 333 static void 334 zs_attach(struct zsc_softc *zsc, struct zsdevice *zsd, int pri) 335 { 336 struct zsc_attach_args zsc_args; 337 struct zs_chanstate *cs; 338 int channel; 339 340 if (zsd == NULL) { 341 aprint_error(": configuration incomplete\n"); 342 return; 343 } 344 345 /* 346 * Initialize software state for each channel. 347 */ 348 for (channel = 0; channel < 2; channel++) { 349 struct zschan *zc; 350 device_t child; 351 352 zsc_args.channel = channel; 353 cs = &zsc->zsc_cs_store[channel]; 354 zsc->zsc_cs[channel] = cs; 355 356 zs_lock_init(cs); 357 cs->cs_channel = channel; 358 cs->cs_private = NULL; 359 cs->cs_ops = &zsops_null; 360 cs->cs_brg_clk = PCLK / 16; 361 362 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 363 364 zsc_args.consdev = NULL; 365 zsc_args.hwflags = zs_console_flags(zsc->zsc_promunit, 366 zsc->zsc_node, 367 channel); 368 369 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) { 370 zsc_args.hwflags |= ZS_HWFLAG_USE_CONSDEV; 371 zsc_args.consdev = &zs_consdev; 372 } 373 374 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_INPUT) != 0) { 375 zs_conschan_get = zc; 376 } 377 if ((zsc_args.hwflags & ZS_HWFLAG_CONSOLE_OUTPUT) != 0) { 378 zs_conschan_put = zc; 379 } 380 381 /* Children need to set cn_dev, etc */ 382 cs->cs_reg_csr = &zc->zc_csr; 383 cs->cs_reg_data = &zc->zc_data; 384 385 memcpy(cs->cs_creg, zs_init_reg, 16); 386 memcpy(cs->cs_preg, zs_init_reg, 16); 387 388 /* XXX: Consult PROM properties for this?! */ 389 cs->cs_defspeed = zs_get_speed(cs); 390 cs->cs_defcflag = zs_def_cflag; 391 392 /* Make these correspond to cs_defcflag (-crtscts) */ 393 cs->cs_rr0_dcd = ZSRR0_DCD; 394 cs->cs_rr0_cts = 0; 395 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 396 cs->cs_wr5_rts = 0; 397 398 /* 399 * Clear the master interrupt enable. 400 * The INTENA is common to both channels, 401 * so just do it on the A channel. 402 */ 403 if (channel == 0) { 404 zs_write_reg(cs, 9, 0); 405 } 406 407 /* 408 * Look for a child driver for this channel. 409 * The child attach will setup the hardware. 410 */ 411 child = config_found(zsc->zsc_dev, (void *)&zsc_args, 412 zs_print, CFARGS_NONE); 413 if (child == NULL) { 414 /* No sub-driver. Just reset it. */ 415 uint8_t reset = (channel == 0) ? 416 ZSWR9_A_RESET : ZSWR9_B_RESET; 417 zs_lock_chan(cs); 418 zs_write_reg(cs, 9, reset); 419 zs_unlock_chan(cs); 420 } 421 #if (NKBD > 0) || (NMS > 0) 422 /* 423 * If this was a zstty it has a keyboard 424 * property on it we need to attach the 425 * sunkbd and sunms line disciplines. 426 */ 427 if (child 428 && (device_is_a(child, "zstty")) 429 && (prom_getproplen(zsc->zsc_node, "keyboard") == 0)) { 430 struct kbd_ms_tty_attach_args kma; 431 struct tty *tp; 432 433 kma.kmta_tp = tp = zstty_get_tty_from_dev(child); 434 kma.kmta_dev = tp->t_dev; 435 kma.kmta_consdev = zsc_args.consdev; 436 437 /* Attach 'em if we got 'em. */ 438 #if (NKBD > 0) 439 if (channel == 0) { 440 kma.kmta_name = "keyboard"; 441 config_found(child, (void *)&kma, NULL, 442 CFARGS_NONE); 443 } 444 #endif 445 #if (NMS > 0) 446 if (channel == 1) { 447 kma.kmta_name = "mouse"; 448 config_found(child, (void *)&kma, NULL, 449 CFARGS_NONE); 450 } 451 #endif 452 } 453 #endif 454 } 455 456 /* 457 * Now safe to install interrupt handlers. Note the arguments 458 * to the interrupt handlers aren't used. Note, we only do this 459 * once since both SCCs interrupt at the same level and vector. 460 */ 461 bus_intr_establish(zsc->zsc_bustag, pri, IPL_SERIAL, zshard, zsc); 462 if (!(zsc->zsc_softintr = softint_establish(SOFTINT_SERIAL, zssoft, zsc))) 463 panic("zsattach: could not establish soft interrupt"); 464 465 evcnt_attach_dynamic(&zsc->zsc_intrcnt, EVCNT_TYPE_INTR, NULL, 466 device_xname(zsc->zsc_dev), "intr"); 467 468 469 /* 470 * Set the master interrupt enable and interrupt vector. 471 * (common to both channels, do it on A) 472 */ 473 cs = zsc->zsc_cs[0]; 474 zs_lock_chan(cs); 475 /* interrupt vector */ 476 zs_write_reg(cs, 2, zs_init_reg[2]); 477 /* master interrupt control (enable) */ 478 zs_write_reg(cs, 9, zs_init_reg[9]); 479 zs_unlock_chan(cs); 480 } 481 482 static int 483 zs_print(void *aux, const char *name) 484 { 485 struct zsc_attach_args *args = aux; 486 487 if (name != NULL) 488 aprint_normal("%s: ", name); 489 490 if (args->channel != -1) 491 aprint_normal(" channel %d", args->channel); 492 493 return (UNCONF); 494 } 495 496 static int 497 zshard(void *arg) 498 { 499 struct zsc_softc *zsc = arg; 500 int rr3, rval; 501 502 rval = 0; 503 while ((rr3 = zsc_intr_hard(zsc))) { 504 /* Count up the interrupts. */ 505 rval |= rr3; 506 zsc->zsc_intrcnt.ev_count++; 507 } 508 if (((zsc->zsc_cs[0] && zsc->zsc_cs[0]->cs_softreq) || 509 (zsc->zsc_cs[1] && zsc->zsc_cs[1]->cs_softreq)) && 510 zsc->zsc_softintr) { 511 softint_schedule(zsc->zsc_softintr); 512 } 513 return (rval); 514 } 515 516 int 517 zscheckintr(void *arg) 518 { 519 struct zsc_softc *zsc; 520 int unit, rval; 521 522 rval = 0; 523 for (unit = 0; unit < zs_cd.cd_ndevs; unit++) { 524 525 zsc = device_lookup_private(&zs_cd, unit); 526 if (zsc == NULL) 527 continue; 528 rval = (zshard((void *)zsc) || rval); 529 } 530 return (rval); 531 } 532 533 534 static void 535 zssoft(void *arg) 536 { 537 struct zsc_softc *zsc = arg; 538 539 #if 0 /* not yet */ 540 /* Make sure we call the tty layer with ttylock held. */ 541 ttylock(tp); 542 #endif 543 (void)zsc_intr_soft(zsc); 544 #if 0 /* not yet */ 545 ttyunlock(tp); 546 #endif 547 } 548 549 550 /* 551 * Compute the current baud rate given a ZS channel. 552 */ 553 static int 554 zs_get_speed(struct zs_chanstate *cs) 555 { 556 int tconst; 557 558 tconst = zs_read_reg(cs, 12); 559 tconst |= zs_read_reg(cs, 13) << 8; 560 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 561 } 562 563 /* 564 * MD functions for setting the baud rate and control modes. 565 */ 566 int 567 zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */) 568 { 569 int tconst, real_bps; 570 571 if (bps == 0) 572 return (0); 573 574 #ifdef DIAGNOSTIC 575 if (cs->cs_brg_clk == 0) 576 panic("zs_set_speed"); 577 #endif 578 579 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 580 if (tconst < 0) 581 return (EINVAL); 582 583 /* Convert back to make sure we can do it. */ 584 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 585 586 /* XXX - Allow some tolerance here? */ 587 if (real_bps != bps) 588 return (EINVAL); 589 590 cs->cs_preg[12] = tconst; 591 cs->cs_preg[13] = tconst >> 8; 592 593 /* Caller will stuff the pending registers. */ 594 return (0); 595 } 596 597 int 598 zs_set_modes(struct zs_chanstate *cs, int cflag) 599 { 600 601 /* 602 * Output hardware flow control on the chip is horrendous: 603 * if carrier detect drops, the receiver is disabled, and if 604 * CTS drops, the transmitter is stopped IN MID CHARACTER! 605 * Therefore, NEVER set the HFC bit, and instead use the 606 * status interrupt to detect CTS changes. 607 */ 608 zs_lock_chan(cs); 609 cs->cs_rr0_pps = 0; 610 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 611 cs->cs_rr0_dcd = 0; 612 if ((cflag & MDMBUF) == 0) 613 cs->cs_rr0_pps = ZSRR0_DCD; 614 } else 615 cs->cs_rr0_dcd = ZSRR0_DCD; 616 if ((cflag & CRTSCTS) != 0) { 617 cs->cs_wr5_dtr = ZSWR5_DTR; 618 cs->cs_wr5_rts = ZSWR5_RTS; 619 cs->cs_rr0_cts = ZSRR0_CTS; 620 } else if ((cflag & CDTRCTS) != 0) { 621 cs->cs_wr5_dtr = 0; 622 cs->cs_wr5_rts = ZSWR5_DTR; 623 cs->cs_rr0_cts = ZSRR0_CTS; 624 } else if ((cflag & MDMBUF) != 0) { 625 cs->cs_wr5_dtr = 0; 626 cs->cs_wr5_rts = ZSWR5_DTR; 627 cs->cs_rr0_cts = ZSRR0_DCD; 628 } else { 629 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 630 cs->cs_wr5_rts = 0; 631 cs->cs_rr0_cts = 0; 632 } 633 zs_unlock_chan(cs); 634 635 /* Caller will stuff the pending registers. */ 636 return (0); 637 } 638 639 640 /* 641 * Read or write the chip with suitable delays. 642 */ 643 644 u_char 645 zs_read_reg(struct zs_chanstate *cs, u_char reg) 646 { 647 u_char val; 648 649 *cs->cs_reg_csr = reg; 650 ZS_DELAY(); 651 val = *cs->cs_reg_csr; 652 ZS_DELAY(); 653 return (val); 654 } 655 656 void 657 zs_write_reg(struct zs_chanstate *cs, u_char reg, u_char val) 658 { 659 *cs->cs_reg_csr = reg; 660 ZS_DELAY(); 661 *cs->cs_reg_csr = val; 662 ZS_DELAY(); 663 } 664 665 u_char 666 zs_read_csr(struct zs_chanstate *cs) 667 { 668 u_char val; 669 670 val = *cs->cs_reg_csr; 671 ZS_DELAY(); 672 return (val); 673 } 674 675 void 676 zs_write_csr(struct zs_chanstate *cs, u_char val) 677 { 678 *cs->cs_reg_csr = val; 679 ZS_DELAY(); 680 } 681 682 u_char 683 zs_read_data(struct zs_chanstate *cs) 684 { 685 u_char val; 686 687 val = *cs->cs_reg_data; 688 ZS_DELAY(); 689 return (val); 690 } 691 692 void 693 zs_write_data(struct zs_chanstate *cs, u_char val) 694 { 695 *cs->cs_reg_data = val; 696 ZS_DELAY(); 697 } 698 699 /**************************************************************** 700 * Console support functions (Sun specific!) 701 * Note: this code is allowed to know about the layout of 702 * the chip registers, and uses that to keep things simple. 703 * XXX - I think I like the mvme167 code better. -gwr 704 ****************************************************************/ 705 706 /* 707 * Handle user request to enter kernel debugger. 708 */ 709 void 710 zs_abort(void) 711 { 712 volatile struct zschan *zc = zs_conschan_get; 713 int rr0; 714 715 /* Wait for end of break to avoid PROM abort. */ 716 /* XXX - Limit the wait? */ 717 do { 718 rr0 = zc->zc_csr; 719 ZS_DELAY(); 720 } while (rr0 & ZSRR0_BREAK); 721 722 #if defined(KGDB) 723 zskgdb(); 724 #elif defined(DDB) 725 if (!db_active) 726 cpu_Debugger(); 727 else 728 /* Debugger is probably hozed */ 729 callrom(); 730 #else 731 printf("stopping on keyboard abort\n"); 732 callrom(); 733 #endif 734 } 735 736 737 /* 738 * Polled input char. 739 */ 740 int 741 zs_getc(void *arg) 742 { 743 volatile struct zschan *zc = arg; 744 int s, c, rr0; 745 746 s = splhigh(); 747 /* Wait for a character to arrive. */ 748 do { 749 rr0 = zc->zc_csr; 750 ZS_DELAY(); 751 } while ((rr0 & ZSRR0_RX_READY) == 0); 752 753 c = zc->zc_data; 754 ZS_DELAY(); 755 splx(s); 756 757 /* 758 * This is used by the kd driver to read scan codes, 759 * so don't translate '\r' ==> '\n' here... 760 */ 761 return (c); 762 } 763 764 /* 765 * Polled output char. 766 */ 767 void 768 zs_putc(void *arg, int c) 769 { 770 volatile struct zschan *zc = arg; 771 int s, rr0; 772 773 s = splhigh(); 774 775 /* Wait for transmitter to become ready. */ 776 do { 777 rr0 = zc->zc_csr; 778 ZS_DELAY(); 779 } while ((rr0 & ZSRR0_TX_READY) == 0); 780 781 /* 782 * Send the next character. 783 * Now you'd think that this could be followed by a ZS_DELAY() 784 * just like all the other chip accesses, but it turns out that 785 * the `transmit-ready' interrupt isn't de-asserted until 786 * some period of time after the register write completes 787 * (more than a couple instructions). So to avoid stray 788 * interrupts we put in the 2us delay regardless of CPU model. 789 */ 790 zc->zc_data = c; 791 delay(2); 792 793 splx(s); 794 } 795 796 /*****************************************************************/ 797 798 799 800 801 /* 802 * Polled console input putchar. 803 */ 804 static int 805 zscngetc(dev_t dev) 806 { 807 return (zs_getc(zs_conschan_get)); 808 } 809 810 /* 811 * Polled console output putchar. 812 */ 813 static void 814 zscnputc(dev_t dev, int c) 815 { 816 zs_putc(zs_conschan_put, c); 817 } 818 819 int swallow_zsintrs; 820 821 static void 822 zscnpollc(dev_t dev, int on) 823 { 824 /* 825 * Need to tell zs driver to acknowledge all interrupts or we get 826 * annoying spurious interrupt messages. This is because mucking 827 * with spl() levels during polling does not prevent interrupts from 828 * being generated. 829 */ 830 831 if (on) swallow_zsintrs++; 832 else swallow_zsintrs--; 833 } 834 835 int 836 zs_console_flags(int promunit, int node, int channel) 837 { 838 int cookie, flags = 0; 839 char buf[255]; 840 841 /* 842 * We'll just do the OBP grovelling down here since that's 843 * the only type of firmware we support. 844 */ 845 846 /* Default to channel 0 if there are no explicit prom args */ 847 cookie = 0; 848 if (node == prom_instance_to_package(prom_stdin())) { 849 if (prom_getoption("input-device", buf, sizeof buf) == 0 && 850 strcmp("ttyb", buf) == 0) 851 cookie = 1; 852 853 if (channel == cookie) 854 flags |= ZS_HWFLAG_CONSOLE_INPUT; 855 } 856 857 if (node == prom_instance_to_package(prom_stdout())) { 858 if (prom_getoption("output-device", buf, sizeof buf) == 0 && 859 strcmp("ttyb", buf) == 0) 860 cookie = 1; 861 862 if (channel == cookie) 863 flags |= ZS_HWFLAG_CONSOLE_OUTPUT; 864 } 865 866 return (flags); 867 } 868 869
Indexes created Sat Nov 14 00:26:57 UTC 2026