| /src/external/gpl3/gdb/dist/sim/ppc/ |
| powerpc.igen | 58 :scratch::::FRS:FRS:
59 :cache:::uint64_t *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
60 :cache:::uint32_t:FRS_BITMASK:FRS:(1 << FRS)
1047 uint32_t::function::SINGLE:uint64_t FRS
1049 if (EXTRACTED64(FRS, 1, 11) > 896
1050 || EXTRACTED64(FRS, 1, 63) == 0)
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| powerpc.igen | 58 :scratch::::FRS:FRS:
59 :cache:::uint64_t *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
60 :cache:::uint32_t:FRS_BITMASK:FRS:(1 << FRS)
1047 uint32_t::function::SINGLE:uint64_t FRS
1049 if (EXTRACTED64(FRS, 1, 11) > 896
1050 || EXTRACTED64(FRS, 1, 63) == 0)
[all...] |
| /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/ |
| BugReporter.cpp | 1251 } else if (const auto *FRS = dyn_cast<CXXForRangeStmt>(Loop)) {
1252 Body = FRS->getBody();
1389 const auto *FRS = cast<CXXForRangeStmt>(S);
1390 return FRS->getCond() == Cond || FRS->getRangeInit() == Cond;
1400 if (const auto *FRS = dyn_cast<CXXForRangeStmt>(FL))
1401 return FRS->getInc() == S || FRS->getRangeStmt() == S ||
1402 FRS->getLoopVarStmt() || FRS->getRangeInit() == S
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 3244 /* The FRS field in an X form instruction or the FRT field in a D, X
3246 #define FRS FRC + 1
3247 #define FRT FRS
3252 #define FRSp FRS + 1
5249 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5338 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
7326 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7423 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
8751 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8776 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 3244 /* The FRS field in an X form instruction or the FRT field in a D, X
3246 #define FRS FRC + 1
3247 #define FRT FRS
3252 #define FRSp FRS + 1
5232 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5320 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
7295 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7392 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
8693 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8718 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 3166 /* The FRS field in an X form instruction or the FRT field in a D, X
3168 #define FRS FRC + 1
3169 #define FRT FRS
3174 #define FRSp FRS + 1
5113 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5201 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
7176 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7273 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
8574 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8599 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 3244 /* The FRS field in an X form instruction or the FRT field in a D, X
3246 #define FRS FRC + 1
3247 #define FRT FRS
3252 #define FRSp FRS + 1
5243 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
5332 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
7317 {"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
7414 {"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}},
8715 {"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}},
8740 {"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}
[all...] |
