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  /src/external/lgpl3/gmp/dist/mpn/x86/p6/sse2/
addmul_1.asm 1 dnl Intel P6/SSE2 mpn_addmul_1.
34 C * Write P6 specific SSE2 code.
37 include_mpn(`x86/pentium4/sse2/addmul_1.asm')
mul_1.asm 1 dnl Intel P6/SSE2 mpn_mul_1.
34 C * Write P6 specific SSE2 code. It should reach 3 c/l.
38 include_mpn(`x86/pentium4/sse2/mul_1.asm')
mod_1_1.asm 1 dnl Intel P6/SSE2 mpn_mod_1_1.
34 include_mpn(`x86/pentium4/sse2/mod_1_1.asm')
mod_1_4.asm 1 dnl Intel P6/SSE2 mpn_mod_1_4.
34 include_mpn(`x86/pentium4/sse2/mod_1_4.asm')
mul_basecase.asm 1 dnl Intel P6/SSE2 mpn_mul_basecase.
35 include_mpn(`x86/pentium4/sse2/mul_basecase.asm')
popcount.asm 1 dnl Intel P6/SSE2 mpn_popcount -- population count.
35 include_mpn(`x86/pentium4/sse2/popcount.asm')
sqr_basecase.asm 1 dnl Intel P6/SSE2 mpn_sqr_basecase.
35 include_mpn(`x86/pentium4/sse2/sqr_basecase.asm')
submul_1.asm 1 dnl Intel P6/SSE2 mpn_submul_1.
35 include_mpn(`x86/pentium4/sse2/submul_1.asm')
  /src/external/gpl3/gcc/dist/gcc/config/i386/
i386-isa.def 42 DEF_PTA(SSE2)
  /src/external/gpl3/gcc.old/dist/gcc/config/i386/
i386-isa.def 42 DEF_PTA(SSE2)
  /src/external/lgpl3/gmp/dist/mpn/x86/atom/sse2/
mod_1_1.asm 1 dnl Intel Atom/SSE2 mpn_mod_1_1.
34 include_mpn(`x86/pentium4/sse2/mod_1_1.asm')
mod_1_4.asm 1 dnl Intel Atom/SSE2 mpn_mod_1_4.
34 include_mpn(`x86/pentium4/sse2/mod_1_4.asm')
  /src/sys/external/mit/xen-include-public/dist/xen/include/public/arch-x86/
cpufeatureset.h 116 XEN_CPUFEATURE(SSE2, 0*32+26) /*A Streaming SIMD Extensions-2 */
  /src/external/apache2/llvm/dist/clang/lib/Basic/Targets/
X86.cpp 109 // X86_64 always has SSE2.
111 setFeatureEnabled(Features, "sse2", true);
327 .Case("+sse2", SSE2)
766 case SSE2:
787 case SSE2:
897 .Case("sse2", true)
991 .Case("sse2", SSELevel >= SSE2)
1189 case 't': // Any SSE register, when SSE2 is enabled
    [all...]
X86.h 55 SSE2,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86Subtarget.h 62 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
77 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
629 bool hasSSE2() const { return X86SSELevel >= SSE2; }
821 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
822 /// no-sse2). There isn't any reason to disable it if the target processor
  /src/external/lgpl3/gmp/dist/mpn/x86/
sec_tabselect.asm 53 C * Using SSE2 could result in many-fold speedup.
  /src/sys/arch/x86/conf/
files.x86 177 # Bitsliced AES with SSE2
183 # ChaCha with SSE2
  /src/external/lgpl3/gmp/dist/mpn/x86_64/fastsse/
sec_tabselect.asm 51 C arguments to allow efficient code using just SSE2. We would need to
52 C either use the SSE4_1 pcmpeqq, or find some other SSE2 sequence.
  /src/external/lgpl3/gmp/dist/mpn/x86/pentium4/sse2/
addmul_1.asm 1 dnl mpn_addmul_1 for Pentium 4 and P6 models with SSE2 (i.e., 9,D,E,F).
mod_1_1.asm 1 dnl x86-32 mpn_mod_1_1p for Pentium 4 and P6 models with SSE2 (i.e., 9,D,E,F).
38 C * Write a cps function that uses sse2 insns.
mul_1.asm 1 dnl mpn_mul_1 for Pentium 4 and P6 models with SSE2 (i.e., 9,D,E,F).
popcount.asm 1 dnl X86-32 and X86-64 mpn_popcount using SSE2.
67 C * There are 35 decode slots unused by the SSE2 instructions. Loop control
mod_1_4.asm 1 dnl x86-32 mpn_mod_1s_4p for Pentium 4 and P6 models with SSE2 (i.e. 9,D,E,F).
38 C * Write a cps function that uses sse2 insns.
  /src/external/lgpl3/gmp/dist/mpn/x86_64/
sec_tabselect.asm 51 C * Using SSE2/AVX2 could result in many-fold speedup.

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