| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86InstrFoldTables.cpp | 1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
31 // because as new instruction are added into holes in the X86 opcode map they
36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE }
[all...] |
| X86InstrInfo.cpp | 1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
45 #define DEBUG_TYPE "x86-instr-info"
57 " fuse, but the X86 backend currently can't"),
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
81 : X86::ADJCALLSTACKDOWN32),
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
83 : X86::ADJCALLSTACKUP32),
84 X86::CATCHRET
[all...] |
| X86InsertWait.cpp | 9 // This file defines the pass which insert x86 wait instructions after each
21 #include "X86.h"
35 #define DEBUG_TYPE "x86-insert-wait"
48 return "X86 insert wait instruction";
60 return (Reg == X86::FPCW || Reg == X86::FPSW ||
61 (Reg >= X86::ST0 && Reg <= X86::ST7));
77 case X86::FNINIT:
78 case X86::FLDCW16m
[all...] |
| X86MacroFusion.cpp | 1 //===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
9 /// \file This file contains the X86 implementation of the DAG scheduling
22 static X86::FirstMacroFusionInstKind classifyFirst(const MachineInstr &MI) {
23 return X86::classifyFirstOpcodeInMacroFusion(MI.getOpcode());
26 static X86::SecondMacroFusionInstKind classifySecond(const MachineInstr &MI) {
27 X86::CondCode CC = X86::getCondFromBranch(MI);
28 return X86::classifySecondCondCodeInMacroFusion(CC);
44 const X86::SecondMacroFusionInstKind BranchKind = classifySecond(SecondMI);
46 if (BranchKind == X86::SecondMacroFusionInstKind::Invalid
[all...] |
| X86FloatingPoint.cpp | 25 #include "X86.h"
52 #define DEBUG_TYPE "x86-codegen"
84 StringRef getPassName() const override { return "X86 FP Stackifier"; }
131 static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133 Mask |= 1 << (Reg - X86::FP0);
195 /// getStackEntry - Return the X86::FP<n> register in register ST(i).
202 /// getSTReg - Return the X86::ST(i) register which contains the specifie
[all...] |
| X86MCInstLower.cpp | 1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
330 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
348 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
349 if (Op0 == X86::AX && Op1 == X86::AL)
350 NewOpcode = X86::CBW
[all...] |
| X86AvoidStoreForwardingBlocks.cpp | 36 #include "X86.h"
55 #define DEBUG_TYPE "x86-avoid-SFB"
58 "x86-disable-avoid-SFB", cl::Hidden,
59 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(false));
62 "x86-sfb-inspection-limit",
63 cl::desc("X86: Number of instructions backward to "
77 return "X86 Avoid Store Forwarding Blocks";
134 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm ||
135 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm |
[all...] |
| X86EvexToVex.cpp | 24 #include "X86.h"
56 #define EVEX2VEX_NAME "x86-evex-to-vex-compress"
120 if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
124 if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
138 assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
154 case X86::VALIGNDZ128rri:
155 case X86::VALIGNDZ128rmi
[all...] |
| X86WinAllocaExpander.cpp | 17 #include "X86.h"
67 StringRef getPassName() const override { return "X86 WinAlloca Expander"; }
81 assert(MI->getOpcode() == X86::WIN_ALLOCA_32 ||
82 MI->getOpcode() == X86::WIN_ALLOCA_64);
89 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) ||
113 case X86::PUSH32i8:
114 case X86::PUSH32r:
115 case X86::PUSH32rmm:
116 case X86::PUSH32rmr
[all...] |
| X86FlagsCopyLowering.cpp | 18 /// SAHF don't work on all x86 processors and are often quite slow compared to
23 #include "X86.h"
65 #define PASS_KEY "x86-flags-copy-lowering"
76 using CondRegArray = std::array<unsigned, X86::LAST_VALID_COND + 1>;
82 StringRef getPassName() const override { return "X86 EFLAGS copy lowering"; }
102 const DebugLoc &TestLoc, X86::CondCode Cond);
105 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
136 "X86 EFLAGS copy lowering", false, false)
138 "X86 EFLAGS copy lowering", false, false)
175 case X86::MNEMONIC##8##SUFFIX:
[all...] |
| X86ExpandPseudo.cpp | 15 #include "X86.h"
29 #define DEBUG_TYPE "x86-pseudo"
30 #define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
59 return "X86 pseudo instruction expansion pass";
75 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
106 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
107 .addReg(X86::RIP)
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
115 .addReg(X86::R11)
[all...] |
| X86RegisterInfo.cpp | 1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // on X86.
43 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
47 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
50 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
66 StackPtr = Use64BitReg ? X86::RSP : X86::ESP
[all...] |
| X86TargetTransformInfo.h | 1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
10 /// X86 target machine. It uses the target's detailed information to
41 X86::Feature64Bit,
44 X86::FeatureNOPL,
45 X86::FeatureCMPXCHG16B,
46 X86::FeatureLAHFSAHF,
49 X86::FeatureFast11ByteNOP,
50 X86::FeatureFast15ByteNOP,
51 X86::FeatureFastBEXTR,
52 X86::FeatureFastHorizontalOps
[all...] |
| X86DomainReassignment.cpp | 15 #include "X86.h"
33 #define DEBUG_TYPE "x86-domain-reassignment"
38 "disable-x86-domain-reassignment", cl::Hidden,
39 cl::desc("X86: Disable Virtual Register Reassignment."), cl::init(false));
45 return X86::GR64RegClass.hasSubClassEq(RC) ||
46 X86::GR32RegClass.hasSubClassEq(RC) ||
47 X86::GR16RegClass.hasSubClassEq(RC) ||
48 X86::GR8RegClass.hasSubClassEq(RC);
53 return X86::VK16RegClass.hasSubClassEq(RC);
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)
[all...] |
| X86CallFrameOptimization.cpp | 1 //===----- X86CallFrameOptimization.cpp - Optimize x86 call sequences -----===//
9 // This file defines a pass that optimizes call sequences on x86.
20 #include "X86.h"
52 #define DEBUG_TYPE "x86-cf-opt"
55 NoX86CFOpt("no-x86-call-frame-opt",
56 cl::desc("Avoid optimizing x86 call frames for size"),
117 StringRef getPassName() const override { return "X86 Optimize Call Frame"; }
130 "X86 Call Frame Optimization", false, false)
288 case X86::AND16mi8:
289 case X86::AND32mi8
[all...] |
| X86FixupSetCC.cpp | 10 // X86 setcc instructions are modeled to have no input arguments, and a single
22 #include "X86.h"
32 #define DEBUG_TYPE "x86-fixup-setcc"
43 StringRef getPassName() const override { return "X86 Fixup SetCC"; }
72 if (MI.definesRegister(X86::EFLAGS))
78 if (MI.getOpcode() != X86::SETCCr)
83 if (Use.getOpcode() == X86::MOVZX32rr8)
97 if (FlagsDefMI->readsRegister(X86::EFLAGS))
102 ? &X86::GR32RegClass
103 : &X86::GR32_ABCDRegClass
[all...] |
| X86LoadValueInjectionRetHardening.cpp | 1 //===-- X86LoadValueInjectionRetHardening.cpp - LVI RET hardening for x86 --==//
20 #include "X86.h"
34 #define PASS_KEY "x86-lvi-ret"
48 return "X86 Load Value Injection (LVI) Ret-Hardening";
79 if (MBBI->getOpcode() != X86::RETQ)
83 if (ClobberReg != X86::NoRegister) {
84 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::POP64r))
87 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE));
88 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::JMP64r))
97 BuildMI(MBB, MBBI, DebugLoc(), TII->get(X86::LFENCE))
[all...] |
| X86LowerTileCopy.cpp | 19 #include "X86.h"
37 #define DEBUG_TYPE "x86-lower-tile-copy"
51 StringRef getPassName() const override { return "X86 Lower Tile Copy"; }
87 if (!X86::TILERegClass.contains(DstReg, SrcReg))
92 unsigned Size = TRI->getSpillSize(X86::TILERegClass);
93 Align Alignment = TRI->getSpillAlign(X86::TILERegClass);
96 Size = TRI->getSpillSize(X86::GR64RegClass);
97 Alignment = TRI->getSpillAlign(X86::GR64RegClass);
102 Register GR64Cand = X86::RAX;
106 BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| X86InstPrinterCommon.cpp | 1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
111 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break;
112 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break;
113 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break;
114 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break;
115 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break
[all...] |
| X86MCTargetDesc.cpp | 1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
72 return MI.getFlags() & X86::IP_HAS_LOCK;
77 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
87 {codeview::RegisterId::AL, X86::AL},
88 {codeview::RegisterId::CL, X86::CL},
89 {codeview::RegisterId::DL, X86::DL},
90 {codeview::RegisterId::BL, X86::BL},
91 {codeview::RegisterId::AH, X86::AH}
[all...] |
| X86ATTInstPrinter.cpp | 57 if (MI->getOpcode() == X86::CALLpcrel32 &&
58 (STI.getFeatureBits()[X86::Mode64Bit])) {
67 else if (MI->getOpcode() == X86::DATA16_PREFIX &&
68 STI.getFeatureBits()[X86::Mode16Bit]) {
92 case X86::CMPPDrmi: case X86::CMPPDrri:
93 case X86::CMPPSrmi: case X86::CMPPSrri:
94 case X86::CMPSDrm: case X86::CMPSDrr
[all...] |
| X86IntelInstPrinter.cpp | 46 if (MI->getOpcode() == X86::DATA16_PREFIX &&
47 STI.getFeatureBits()[X86::Mode16Bit]) {
72 case X86::CMPPDrmi: case X86::CMPPDrri:
73 case X86::CMPPSrmi: case X86::CMPPSrri:
74 case X86::CMPSDrm: case X86::CMPSDrr:
75 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int
[all...] |
| X86BaseInfo.h | 1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
10 // the X86 target useful for the compiler back-end and the MC libraries.
26 namespace X86 {
78 // X86 specific condition code. These correspond to X86_*_COND in
102 // which can't be represented on x86 with a single condition. These
145 case X86::TEST16i16:
146 case X86::TEST16mr:
147 case X86::TEST16ri:
148 case X86::TEST16rr:
149 case X86::TEST32i32
[all...] |
| X86AsmBackend.cpp | 1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
40 /// A wrapper for holding a mask of the values from X86::AlignBranchBoundaryKind
53 addKind(X86::AlignBranchFused);
55 addKind(X86::AlignBranchJcc);
57 addKind(X86::AlignBranchJmp);
59 addKind(X86::AlignBranchCall);
61 addKind(X86::AlignBranchRet);
63 addKind(X86::AlignBranchIndirect);
66 << " to -x86-align-branch=; each element must be one of: fused, "
73 void addKind(X86::AlignBranchBoundaryKind Value) { AlignBranchKind |= Value;
[all...] |
| X86WinCOFFObjectWriter.cpp | 1 //===-- X86WinCOFFObjectWriter.cpp - X86 Win COFF Writer ------------------===//
47 if (FixupKind != FK_Data_4 && FixupKind != llvm::X86::reloc_signed_4byte) {
60 case X86::reloc_riprel_4byte:
61 case X86::reloc_riprel_4byte_movq_load:
62 case X86::reloc_riprel_4byte_relax:
63 case X86::reloc_riprel_4byte_relax_rex:
64 case X86::reloc_branch_4byte_pcrel:
67 case X86::reloc_signed_4byte:
68 case X86::reloc_signed_4byte_relax:
87 case X86::reloc_riprel_4byte
[all...] |
