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    Searched refs:imc (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/modules/imc/
Makefile 9 KMOD= imc
10 IOCONF= imc.ioconf
12 SRCS+= imc.c
  /src/share/man/man4/man4.sgimips/
Makefile 4 imc.4 intro.4 light.4 mace.4 mavb.4 mec.4 newport.4 pic.4 sq.4 wdsc.4
  /src/sys/arch/x86/pci/imcsmb/
imc.c 1 /* $NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $ */
68 __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $");
87 * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
89 * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
93 * The publicly available documentation for the iMC SMBus controllers can be
107 * The iMC SMBus controllers do not support interrupts (thus, they must be
108 * polled for IO completion). All of the iMC registers are in PCI configuration
169 "Intel Sandybridge Xeon iMC 0 SMBus controllers" },
171 "Intel Ivybridge Xeon iMC 0 SMBus controllers" },
173 "Intel Haswell Xeon iMC 0 SMBus controllers" }
    [all...]
  /src/sys/dev/acpi/
apei_hest.c 696 ACPI_HEST_IA_MACHINE_CHECK *const imc = container_of(header, local in function:apei_hest_attach_source
702 if (maxlen < sizeof(*imc))
704 maxlen -= sizeof(*imc);
705 ACPI_HEST_IA_ERROR_BANK *const bank = (void *)(imc + 1);
706 if (maxlen < imc->NumHardwareBanks*sizeof(*bank))
708 return (ACPI_HEST_HEADER *)(bank + imc->NumHardwareBanks);
  /src/sys/arch/sgimips/dev/
imc.c 1 /* $NetBSD: imc.c,v 1.38 2025/10/19 20:35:02 thorpej Exp $ */
31 __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.38 2025/10/19 20:35:02 thorpej Exp $");
67 CFATTACH_DECL_NEW(imc, sizeof(struct imc_softc),
  /src/sys/modules/
Makefile 474 SUBDIR+= imc

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