| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.c | 46 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
47 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
82 enum phy phy)
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy);
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val)
141 enum phy phy = PHY_A; local
299 enum phy phy; local
353 enum phy phy; local
[all...] |
| intel_combo_phy.h | 14 enum phy;
19 enum phy phy, bool is_dsi,
|
| intel_dpio_phy.c | 39 * ports. DPIO is the name given to such a display PHY. These PHYs
42 * sideband. VLV has one such PHY for driving ports B and C, and CHV
43 * adds another PHY for driving port D. Each PHY responds to specific
46 * Each display PHY is made up of one or two channels. Each channel
63 * Additionally the PHY also contains an AUX lane with AUX blocks
72 * For dual channel PHY (VLV/CHV):
85 * For single channel PHY (CHV):
91 * On BXT the entire PHY channel corresponds to the port. That means
101 * Dual channel PHY (VLV/CHV/BXT
277 enum dpio_phy phy; local
600 enum dpio_phy phy; local
626 enum dpio_phy phy; local
[all...] |
| intel_dpio_phy.h | 21 enum dpio_phy *phy, enum dpio_channel *ch);
25 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
26 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
28 enum dpio_phy phy);
30 enum dpio_phy phy);
|
| /src/sys/dev/pci/cxgb/ |
| cxgb_ael1002.c | 51 static void ael100x_txon(struct cphy *phy)
53 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL;
56 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio);
60 static int ael1002_power_down(struct cphy *phy, int enable)
64 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
66 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
71 static int ael1002_reset(struct cphy *phy, int wait)
75 if ((err = ael1002_power_down(phy, 0)) ||
76 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
77 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) |
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 13 #include <dt-bindings/phy/phy-cadence.h>
14 #include <dt-bindings/phy/phy.h>
32 phy-mode = "usxgmii";
35 phy-names = "mac", "serdes";
44 phy-mode = "usxgmii";
47 phy-names = "mac", "serdes";
65 serdes2_usxgmii_link: phy@2 {
68 #phy-cells = <0>
[all...] |
| k3-j784s4-evm-quad-port-eth-exp1.dtso | 18 #include <dt-bindings/phy/phy-cadence.h>
19 #include <dt-bindings/phy/phy.h>
39 phy-handle = <&cpsw9g_phy1>;
40 phy-mode = "qsgmii";
43 phy-names = "mac", "serdes";
48 phy-handle = <&cpsw9g_phy2>;
49 phy-mode = "qsgmii";
52 phy-names = "mac", "serdes"
[all...] |
| /src/sys/dev/pci/igc/ |
| igc_phy.c | 16 * igc_init_phy_ops_generic - Initialize PHY function pointers
24 struct igc_phy_info *phy = &hw->phy; local
28 phy->ops.init_params = igc_null_ops_generic;
29 phy->ops.acquire = igc_null_ops_generic;
30 phy->ops.check_reset_block = igc_null_ops_generic;
31 phy->ops.force_speed_duplex = igc_null_ops_generic;
32 phy->ops.get_info = igc_null_ops_generic;
33 phy->ops.set_page = igc_null_set_page;
34 phy->ops.read_reg = igc_null_read_reg
142 struct igc_phy_info *phy = &hw->phy; local
179 struct igc_phy_info *phy = &hw->phy; local
237 struct igc_phy_info *phy = &hw->phy; local
292 struct igc_phy_info *phy = &hw->phy; local
470 struct igc_phy_info *phy = &hw->phy; local
586 struct igc_phy_info *phy = &hw->phy; local
704 struct igc_phy_info *phy = &hw->phy; local
[all...] |
| /src/sys/arch/evbarm/conf/ |
| RPI | 134 # MII/PHY support
135 exphy* at mii? phy ? # 3Com internal PHYs
136 gentbi* at mii? phy ? # Generic Ten-Bit 1000BASE-[CLS]X PHYs
137 glxtphy* at mii? phy ? # Level One LXT-1000 PHYs
138 gphyter* at mii? phy ? # NS83861 Gig-E PHY
139 icsphy* at mii? phy ? # Integrated Circuit Systems ICS189x
140 igphy* at mii? phy ? # Intel IGP01E1000
141 ihphy* at mii? phy ? # Intel 82577 PHYs
142 ikphy* at mii? phy ? # Intel 82563 PHY
[all...] |
| ARMADAXP | 270 acphy* at mii? phy ? # Altima AC101 10/100 PHY
271 amhphy* at mii? phy ? # AMD 79c901 PHY (10BASE-T part)
272 bmtphy* at mii? phy ? # Broadcom BCM5201/5202 PHYs
273 brgphy* at mii? phy ? # Broadcom BCM5400/5401 Gig-E PHYs
274 ciphy* at mii? phy ? # Cicada CS8201 Gig-E PHYs
275 dmphy* at mii? phy ? # Davicom DM9101 PHYs
276 exphy* at mii? phy ? # 3Com internal PHYs
277 gentbi* at mii? phy ? # Generic ten-bit 1000BASE-X PHY
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/allwinner/ |
| sun8i-h3-orangepi-plus2e.dts | 45 * with 2G RAM and an external gbit ethernet phy.
68 phy-supply = <®_gmac_3v3>;
69 phy-handle = <&ext_rgmii_phy>;
70 phy-mode = "rgmii-id";
75 ext_rgmii_phy: ethernet-phy@1 {
76 compatible = "ethernet-phy-ieee802.3-c22";
|
| sun8i-h3-zeropi.dts | 65 ext_rgmii_phy: ethernet-phy@7 {
66 compatible = "ethernet-phy-ieee802.3-c22";
74 phy-supply = <®_gmac_3v3>;
75 phy-handle = <&ext_rgmii_phy>;
76 phy-mode = "rgmii-id";
|
| sun8i-h3-nanopi-neo.dts | 59 phy-handle = <&int_mii_phy>;
60 phy-mode = "mii";
|
| sun6i-a31s-cs908.dts | 70 phy-handle = <&phy1>;
71 phy-mode = "mii";
82 phy1: ethernet-phy@1 {
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| bcm958742t.dts | 43 enet-phy-lane-swap;
|
| /src/sys/dev/mii/ |
| ukphy_subr.c | 34 * Subroutines shared by the ukphy driver and other PHY drivers.
53 * Media status subroutine. If a PHY driver does media detection simply
57 ukphy_status(struct mii_softc *phy)
59 struct mii_data *mii = phy->mii_pdata;
68 PHY_READ(phy, MII_BMSR, &bmsr);
69 PHY_READ(phy, MII_BMSR, &bmsr);
73 PHY_READ(phy, MII_BMCR, &bmcr);
95 PHY_READ(phy, MII_ANAR, &anar);
96 PHY_READ(phy, MII_ANLPAR, &anlpar);
98 if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 &
[all...] |
| /src/sys/arch/hpcmips/vr/ |
| vrdmaau.c | 96 u_int32_t phy; local
101 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAH_REG_W, phy >> 16);
105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAL_REG_W, phy & 0xffff);
113 u_int32_t phy; local
118 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
121 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAH_REG_W, phy >> 16);
122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAL_REG_W, phy & 0xffff);
130 u_int32_t phy; local
135 if ((err = vrdmaau_phy_addr(sc, addr, &phy)))
[all...] |
| /src/sys/arch/arm/dts/ |
| sun8i-h2-plus-bananapi-p2-zero.dts | 57 phy-handle = <&int_mii_phy>;
58 phy-mode = "mii";
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_usb3phy.c | 71 { .compat = "allwinner,sun50i-h6-usb3-phy", .value = USB3PHY_H6 },
91 #define PHY_READ(phy, reg) \
92 bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))
93 #define PHY_WRITE(phy, reg, val) \
94 bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))
115 struct sunxi_usb3phy * const phy = priv; local
119 val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL);
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val)
170 struct sunxi_usb3phy *phy = &sc->sc_phy; local
[all...] |
| /src/sys/dev/fdt/ |
| fdt_phy.c | 84 struct fdtbus_phy *phy = NULL; local
109 if (of_getprop_uint32(pc_phandle, "#phy-cells", &phy_cells))
118 phy = kmem_alloc(sizeof(*phy), KM_SLEEP);
119 phy->phy_pc = pc;
120 phy->phy_priv = phy_priv;
133 return phy;
142 err = fdtbus_get_index(phandle, "phy-names", phyname, &index);
150 fdtbus_phy_put(struct fdtbus_phy *phy)
152 struct fdtbus_phy_controller *pc = phy->phy_pc
[all...] |
| /src/sys/dev/pci/ixgbe/ |
| ixgbe_phy.c | 120 u32 swfw_mask = hw->phy.phy_semaphore_mask;
197 u32 swfw_mask = hw->phy.phy_semaphore_mask;
250 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
257 struct ixgbe_phy_info *phy = &hw->phy; local
261 /* PHY */
262 phy->ops.identify = ixgbe_identify_phy_generic;
263 phy->ops.reset = ixgbe_reset_phy_generic;
264 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
265 phy->ops.write_reg = ixgbe_write_phy_reg_generic
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/ |
| imx6q-b450v3.dts | 119 phy-handle = <&switchphy0>;
125 phy-handle = <&switchphy1>;
131 phy-handle = <&switchphy2>;
137 phy-handle = <&switchphy3>;
144 phy-handle = <&switchphy4>;
|
| imx6qdl-sr-som.dtsi | 56 phy-mode = "rgmii-id";
59 * The PHY seems to require a long-enough reset duration to avoid
60 * some rare issues where the PHY gets stuck in an inconsistent and
63 phy-reset-duration = <10>;
64 phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
72 * The PHY can appear at either address 0 or 4 due to the
75 ethernet-phy@0 {
81 ethernet-phy@4 {
91 ethernet-phy@1 {
93 adi,phy-output-clock = "125mhz-free-running"
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| dv-eth_phy.c | 81 struct eth_phy *phy = hw_data (me); local
88 reg_off = addr - phy->base;
89 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
115 struct eth_phy *phy = hw_data (me); local
119 reg_off = addr - phy->base;
120 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
149 attach_eth_phy_regs (struct hw *me, struct eth_phy *phy)
173 phy->base = attach_address;
179 struct eth_phy *phy; local
181 phy = HW_ZALLOC (me, struct eth_phy)
[all...] |
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| dv-eth_phy.c | 81 struct eth_phy *phy = hw_data (me); local
88 reg_off = addr - phy->base;
89 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
115 struct eth_phy *phy = hw_data (me); local
119 reg_off = addr - phy->base;
120 valuep = (void *)((uintptr_t)phy + reg_base() + reg_off);
149 attach_eth_phy_regs (struct hw *me, struct eth_phy *phy)
173 phy->base = attach_address;
179 struct eth_phy *phy; local
181 phy = HW_ZALLOC (me, struct eth_phy)
[all...] |
