| /src/sys/arch/arm/arm/ |
| cpu_in_cksum.S | 53 * r2 off
74 subs r2, r2, r1 /* offset = offset - mbuf length */
81 add r0, r2, r0 /* data += offset (offset is < 0) */
84 rsb r1, r2, #0x00 /* length = remainder of mbuf to read */
103 adds r2, r1, #0x00
112 movne r2, r2, ror #8
113 adds r8, r8, r2
120 lsls r2, r0, #1
[all...] |
| cpufunc_asm_arm8.S | 44 bic r2, r3, #0x11 /* turn off dynamic clocking
46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
48 bic r2, r3, r0 /* Clear bits */
49 eor r2, r2, r1 /* XOR bits */
50 bic r2, r2, #0x10 /* clear the L bit */
52 bic r1, r2, #0x01 /* still keep dynamic clocking off */
58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
71 orr r2, r3, #(I32_bit | F32_bit
[all...] |
| bus_space_a2x.S | 44 ldrb r0, [r1, r2, lsl #1]
50 lsls r2, r2, #1
51 ldrh r0, [r1, r2]
56 lsls r2, r2, #1
57 ldrh r0, [r1, r2]
64 ldr r0, [r1, r2, lsl #1]
69 ldr r0, [r1, r2, lsl #1]
80 lsls r2, r2, #
[all...] |
| bus_space_a4x.S | 44 ldrb r0, [r1, r2, lsl #2]
50 lsls r2, r2, #2
51 ldrh r0, [r1, r2]
56 lsls r2, r2, #2
57 ldrh r0, [r1, r2]
64 ldr r0, [r1, r2, lsl #2]
69 ldr r0, [r1, r2, lsl #2]
80 lsls r2, r2, #
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/bpf/ |
| mem.s | 13 mov %r2, 0x1000
16 stxb [%r2+0], %r1
17 stxh [%r2+2], %r1
18 stxw [%r2+4], %r1
19 stxdw [%r2+8], %r1
21 stb [%r2+16], 0x5a
22 sth [%r2+18], 0xcafe
23 stw [%r2+20], -1091568946 /* 0xbeefface */
24 stdw [%r2+24], 0x7eadbeef
26 ldxb %r1, [%r2+16
[all...] |
| alu.s | 13 mov %r2, -1
17 add %r2, -1
18 add %r1, %r2
25 sub %r2, %r1
26 fail_ne %r2, 8
29 mul %r2, %r2 /* r2 = 64 */
30 mul %r2, 3 /* r2 = 192 *
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bpf/ |
| mem.s | 13 mov %r2, 0x1000
16 stxb [%r2+0], %r1
17 stxh [%r2+2], %r1
18 stxw [%r2+4], %r1
19 stxdw [%r2+8], %r1
21 stb [%r2+16], 0x5a
22 sth [%r2+18], 0xcafe
23 stw [%r2+20], -1091568946 /* 0xbeefface */
24 stdw [%r2+24], 0x7eadbeef
26 ldxb %r1, [%r2+16
[all...] |
| alu.s | 13 mov %r2, -1
17 add %r2, -1
18 add %r1, %r2
25 sub %r2, %r1
26 fail_ne %r2, 8
29 mul %r2, %r2 /* r2 = 64 */
30 mul %r2, 3 /* r2 = 192 *
[all...] |
| /src/sys/arch/epoc32/epoc32/ |
| external_io_asm.S | 46 mov r2, r2, lsl r0
47 ldrb r0, [r1, r2]
51 mov r2, r2, lsl r0
52 ldr r0, [r1, r2]
60 mov r2, r2, lsl r0
61 strb r3, [r1, r2]
65 mov r2, r2, lsl r
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/example-synacor/ |
| add.s | 10 SET r2, 2
11 ADD r2, r2, r2
12 EQ r3, r2, 4
15 ADD r1, 100, r2
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/example-synacor/ |
| add.s | 10 SET r2, 2
11 ADD r2, r2, r2
12 EQ r3, r2, 4
15 ADD r1, 100, r2
|
| /src/sys/arch/acorn32/eb7500atx/ |
| rsbus_io_asm.S | 46 mov r2, r2, lsl r0
47 ldrb r0, [r1, r2]
51 mov r2, r2, lsl r0
52 ldr r0, [r1, r2]
58 mov r2, r2, lsl r0
59 ldr r0, [r1, r2]
67 mov r2, r2, lsl r
[all...] |
| /src/sys/arch/acorn32/podulebus/ |
| podulebus_io_asm.S | 46 mov r2, r2, lsl r0
47 ldrb r0, [r1, r2]
51 mov r2, r2, lsl r0
52 ldr r0, [r1, r2]
58 mov r2, r2, lsl r0
59 ldr r0, [r1, r2]
67 mov r2, r2, lsl r
[all...] |
| /src/sys/arch/arm/arm32/ |
| setstack.S | 64 bic r2, r3, #(PSR_MODE)
65 orr r2, r2, r0
66 msr cpsr_c, r2
84 bic r2, r3, #(PSR_MODE)
85 orr r2, r2, r0
86 msr cpsr_c, r2
|
| /src/sys/external/bsd/compiler_rt/dist/lib/builtins/arm/ |
| bswapdi2.S | 31 // r2 = rev(r0)
32 eor r2, r0, r0, ror #16
33 bic r2, r2, #0xff0000
34 mov r2, r2, lsr #8
35 eor r2, r2, r0, ror #8
42 rev r2, r0 // r2 = rev(r0
[all...] |
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| add_shift.S | 11 r2=0;
12 r2.h=0x4000;
13 r2=(r2+r1)<<2;
14 dbga (r2.l,0x0);
15 dbga (r2.h,0x0);
20 r2=0;
21 r2.h=0x4000;
22 r2=(r2+r1)<<1
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| add_shift.S | 11 r2=0;
12 r2.h=0x4000;
13 r2=(r2+r1)<<2;
14 dbga (r2.l,0x0);
15 dbga (r2.h,0x0);
20 r2=0;
21 r2.h=0x4000;
22 r2=(r2+r1)<<1
[all...] |
| /src/external/mpl/bind/dist/lib/isc/ |
| region.c | 25 isc_region_compare(isc_region_t *r1, isc_region_t *r2) {
30 REQUIRE(r2 != NULL);
32 REQUIRE(r2->base != NULL);
34 l = (r1->length < r2->length) ? r1->length : r2->length;
36 if ((result = memcmp(r1->base, r2->base, l)) != 0) {
39 return (r1->length == r2->length) ? 0
40 : (r1->length < r2->length) ? -1
|
| /src/sys/arch/arm/footbridge/isa/ |
| isa_io_asm.S | 88 ldrb r0, [r1, r2]
93 ldrh r0, [r1, r2] /*.word 0xe19100b2*/
98 ldr r0, [r1, r2]
107 add r0, r1, r2
109 ldr r2, [sp, #0]
110 teq r2, #0
116 subs r2, r2, #1
122 add r0, r1, r2
124 ldr r2, [sp, #0
[all...] |
| /src/sys/arch/evbarm/tsarm/isa/ |
| isa_io_asm.S | 92 ldrb r0, [r1, r2]
97 ldrh r0, [r1, r2]
102 ldr r0, [r1, r2]
111 add r0, r1, r2
114 ldr r2, [sp, #0]
115 teq r2, #0
121 subs r2, r2, #1
127 add r0, r1, r2
129 ldr r2, [sp, #0
[all...] |
| /src/common/lib/libc/arch/arm/string/ |
| strncmp.S | 37 subs r2, r2, #1
47 adds r3, r0, r2
51 add ip, r0, r2
55 ldrb r2, [r0]
60 cmp r2, #1 /* NUL? */
62 cmp r2, r3 /* different? */
64 ldrb r2, [r0], #1
67 cmpcs r2, #1
68 cmpcs r2, r
[all...] |
| strcmp.S | 37 1: ldrb r2, [r0], #1
39 cmp r2, #1
40 cmpcs r2, r3
43 1: ldrb r2, [r0]
46 cmp r2, #1
48 cmp r2, r3
51 2: subs r0, r2, r3
|
| /src/external/gpl3/gdb/dist/sim/testsuite/sh/ |
| shll8.s | 25 mov #1, r2
26 shll r2
27 shll r2
28 shll r2
29 shll r2
30 shll r2
31 shll r2
32 shll r2
33 shll r2
34 cmp/eq r1, r2
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/testsuite/sh/ |
| shll8.s | 25 mov #1, r2
26 shll r2
27 shll r2
28 shll r2
29 shll r2
30 shll r2
31 shll r2
32 shll r2
33 shll r2
34 cmp/eq r1, r2
[all...] |
| /src/sys/arch/arm/sa11x0/ |
| sa11x0_io_asm.S | 47 ldrb r0, [r1, r2]
51 ldrh r0, [r1, r2]
55 ldr r0, [r1, r2]
63 strb r3, [r1, r2]
67 strh r3, [r1, r2]
71 str r3, [r1, r2]
80 add r0, r1, r2
81 ldr r2, [sp, #0]
82 cmp r2, #0x00000000
87 subs r2, r2, #0x0000000
[all...] |
