| /src/usr.sbin/btattach/ |
| init_ericsson.c | 47 uint8_t rate; local
50 case B460800: rate = 0x00; break;
51 case B230400: rate = 0x01; break;
52 case B115200: rate = 0x02; break;
53 case B57600: rate = 0x03; break;
54 case B28800: rate = 0x04; break;
55 case B14400: rate = 0x05; break;
56 case B7200: rate = 0x06; break;
58 case B3600: rate = 0x07; break;
60 case B1800: rate = 0x08; break
[all...] |
| init_st.c | 50 uint8_t rate; local
53 case B9600: rate = 0x09; break;
54 case B19200: rate = 0x0b; break;
55 case B38400: rate = 0x0d; break;
56 case B57600: rate = 0x0e; break;
57 case B115200: rate = 0x10; break;
58 case B230400: rate = 0x12; break;
59 case B460800: rate = 0x13; break;
60 case B921600: rate = 0x14; break;
65 uart_send_cmd(fd, HCI_CMD_ST_SET_UART_BAUD_RATE, &rate, sizeof(rate))
[all...] |
| init_bcm2035.c | 53 uint16_t rate; local
63 case B57600: rate = 0xe600; break;
64 case B115200: rate = 0xf300; break;
65 case B230400: rate = 0xfa22; break;
66 case B460800: rate = 0xfd22; break;
67 case B921600: rate = 0xff55; break;
72 rate = htole16(rate);
73 uart_send_cmd(fd, HCI_CMD_BCM2035_SET_UART_BAUD_RATE, &rate, sizeof(rate));
[all...] |
| init_digi.c | 50 uint8_t rate; local
53 case B57600: rate = 0x08; break;
54 case B115200: rate = 0x09; break;
59 uart_send_cmd(fd, HCI_CMD_DIGIANSWER_SET_UART_BAUD_RATE, &rate, sizeof(rate));
|
| init_unistone.c | 77 uint8_t rate, v[2]; local
81 case B9600: rate = 0x00; break;
82 case B19200: rate = 0x01; break;
83 case B38400: rate = 0x02; break;
84 case B57600: rate = 0x03; break;
85 case B115200: rate = 0x04; break;
86 case B230400: rate = 0x05; break;
87 case B460800: rate = 0x06; break;
88 case B921600: rate = 0x07; break;
90 case B1843200: rate = 0x08; break
[all...] |
| init_bcm43xx.c | 94 uint8_t rate[6], clock; local
102 memset(rate, 0, sizeof(rate));
152 rate[2] = speed;
153 rate[3] = speed >> 8;
154 rate[4] = speed >> 16;
155 rate[5] = speed >> 24;
157 uart_send_cmd(fd, HCI_CMD_BCM43XX_SET_UART_BAUD_RATE, &rate, sizeof(rate));
|
| /src/usr.sbin/altq/tbrconfig/ |
| tbrconfig.c | 50 static u_int size_bucket(const char *ifname, const u_int rate);
51 static u_int autosize_bucket(const char *ifname, const u_int rate);
69 u_int rate, depth; local
73 rate = 0;
95 rate = (u_int)atobps(argv[1]);
98 depth = autosize_bucket(req.ifname, rate);
105 if (delete || rate > 0) {
108 rate = 0;
110 depth = size_bucket(req.ifname, rate);
112 req.tb_prof.rate = rate
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_display.c | 50 int rate, rate_x2; local
53 rate = clk_round_rate(clkp, new_rate);
54 diff = abs(new_rate - rate);
59 if (rate == 0 && rate_x2 == 0)
84 int rate, rate_x2; local
87 rate = clk_round_rate(clkp, try_rate);
88 diff = abs(try_rate - rate);
95 return rate;
114 int rate, diff; local
119 rate = parent_rate * d / m
[all...] |
| sunxi_ccu_fixed_factor.c | 68 sunxi_ccu_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)
76 return clk_set_rate(clkp_parent, rate);
81 struct sunxi_ccu_clk *clk, u_int rate)
88 rate *= fixed_factor->div;
89 rate /= fixed_factor->mult;
91 return sunxi_ccu_fixed_factor_set_parent_rate(clkp, rate);
|
| sunxi_ccu_fractional.c | 67 u_int rate, m; local
77 rate = clk_get_rate(clkp_parent);
78 if (rate == 0)
84 rate = rate / (__SHIFTOUT(val, fractional->prediv) + 1);
86 rate = rate / fractional->prediv_val;
101 return rate * m;
111 u_int m, rate; local
156 rate = parent_rate * m
190 u_int m, rate; local
[all...] |
| sunxi_ccu_nm.c | 67 u_int rate, n, m; local
77 rate = clk_get_rate(clkp_parent);
78 if (rate == 0)
98 return rate / n / m;
108 u_int n, m, pindex, rate; local
120 rate = clk_get_rate(clkp_parent);
121 if (rate == 0)
128 * Shouldn't have to set parent to get potential parent clock rate
145 rate = parent_rate / (1 << n) / (m + 1);
147 rate = parent_rate / (n + 1) / (m + 1)
[all...] |
| /src/sys/arch/arm/amlogic/ |
| meson_clk_fixed_factor.c | 68 meson_clk_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)
76 return clk_set_rate(clkp_parent, rate);
81 struct meson_clk_clk *clk, u_int rate)
88 rate *= fixed_factor->div;
89 rate /= fixed_factor->mult;
91 return meson_clk_fixed_factor_set_parent_rate(clkp, rate);
|
| meson_clk_div.c | 45 u_int rate, ratio; local
55 rate = clk_get_rate(clkp_parent);
56 if (rate == 0)
69 return rate >> ratio;
73 return rate / ((ratio + 1) * 2);
75 return rate / (ratio + 1);
|
| /src/sys/arch/arm/nxp/ |
| imx_ccm_fixed_factor.c | 68 imx_ccm_fixed_factor_set_parent_rate(struct clk *clkp, u_int rate)
76 return clk_set_rate(clkp_parent, rate);
81 struct imx_ccm_clk *clk, u_int rate)
88 rate *= fixed_factor->div;
89 rate /= fixed_factor->mult;
91 return imx_ccm_fixed_factor_set_parent_rate(clkp, rate);
|
| /src/sys/arch/i386/stand/lib/ |
| comio_direct.c | 183 int rate, err; local
190 /* Try to determine the current baud rate */
191 rate = inb(combase + com_dlbl) | inb(combase + com_dlbh) << 8;
192 if (rate == 0)
193 rate = RATE_9600;
194 speed = divrnd((COM_FREQ / 16), rate);
202 rate = comspeed(speed);
203 outb(combase + com_dlbl, rate);
204 outb(combase + com_dlbh, rate >> 8);
|
| /src/external/bsd/zstd/dist/tests/ |
| rateLimiter.py | 13 # Rate limiter, replacement for pv
14 # this rate limiter does not "catch up" after a blocking period
22 rate = float(sys.argv[1]) * MB variable
32 to_read = max(int(rate * (now - start)), 1)
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/ |
| stm32h7-pinctrl.dtsi | 53 slew-rate = <0>;
68 slew-rate = <2>;
80 slew-rate = <3>;
93 slew-rate = <3>;
99 slew-rate = <3>;
121 slew-rate = <3>;
148 slew-rate = <3>;
161 slew-rate = <3>;
167 slew-rate = <3>;
192 slew-rate = <2>
[all...] |
| /src/external/bsd/ntp/dist/adjtimed/ |
| adjtimed.c | 23 * This daemon adjusts the rate of the system clock a la BSD's adjtime().
265 * Default clock rate (old_tick).
269 #define TICK_ADJ 5 /* standard adjustment rate, microsec/tick */
281 register long rate, dt, leftover; local
292 rate = dt;
295 * Apply a slew rate of slew_rate over a period of dt/slew_rate seconds.
298 rate = slew_rate;
300 rate = -slew_rate;
307 * using the modified clock rate rather than an assumed nominal clock rate,
368 long rate, mask; local
[all...] |
| /src/sys/arch/hpcmips/stand/lcboot/ |
| com.c | 137 int rate; local
139 /* enable divisor latch access and set bit rate */
141 rate = 10; /* 115200bps with VRCOM_FREQ */
142 REGWRITE_1(VR4181_SIU_ADDR, com_dlbl, rate);
143 REGWRITE_1(VR4181_SIU_ADDR, com_dlbh, rate >> 8);
|
| /src/tests/lib/libossaudio/ |
| t_ossaudio.c | 48 int fd, channels, fmt, rate; local
196 rate = 8000;
197 if (ioctl(fd, SNDCTL_DSP_SPEED, &rate) < 0)
202 ATF_REQUIRE_EQ(rate, (int)info.play.sample_rate);
204 rate = 32000;
205 if (ioctl(fd, SNDCTL_DSP_SPEED, &rate) < 0)
211 ATF_REQUIRE_EQ(rate, (int)info.play.sample_rate);
213 rate = 44100;
214 if (ioctl(fd, SNDCTL_DSP_SPEED, &rate) < 0)
220 ATF_REQUIRE_EQ(rate, (int)info.play.sample_rate)
[all...] |
| /src/external/gpl3/gdb/dist/gdb/ |
| ser-unix.c | 77 static int rate_to_code (int rate);
78 static void hardwire_setbaudrate (struct serial *scb, int rate);
264 int rate; member in struct:__anon425
450 rate_to_code (int rate)
454 for (i = 0; baudtab[i].rate != -1; i++)
457 if (rate == baudtab[i].rate)
462 if (rate < baudtab[i].rate)
467 error (_("Invalid baud rate %d.
[all...] |
| /src/external/gpl3/gdb.old/dist/gdb/ |
| ser-unix.c | 53 static int rate_to_code (int rate);
54 static void hardwire_setbaudrate (struct serial *scb, int rate);
239 int rate; member in struct:__anon20741
401 rate_to_code (int rate)
405 for (i = 0; baudtab[i].rate != -1; i++)
408 if (rate == baudtab[i].rate)
413 if (rate < baudtab[i].rate)
417 error (_("Invalid baud rate %d.
[all...] |
| /src/sys/arch/arm/fdt/ |
| a9ptmr_fdt.c | 98 uint32_t rate = clk_get_rate(sc->sc_clk); local
100 prop_dictionary_set_uint32(dict, "frequency", rate);
163 uint32_t rate; local
165 rate = clk_get_rate(sc->sc_clk);
166 prop_dictionary_set_uint32(dict, "frequency", rate);
168 a9ptmr_update_freq(rate);
|
| /src/sys/arch/riscv/starfive/ |
| jh7100_gmac.c | 68 u_int rate = clk_get_rate(jheth_sc->sc_clk_tx); local
71 rate = 2500000;
74 rate = 25000000;
77 rate = 125000000;
83 int error = clk_set_rate(jheth_sc->sc_clk_tx, rate);
85 aprint_error_dev(jheth_sc->sc_dev, "failed to set TX rate %u",
86 rate);
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru_arm.c | 65 struct rk_cru_clk *clk, u_int rate)
74 if (arm->rates == NULL || rate == 0)
78 if (arm->rates[i].rate == rate) {
96 const u_int parent_rate = arm_rate->rate / arm_rate->div;
119 struct rk_cru_clk *clk, u_int rate)
129 if (arm->cpurates == NULL || rate == 0)
133 if (arm->cpurates[i].rate == rate) {
153 error = clk_set_rate(&main_parent->base, rate);
[all...] |
