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  /src/crypto/external/apache2/openssl/lib/libcrypto/arch/riscv64/
sha512-riscv64-zvkb-zvknhb.S 29 # Setup v0 mask for the vmerge to replace the first word (idx==0) in key-scheduling.
sha256-riscv64-zvkb-zvknha_or_zvknhb.S 63 # Setup v0 mask for the vmerge to replace the first word (idx==0) in key-scheduling.
  /src/external/lgpl3/gmp/dist/mpn/x86/p6/
lshsub_n.asm 35 C (1) The loop is not scheduled in any way, and scheduling attempts have not
36 C improved speed on P6/13. Presumably, the K7 will want scheduling, if it
mode1o.asm 129 C and this is the measured speed. No special scheduling is necessary, out
aorsmul_1.asm 86 C the same, but there's just a few scheduling tweaks in the setups and the
bdiv_q_1.asm 190 C and this is the measured speed. No special scheduling is necessary, out
dive_1.asm 143 C and this is the measured speed. No special scheduling is necessary, out
  /src/crypto/external/apache2/openssl/dist/providers/implementations/ciphers/
cipher_aes_hw_rv64i.inc 77 * All Zvkned-based implementations use the same `encrypt-key` scheduling
  /src/external/lgpl3/gmp/dist/mpn/arm/v7a/cora15/
mul_1.asm 42 C This runs well on A15 but very poorly on A9. By scheduling loads and adds
  /src/external/lgpl3/gmp/dist/mpn/powerpc64/mode64/p9/
addmul_2.asm 41 C * No local scheduling for performance tweaking has been done.
42 C * Decrease load scheduling!
mul_2.asm 41 C * No local scheduling for performance tweaking has been done.
42 C * Decrease load scheduling!
  /src/external/lgpl3/gmp/dist/mpn/x86/k7/mmx/
copyi.asm 49 C one cycle, so perhaps some scheduling is needed to ensure it's a
  /src/external/lgpl3/gmp/dist/mpn/x86/k7/
mode1o.asm 141 C special scheduling is required.
  /src/external/lgpl3/gmp/dist/mpn/x86_64/core2/
popcount.asm 60 C * Consider doing some instruction scheduling.
hamdist.asm 60 C * Consider doing some instruction scheduling.
  /src/external/lgpl3/gmp/dist/mpn/x86_64/fastsse/
lshift.asm 59 C With 2-way unrolling but no scheduling we reach 1.5 c/l on K10 and 2 c/l on
lshiftc.asm 60 C With 2-way unrolling but no scheduling we reach 1.5 c/l on K10 and 2 c/l on
  /src/external/lgpl3/gmp/dist/mpn/ia64/
lorrshift.asm 40 C have a latency of 4 (on Itanium) or 3 (on Itanium 2). Poor scheduling of
43 C The ld8 scheduling should probably be decreased to make the function smaller.
lshiftc.asm 40 C have a latency of 4 (on Itanium) or 3 (on Itanium 2). Poor scheduling of
43 C The ld8 scheduling should probably be decreased to make the function smaller.
  /src/external/gpl3/gcc/dist/gcc/config/nds32/
nds32-pipelines-auxiliary.cc 40 namespace scheduling { namespace in namespace:nds32
456 } // namespace scheduling
462 using namespace nds32::scheduling;
  /src/external/gpl3/gcc.old/dist/gcc/config/nds32/
nds32-pipelines-auxiliary.cc 40 namespace scheduling { namespace in namespace:nds32
456 } // namespace scheduling
462 using namespace nds32::scheduling;
  /src/external/lgpl3/gmp/dist/mpn/sparc32/v9/
addmul_1.asm 48 C Unrolling would allow deeper scheduling which could improve speed for L2
mul_1.asm 48 C Unrolling would allow deeper scheduling which could improve speed for L2
submul_1.asm 48 C Unrolling would allow deeper scheduling which could improve speed for L2
  /src/external/lgpl3/gmp/dist/mpn/x86/pentium/mmx/
mul_1.asm 241 C The scheduling here is quite tricky, since so many instructions have

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